JPH08228075A - Manufacture of substrate - Google Patents

Manufacture of substrate

Info

Publication number
JPH08228075A
JPH08228075A JP5805495A JP5805495A JPH08228075A JP H08228075 A JPH08228075 A JP H08228075A JP 5805495 A JP5805495 A JP 5805495A JP 5805495 A JP5805495 A JP 5805495A JP H08228075 A JPH08228075 A JP H08228075A
Authority
JP
Japan
Prior art keywords
solder
hole
substrate
flux
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5805495A
Other languages
Japanese (ja)
Inventor
Koji Tateishi
幸治 立石
Hideo Kawakami
秀雄 川上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP5805495A priority Critical patent/JPH08228075A/en
Publication of JPH08228075A publication Critical patent/JPH08228075A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3478Applying solder preforms; Transferring prefabricated solder patterns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE: To make each conductive pattern of the top face and underside of a substrate have a sure continuity with high reliability, and to connect the substrate to another mounting substrate without generating defective connection. CONSTITUTION: A through-hole 4 communicating with an underside from a top face is formed, the underside opening section 5 of the through-hole 4 is closed by a receiving member 6, flux 8 is injected from the top-face opening section 7 of the through-hole 4, solder powder 9 is injected from the top-face opening section 7, and flux 8 and powder solder 9 are made to reflow in the manufacture of a substrate. Spherical solder is loaded in the top-face opening section 7 after the injection process of powder solder 9, and flux 8, powder solder 9 and spherical solder are made to reflow in the manufacture of the substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業状の利用分野】本発明は、半導体装置用基板の製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device substrate.

【0002】[0002]

【従来の技術】従来、絶縁性基板材の上面および下面に
それぞれ形成した導電パターンをスルーホールを介して
導通させた基板、例えばプリント基板がある。また、半
導体装置の高密度化、多ピン化及び実装性の向上を図る
ものとして、上面および下面に導電パターンを形成した
半導体素子搭載基板がある。
2. Description of the Related Art Conventionally, there is a substrate, for example, a printed circuit board, in which conductive patterns formed on the upper surface and the lower surface of an insulating substrate material are electrically connected through through holes. Further, as an attempt to increase the density, increase the number of pins, and improve the mountability of a semiconductor device, there is a semiconductor element mounting substrate having conductive patterns formed on the upper and lower surfaces.

【0003】これら基板の上面と下面の導電パターンの
導通は、当該両導電パターンに通じたスルーホールの内
周面に銅メッキ、又は銅メッキした後に半田メッキを施
すことにより行われている。
Conduction between the conductive patterns on the upper surface and the lower surface of these substrates is carried out by plating copper on the inner peripheral surfaces of the through holes communicating with the conductive patterns, or by plating with copper and then solder plating.

【0004】[0004]

【この発明が解決しようとする課題】前記基板の導通で
は、メッキされる基板材が絶縁性であるので密着性が悪
く、メッキ剥離を生じることがあり信頼性が低下する。
なかでも基板材がポリミイドテープ等の半導体素子搭載
基板では前記メッキ剥離が多発し問題である。
In the conduction of the substrate, since the substrate material to be plated is insulative, the adhesion is poor and the plating may be peeled off, resulting in a decrease in reliability.
In particular, when the substrate material is a semiconductor element mounting substrate such as a polymide tape, the plating peeling occurs frequently, which is a problem.

【0005】前記メッキ剥離の防止には、スルーホール
の内周面へのメッキに先立って複雑で多工程からなる前
処理が必要となり、作業性及び生産性に問題を生じ、ま
たコスト高になる。
In order to prevent the peeling of the plating, a complicated and multi-step pretreatment is required prior to the plating on the inner peripheral surface of the through hole, which causes a problem in workability and productivity, and also causes an increase in cost. .

【0006】前記上面と下面に導電パターンを形成した
基板は、他の実装基板の配線端子に接続し組立てられ
る。その接続のために基板には半田ボールが実装面側の
スルーホール上に設けられ、該半田ボールに加熱作用を
与えて溶融させ前記配線端子と接続しているが、前記加
熱時にスルーホール内の中空部に該半田ボールが流れ込
む場合があり、半田ボールの高さ不良や基板と実装基板
の接続不良が生じることがある。
The board having conductive patterns formed on the upper and lower surfaces is connected to wiring terminals of another mounting board and assembled. For the connection, solder balls are provided on the through holes on the mounting surface side of the board for the connection, and the solder balls are heated to melt and connect to the wiring terminals. The solder balls may flow into the hollow portion, which may result in defective height of the solder balls or defective connection between the substrate and the mounting substrate.

【0007】また、該半田ボールは前記基板との接触面
積が小さく接着強度が低いため基板から半田ボールが取
れてしまうことがあった。
Further, since the solder ball has a small contact area with the substrate and has a low adhesive strength, the solder ball may be removed from the substrate.

【0008】本発明は、上面と下面にそれぞれ形成した
導電パターンの導通が確実に信頼性高くなされ、さらに
他の実装基板に接続不良を生じることなく接続できる基
板の製造方法を目的とする。
It is an object of the present invention to provide a method of manufacturing a substrate in which the conductive patterns formed on the upper surface and the lower surface are surely highly conductive, and can be connected to another mounting board without causing a connection failure.

【0009】[0009]

【問題を解決するための手段】本発明の要旨は、上面か
ら下面に連通するスルーホールを設け、当該スルーホー
ル内に導電性物質を充填してなる基板の製造方法におい
て、前記上面もしくは下面のいずれか一方の面を閉塞し
て前記スルーホール内に半田ぬれ性を良くするフラック
スを注入するフラックス注入工程と、フラックスが注入
された前記スルーホールに粉末状の半田を充填する半田
粉末充填工程と、フラックスおよび粉末状の半田を加熱
するリフロー工程を経てなる基板の製造方法にある。
SUMMARY OF THE INVENTION The gist of the present invention is to provide a through hole communicating from the upper surface to the lower surface and to fill the through hole with a conductive substance. A flux injecting step of injecting a flux that improves solder wettability into the through hole by closing one of the surfaces, and a solder powder filling step of filling the through hole into which the flux is injected with powdered solder. , A method of manufacturing a substrate through a reflow step of heating flux and powdered solder.

【0010】また、他の要旨は、上面から下面に連通す
るスルーホールを設け、当該スルーホール内に導電性物
質を充填してなる基板の製造方法において、前記上面も
しくは下面のいずれか一方の面を閉塞して前記スルーホ
ール内に半田ぬれ性を良くするフラックスを注入するフ
ラックス注入工程と、フラックスが注入された前記スル
ーホールに粉末状の半田を充填する半田粉末充填工程
と、閉塞されない面のスルーホールに球状半田を搭載す
る工程とフラックスおよび粉末状の半田を加熱するリフ
ロー工程を経てなる基板の製造方法にある。
Another aspect is that in a method of manufacturing a substrate in which a through hole communicating from the upper surface to the lower surface is provided and a conductive substance is filled in the through hole, either one of the upper surface and the lower surface is provided. A flux injection step of injecting a flux that closes the through hole to improve solder wettability, a solder powder filling step of filling the through hole into which the flux is injected with a powdered solder, and a non-closed surface It is a method of manufacturing a substrate that includes a step of mounting spherical solder in a through hole and a reflow step of heating flux and powdery solder.

【0011】[0011]

【作用】本発明の基板の製造方法は、フラックスおよび
半田粉末をスルーホールに充填しリフローするので、充
填物の体積の減少を抑えることができるとともにボイド
の発生を防ぐことができ、上面と下面の導通が確実に信
頼性高くなされる。
In the substrate manufacturing method of the present invention, since the flux and the solder powder are filled in the through holes and the reflow is performed, it is possible to suppress the decrease in the volume of the filling material and prevent the generation of voids. Is surely reliable.

【0012】さらには、スルーホールの上面もしくは下
面の一方に確実に安定した高さの半田ボールを搭載する
ことができ、他の実装基板との導通が確実に信頼性高く
なされる。
Furthermore, a solder ball having a stable height can be surely mounted on one of the upper surface and the lower surface of the through hole, and conduction with another mounting board can be surely made highly reliable.

【0013】[0013]

【実施例】本発明について半導体素子搭載に使用される
基板の製造方法を図面を参照して詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a substrate used for mounting a semiconductor device according to the present invention will be described in detail with reference to the drawings.

【0014】まず、第1の実施例は、図1に示すように
基材1の上面および下面にエッチングにより上面導電パ
ターン2および下面導電パターン3を形成し、エッチン
グによりスルーホール4を上面導電パターン2および下
面導電パターン3に連通するよう形成し、スルーホール
4の下面開口部5を受け部材6で閉塞し、スルーホール
4の上面開口部7よりフラックス8を注入し、さらに上
面開口部7より半田粉末9を注入して当該スルーホール
4の上面上方まで充填し、受け部材6を直接または間接
的に加熱しフラックス8および半田粉末9をリフロー
し、受け部材6を取りはずし基板を製造する方法であ
る。
First, in the first embodiment, as shown in FIG. 1, the upper surface conductive pattern 2 and the lower surface conductive pattern 3 are formed on the upper surface and the lower surface of the base material 1 by etching, and the through holes 4 are formed by etching. 2 and the lower surface conductive pattern 3 are formed, the lower surface opening 5 of the through hole 4 is closed by the receiving member 6, the flux 8 is injected through the upper surface opening 7 of the through hole 4, and further through the upper surface opening 7. By injecting the solder powder 9 to fill the upper surface of the through hole 4 and directly or indirectly heating the receiving member 6 to reflow the flux 8 and the solder powder 9, the receiving member 6 is removed, and a substrate is manufactured. is there.

【0015】第2の実施例は、図2に示すように基材1
の上面および下面にエッチングにより上面導電パターン
2および下面導電パターン3を形成し、エッチングによ
りスルーホール4を上面導電パターン2および下面導電
パターン3に連通するよう形成し、スルーホール4の上
面開口部7に半田レジスト10を形成し、スルーホール
4の下面開口部5を受け部材6で閉塞し、スルーホール
4の上面開口部7よりフラックス8を注入し、さらに上
面開口部7より半田粉末9を注入して当該スルーホール
4の上面上方まで充填し、スルーホール4の上面開口部
7に球状半田11を搭載し、受け部材6を直接または間
接的に加熱しフラックス8および半田粉末9および球状
半田10をリフローし、受け部材6を取りはずし基板を
製造する方法である。
In the second embodiment, as shown in FIG.
Upper surface conductive pattern 2 and lower surface conductive pattern 3 are formed on the upper surface and lower surface of the through hole 4, and through hole 4 is formed by etching so as to communicate with upper surface conductive pattern 2 and lower surface conductive pattern 3, and upper surface opening 7 of through hole 4 is formed. A solder resist 10 is formed on the through hole 4, a lower surface opening 5 of the through hole 4 is closed by a receiving member 6, a flux 8 is injected from an upper surface opening 7 of the through hole 4, and a solder powder 9 is further injected from an upper surface opening 7. The upper surface opening 7 of the through hole 4 is filled with the spherical solder 11 and the receiving member 6 is directly or indirectly heated to heat the flux 8 and the solder powder 9 and the spherical solder 10. Is reflowed, the receiving member 6 is removed, and a substrate is manufactured.

【0016】第3の実施例は、図3に示すように基材1
の上面および下面にエッチングにより上面導電パターン
2および下面導電パターン3を形成し、エッチングによ
りスルーホール4を上面導電パターン2および下面導電
パターン3に連通するよう形成し、スルーホール4の上
面開口部7に半田レジスト10を形成し、スルーホール
4の下面開口部5を受け部材6で閉塞し、スルーホール
4の上面開口部7よりフラックス8を注入し、さらに上
面開口部7より半田粉末9を注入して当該スルーホール
4の上面上方まで充填し、受け部材6を直接または間接
的に加熱しフラックス8および半田粉末9をリフロー
し、リフローした充填半田12の上に球状半田11を搭
載し、該充填半田12および球状半田11をリフロー
し、受け部材6を取りはずし基板を製造する方法であ
る。
In the third embodiment, as shown in FIG.
Upper surface conductive patterns 2 and lower surface conductive patterns 3 are formed on the upper and lower surfaces of the through holes 4, and through holes 4 are formed by etching so as to communicate with the upper surface conductive patterns 2 and the lower surface conductive patterns 3. A solder resist 10 is formed on the through hole 4, a lower surface opening 5 of the through hole 4 is closed by a receiving member 6, a flux 8 is injected from an upper surface opening 7 of the through hole 4, and a solder powder 9 is further injected from an upper surface opening 7. Then, the upper surface of the through hole 4 is filled up, the receiving member 6 is directly or indirectly heated to reflow the flux 8 and the solder powder 9, and the spherical solder 11 is mounted on the reflowed filled solder 12. In this method, the filling solder 12 and the spherical solder 11 are reflowed, the receiving member 6 is removed, and a substrate is manufactured.

【0017】この製造方法によれば、半田粉末9を充填
する時半田粉末9を上面開口部7よりも高く盛り上げる
ことができ、充填半田12を上面方向に高く形成するこ
とができるので半田ボール部13の高さを高くすること
ができ、他の実装基板との接続がさらに確実になる。
According to this manufacturing method, when the solder powder 9 is filled, the solder powder 9 can be raised higher than the upper surface opening portion 7, and the filled solder 12 can be formed higher in the upper surface direction, so that the solder ball portion can be formed. The height of 13 can be increased, and the connection with other mounting boards is further ensured.

【0018】第4の実施例は、図4に示すように、基材
1の上面および下面にエッチングにより上面導電パター
ン2および下面導電パターン3を形成し、エッチングに
よりスルーホール4を上面導電パターン2および下面導
電パターン3に連通するよう形成し、スルーホール4の
上面開口部7に半田レジスト10を形成し、スルーホー
ル4の下面開口部5を受け部材6で閉塞し、上面開口部
7に半田粉末保持治具14を搭載し、該半田粉末保持治
具14の上面開口部15よりフラックス8を注入し、さ
らに半田粉末9を充填して当該半田粉末保持治具14の
上面上方まで充填し、受け部材6を直接または間接的に
加熱しフラックス8および半田粉末9をリフローすると
ともに、リフロー中に半田粉末9が溶融した段階で半田
保持治具14を取りはずし、受け部材6を取りはずすこ
とを特徴とする基板の製造方法である。
In the fourth embodiment, as shown in FIG. 4, an upper surface conductive pattern 2 and a lower surface conductive pattern 3 are formed on the upper surface and the lower surface of a base material 1 by etching, and the through holes 4 are formed by etching. And the lower surface conductive pattern 3, and a solder resist 10 is formed in the upper surface opening 7 of the through hole 4, the lower surface opening 5 of the through hole 4 is closed by the receiving member 6, and the upper surface opening 7 is soldered. The powder holding jig 14 is mounted, the flux 8 is injected from the upper surface opening 15 of the solder powder holding jig 14, and the solder powder 9 is further filled up to above the upper surface of the solder powder holding jig 14. The flux 8 and the solder powder 9 are reflowed by directly or indirectly heating the receiving member 6, and the solder holding jig 14 is removed at the stage when the solder powder 9 is melted during the reflow. Remove a method of manufacturing a substrate, characterized in that the receiving member 6 removed.

【0019】この方法によれば、球状半田11を必要と
せず、工程を簡略化することができるとともに半田ボー
ル13の高さを高くすることができ、他の実装基板との
接続が更に確実になる。
According to this method, the spherical solder 11 is not required, the process can be simplified, and the height of the solder ball 13 can be increased, so that the connection with another mounting substrate can be made more reliable. Become.

【0020】実施例2、実施例3および実施例4におい
て上面および下面にそれぞれ上面導電パターン2および
下面導電パターン3を形成したがこれは任意であり、図
5に示すように上面には導電パターンは形成せず他の実
装基板との導通を行う半田ボール部13のみを形成して
もよい。
In the second, third and fourth embodiments, the upper conductive pattern 2 and the lower conductive pattern 3 are formed on the upper surface and the lower surface, respectively, but this is optional. As shown in FIG. 5, the conductive pattern is formed on the upper surface. It is also possible to form only the solder ball portion 13 that conducts with another mounting board without forming the solder ball portion.

【0021】以上に述べた実施例において、受け部材6
で下面開口部5を覆い、さらには受け部材6を直接また
は間接的に加熱することによりフラックス8および半田
粉末9もしくはフラックス8および半田粉末9および球
状半田11をリフローしたがこれは任意であり、図6に
示すように、スルーホール4を覆うように下面導電パタ
ーン16を形成し、該下面導電パターン16を直接また
は間接的に加熱することによりフラックス8および半田
粉末9もしくはフラックス8および半田粉末9および球
状半田11をリフローしてもよい。
In the embodiment described above, the receiving member 6
The bottom opening 5 is covered with and the flux 8 and the solder powder 9 or the flux 8 and the solder powder 9 and the spherical solder 11 are reflowed by directly or indirectly heating the receiving member 6, but this is optional. As shown in FIG. 6, a lower surface conductive pattern 16 is formed so as to cover the through holes 4, and the lower surface conductive pattern 16 is directly or indirectly heated to form the flux 8 and the solder powder 9 or the flux 8 and the solder powder 9. The spherical solder 11 may be reflowed.

【0022】この方法によれば、受け部材6の取り付け
および取りはずしの工程を省くことができ製造工程の簡
略化になる。
According to this method, the steps of attaching and detaching the receiving member 6 can be omitted and the manufacturing process can be simplified.

【0023】また、以上に述べた実施例において下面よ
りリフローを行ないながらフラックス8および半田粉末
9を充填することにより、ボイドの発生をさらに防ぐこ
とができ、上面と下面の導通もさらに確実になる。
Further, by filling the flux 8 and the solder powder 9 while performing reflow from the lower surface in the above-described embodiment, the generation of voids can be further prevented, and the conduction between the upper surface and the lower surface is further ensured. .

【0024】[0024]

【発明の効果】本発明の基板の製造方法によれば、前述
のように半田粉末およびフラックスを使用するので、リ
フロー工程における体積の減少が少なく、スルーホール
内には十分な半田が充填されるため、基板の上面および
下面に設けられた導電パターンの導通不良を防止するこ
とができ、製造歩留りを格段に向上させることが可能と
なる。
According to the board manufacturing method of the present invention, since the solder powder and the flux are used as described above, the volume reduction in the reflow step is small, and the through holes are sufficiently filled with solder. Therefore, it is possible to prevent conduction defects of the conductive patterns provided on the upper surface and the lower surface of the substrate, and it is possible to significantly improve the manufacturing yield.

【0025】さらに、スルーホールの上面もしくは下面
の一方の面に安定した高さの半田ボールを形成できるた
め、他の実装基板に接続不良を生じることなく接続可能
である。
Furthermore, since solder balls having a stable height can be formed on one of the upper surface and the lower surface of the through hole, connection can be made to other mounting boards without causing connection failure.

【0026】[0026]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明における基板の製造方法の第1の実施例
を説明するための図である。
FIG. 1 is a diagram for explaining a first embodiment of a substrate manufacturing method according to the present invention.

【図2】本発明における基板の製造方法の第2の実施例
を説明するための図である。
FIG. 2 is a diagram for explaining a second embodiment of the method of manufacturing a substrate according to the present invention.

【図3】本発明における基板の製造方法の第3の実施例
を説明するための図である。
FIG. 3 is a drawing for explaining the third embodiment of the method for manufacturing a substrate according to the present invention.

【図4】本発明における基板の製造方法の第4の実施例
を説明するための図である。
FIG. 4 is a drawing for explaining the fourth embodiment of the method of manufacturing a substrate according to the present invention.

【図5】本発明における基板の製造方法の実施例の一部
を説明するための図である。
FIG. 5 is a drawing for explaining a part of the embodiment of the method for manufacturing a substrate according to the present invention.

【図6】本発明における基板の製造方法の実施例の一部
を説明するための図である。
FIG. 6 is a view for explaining a part of the embodiment of the method for manufacturing the substrate according to the present invention.

【符号の説明】[Explanation of symbols]

1 基材 2 上面導電パターン 3 下面導電パターン 4 スルーホール 5 下面開口部 6 受け部材 7 上面開口部 8 フラックス 9 半田粉末 10 半田レジスト 11 球状半田 12 充填半田 13 半田ボール部 14 半田粉末保持治具 15 上面開口部 16 下面導電パターン DESCRIPTION OF SYMBOLS 1 Base material 2 Upper surface conductive pattern 3 Lower surface conductive pattern 4 Through hole 5 Lower surface opening 6 Receiving member 7 Upper surface opening 8 Flux 9 Solder powder 10 Solder resist 11 Spherical solder 12 Filled solder 13 Solder ball part 14 Solder powder holding jig 15 Upper surface opening 16 Lower surface conductive pattern

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 上面から下面に連通するスルーホールを
設け、当該スルーホール内に導電性物質を充填してなる
基板の製造方法において、前記上面もしくは下面のいず
れか一方の面を閉塞して前記スルーホール内にフラック
スを注入するフラックス注入工程と、フラックスが注入
された前記スルーホールに粉末状の半田を充填する半田
粉末充填工程と、フラックスおよび粉末状の半田を加熱
するリフロー工程を経てなる基板の製造方法。
1. A method of manufacturing a substrate in which a through hole communicating from the upper surface to the lower surface is provided, and the through hole is filled with a conductive material, wherein either one of the upper surface and the lower surface is closed and the through hole is closed. Substrate obtained through a flux injecting step of injecting a flux into the through hole, a solder powder filling step of filling the through hole into which the flux is injected with a powdery solder, and a reflow step of heating the flux and the powdery solder. Manufacturing method.
【請求項2】 上面から下面に連通するスルーホールを
設け、当該スルーホール内に導電性物質を充填してなる
基板の製造方法において、前記上面もしくは下面のいず
れか一方の面を閉塞して前記スルーホール内にフラック
スを注入するフラックス注入工程と、フラックスが注入
された前記スルーホールに粉末状の半田を充填する半田
粉末充填工程と、閉塞されない面のスルーホールに球状
半田を搭載する工程とフラックスおよび粉末状の半田お
よび球状半田を加熱するリフロー工程を経てなる基板の
製造方法。
2. A method of manufacturing a substrate in which a through hole communicating from the upper surface to the lower surface is provided, and the through hole is filled with a conductive substance, wherein either one of the upper surface and the lower surface is closed. Flux injection step of injecting flux into the through hole, solder powder filling step of filling the through hole into which the flux is injected with powdered solder, and step of mounting spherical solder in the through hole of the surface not blocked and flux And a method of manufacturing a substrate that undergoes a reflow step of heating powdered solder and spherical solder.
JP5805495A 1995-02-21 1995-02-21 Manufacture of substrate Pending JPH08228075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5805495A JPH08228075A (en) 1995-02-21 1995-02-21 Manufacture of substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5805495A JPH08228075A (en) 1995-02-21 1995-02-21 Manufacture of substrate

Publications (1)

Publication Number Publication Date
JPH08228075A true JPH08228075A (en) 1996-09-03

Family

ID=13073207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5805495A Pending JPH08228075A (en) 1995-02-21 1995-02-21 Manufacture of substrate

Country Status (1)

Country Link
JP (1) JPH08228075A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003005789A1 (en) * 2001-07-05 2003-01-16 Nitto Denko Corporation Method for producing multilayer wiring circuit board
KR100645541B1 (en) * 2005-08-30 2006-11-14 삼성전자주식회사 Apparatus and method for printing solder paste
JP2011086694A (en) * 2009-10-14 2011-04-28 Sumitomo Bakelite Co Ltd Bump forming method and wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003005789A1 (en) * 2001-07-05 2003-01-16 Nitto Denko Corporation Method for producing multilayer wiring circuit board
US6851599B2 (en) 2001-07-05 2005-02-08 Nitto Denko Corporation Method for producing multilayer wiring circuit board
KR100645541B1 (en) * 2005-08-30 2006-11-14 삼성전자주식회사 Apparatus and method for printing solder paste
JP2011086694A (en) * 2009-10-14 2011-04-28 Sumitomo Bakelite Co Ltd Bump forming method and wiring board

Similar Documents

Publication Publication Date Title
US5875102A (en) Eclipse via in pad structure
US6400018B2 (en) Via plug adapter
US6358630B1 (en) Soldering member for printed wiring boards
JPH0410240B2 (en)
JPH0945805A (en) Wiring board, semiconductor device, method for removing the semiconductor device from wiring board, and manufacture of semiconductor device
US5541368A (en) Laminated multi chip module interconnect apparatus
JP2000068409A (en) Manufacture of semiconductor device, circuit board and the semiconductor device
US20120043371A1 (en) Wiring substrate manufacturing method
US20120048914A1 (en) Wiring substrate manufacturing method
WO2000005936A1 (en) Hybrid solder ball and pin grid array circuit board interconnect system and method
JP2717313B2 (en) Manufacturing method of electronic component mounting board
JP2004273990A (en) Electronic circuit board and its production
JPH08228075A (en) Manufacture of substrate
US6528873B1 (en) Ball grid assembly with solder columns
JPH0685425A (en) Board for mounting electronic part thereon
JPH08213748A (en) Board and manufacture thereof
JPH08340164A (en) Surface mounting structure of bga type package
JPH0223644A (en) Manufacture of mounting board equipped with conduction pin
JPH098424A (en) Printed wiring board and its manufacturing method
JP2001148441A (en) Semiconductor package and its manufacturing method
JPH03262186A (en) Printed wiring board
JPH0766318A (en) Semiconductor device
JP2799456B2 (en) Electronic component mounting substrate and method of manufacturing the same
JPH10335388A (en) Ball grid array
JPH11251477A (en) Semiconductor package, semiconductor device, and their manufacturing method