JPH06169153A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH06169153A
JPH06169153A JP32101492A JP32101492A JPH06169153A JP H06169153 A JPH06169153 A JP H06169153A JP 32101492 A JP32101492 A JP 32101492A JP 32101492 A JP32101492 A JP 32101492A JP H06169153 A JPH06169153 A JP H06169153A
Authority
JP
Japan
Prior art keywords
pad
solder
wiring board
pads
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32101492A
Other languages
Japanese (ja)
Inventor
Kiyohisa Hasegawa
清久 長谷川
Toru Nohara
徹 野原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP32101492A priority Critical patent/JPH06169153A/en
Publication of JPH06169153A publication Critical patent/JPH06169153A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Abstract

PURPOSE:Not only to prevent a semiconductor package from falling off from a wiring board due to external shocks or oscillations but also to restrain solder bridges from being produced on the wiring board even if solder increases in amount. CONSTITUTION:An electronic component mounting pad 3b located at the outermost end of a pad row is set larger in dimensions in both a lateral and a longitudinal direction than the other electronic component mounting pads 3a. Therefore, the pad 3b is larger than the pad 3a in area, and when an SOP 4 is mounted, cream solder applied onto the pad 3b increases in amount, so that a lead 5 is firmly connected to the pad 3b. Even if solder is much applied onto the pad 3b, as the pad 3b is large in area, solder is restrained from flowing out of it, and consequently a solder bridge is hardly produced between the adjacent pads 3a and 3b at the time of reflow.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント配線板に係
り、詳しくは、表面実装用の電子部品を搭載するための
パッドが形成されたプリント配線板に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly to a printed wiring board having pads for mounting surface mounting electronic components.

【0002】[0002]

【従来の技術】電子機器の小型化、高機能化に伴いSO
P(スモール・アウトライン・パッケージ)、QFP
(クワッド・フラット・パッケージ)等の半導体パッケ
ージのプリント配線板への表面実装化が進んでいる。こ
のプリント配線板においては、例えば図5に示すよう
に、絶縁基板20の表面に複数の部品搭載用パッド(以
下、単にパッドという)21が並列かつ等間隔に形成さ
れている。そのパッド21には配線部22がそれぞれ接
続形成されており、パッド21と配線部22とにより導
体回路の一部が構成されている。そして、半導体パッケ
ージをプリント配線板に実装する際には、各パッド21
上にクリーム半田を塗布したあと、図6に示すように半
導体パッケージ(この場合、SOP)23のリード24
がパッド21上に位置決めされてリフローソルダリング
により半田付けされる。
2. Description of the Related Art As electronic equipment becomes smaller and more sophisticated, SO
P (Small Outline Package), QFP
Surface mounting of semiconductor packages such as (quad flat packages) on printed wiring boards is progressing. In this printed wiring board, for example, as shown in FIG. 5, a plurality of component mounting pads (hereinafter, simply referred to as pads) 21 are formed in parallel on the surface of an insulating substrate 20 at equal intervals. Wiring portions 22 are connected to the pads 21, respectively, and the pads 21 and the wiring portions 22 form a part of a conductor circuit. When the semiconductor package is mounted on the printed wiring board, each pad 21
After applying the cream solder, the leads 24 of the semiconductor package (in this case, SOP) 23 are applied as shown in FIG.
Are positioned on the pad 21 and soldered by reflow soldering.

【0003】[0003]

【発明が解決しようとする課題】近年、プリント配線板
の高密度実装化に伴い半導体パッケージのリードの狭ピ
ッチ化も進んで、隣接するパッド21間の間隔が狭くな
り、パッド21の面積が小さくなる傾向にある。そし
て、パッド21の面積が小さいと、パッド21と基板2
0との接着強度が小さくなるとともに、塗布する半田量
も少なくなりリード24とパッド21との接続が弱まる
という問題がある。このため、半導体パッケージ23を
実装した後に、外部からの衝撃や振動によってリード2
4とパッド21との接続部分が剥がれたり、パッド21
が基板20から剥がれたりして半導体パッケージ23が
離脱する虞がある。
In recent years, as the density of printed wiring boards has been increased, the pitch of leads of a semiconductor package has become narrower, the distance between adjacent pads 21 has become narrower, and the area of the pads 21 has become smaller. Tends to become. When the area of the pad 21 is small, the pad 21 and the substrate 2
There is a problem that the bonding strength between the lead 24 and the pad 21 is weakened as the adhesive strength with 0 is reduced and the amount of applied solder is reduced. Therefore, after the semiconductor package 23 is mounted, the leads 2 are exposed to external shock or vibration.
4 and the connection between the pad 21 and the
May be peeled off from the substrate 20 and the semiconductor package 23 may be detached.

【0004】リード24とパッド21との接続を強固に
するために、クリーム半田の量を増加するということが
考えられるが、半田量を増加すると、リフロー時に半田
がパッド21から流れ出して隣接するパッド21間で半
田ブリッジが発生するという問題がある。
It is conceivable to increase the amount of cream solder in order to strengthen the connection between the lead 24 and the pad 21, but if the amount of solder is increased, the solder will flow out of the pad 21 during reflow and the adjacent pad There is a problem that a solder bridge occurs between the two.

【0005】又、プリント配線板に電子部品を実装する
際に、電子部品がその中心を軸として回動するようにず
れる場合がある。この場合、電子部品の最外側リードの
ズレ量は他のリードのズレ量よりも大きくなり、最外側
リードと最外側パッドとの接続信頼性が低下するという
問題がある。
Further, when the electronic component is mounted on the printed wiring board, the electronic component may be displaced so as to rotate about its center. In this case, the deviation amount of the outermost lead of the electronic component becomes larger than the deviation amounts of the other leads, and there is a problem that the connection reliability between the outermost lead and the outermost pad is lowered.

【0006】本発明は前記の問題点に鑑みてなされたも
のであり、その目的は、外部からの衝撃や振動による半
導体パッケージの配線板からの離脱を防止するととも
に、半田量の増加による半田ブリッジの発生を防止する
ことができ、更には、電子部品実装の信頼性を向上させ
ることができるプリント配線板を提供することにある。
The present invention has been made in view of the above problems, and an object thereof is to prevent the semiconductor package from being detached from the wiring board due to external impact or vibration and to increase the solder amount by increasing the solder bridge. It is an object of the present invention to provide a printed wiring board capable of preventing the occurrence of the above-mentioned problem and further improving the reliability of mounting electronic components.

【0007】[0007]

【課題を解決するための手段】上記の課題を解決するた
め本発明では、電子部品を実装するための複数の電子部
品搭載用パッドによりパッド列が構成され、前記複数の
電子部品搭載用パッドのうち、パッド列の最端部に位置
する電子部品搭載用パッドの配列方向寸法及び配列方向
と直交する方向の寸法を、パッド列内の他の電子部品搭
載用パッドの前記各方向の寸法よりそれぞれ大きくし
た。
In order to solve the above problems, in the present invention, a pad row is constituted by a plurality of electronic component mounting pads for mounting electronic components, and the pad row of the plurality of electronic component mounting pads is formed. Among them, the arrangement direction dimension of the electronic component mounting pads located at the end of the pad row and the dimension in the direction orthogonal to the arrangement direction are respectively larger than the dimensions of the other electronic component mounting pads in the pad row in the respective directions. I made it bigger.

【0008】[0008]

【作用】本発明では、パッド列の最端部に位置する電子
部品搭載用パッドの配列方向寸法及び配列方向と直交す
る方向の寸法を、パッド列内の他の電子部品搭載用パッ
ドの各方向の寸法よりそれぞれ大きくしたことにより、
その最端部のパッドの面積が大きくなり、パッドと基材
との接着強度が向上する。又、電子部品を実装する際に
パッドに塗布するクリーム半田の量を多くでき、リード
とパッドとの接続が強固となる。この結果、プリント配
線板から電子部品が離脱するのが確実に防止される。
In the present invention, the dimension of the electronic component mounting pad located at the end of the pad row and the dimension in the direction orthogonal to the array direction are set to the respective directions of other electronic component mounting pads in the pad row. By making each larger than
The area of the pad at the end is increased, and the adhesive strength between the pad and the base material is improved. In addition, the amount of cream solder applied to the pad when mounting the electronic component can be increased, and the connection between the lead and the pad can be strengthened. As a result, it is possible to reliably prevent the electronic component from coming off from the printed wiring board.

【0009】又、最端部に位置する電子部品搭載用パッ
ドに塗布される半田量が多くても、その面積が大きいた
めはみ出すことがなく、リフロー時において隣接するパ
ッド間で半田ブリッジは発生しない。更に、電子部品を
実装する際に電子部品が回動するようにずれた場合にリ
ードのズレ量が大きくなるが、そのリードに対応する最
端部のパッドの面積が大きいため、パッドとリードとが
確実に接続される。
Further, even if a large amount of solder is applied to the electronic component mounting pad located at the outermost end, it does not protrude due to its large area, and a solder bridge does not occur between adjacent pads during reflow. . Further, when the electronic component is mounted such that the electronic component is rotated and displaced, the lead shift amount increases. However, since the area of the pad at the end corresponding to the lead is large, the pad and the lead Is securely connected.

【0010】[0010]

【実施例】以下、本発明を具体化した一実施例を図1、
図2に従って説明する。図1、図2(a)に示すよう
に、プリント配線板1を構成する絶縁基板2上には、パ
ッド3が複数個形成されている。このパッド3は4個を
一列として2列に亘って平行となるように配置されてい
る。各列の内側に位置する2個のパッド3aの配列方向
寸法(幅)及び配列方向と直交する方向の寸法(長さ)
よりも外側すなわち最端部に位置する2個のパッド3b
の各寸法が大きくなるように形成されている。すなわ
ち、パッド3aはプリント配線板1に実装される電子部
品としてのSOP4のリード5を接続する際に必要な一
定の幅(約0.7mm)及び長さ(約1.5mm)を有
している。パッド3bは前記パッド3aの幅及び長さよ
りも大きな幅(約1.0mm)及び長さ(約2.0m
m)を有している。なお、前記パッド3a、3bには配
線部6がそれぞれ接続形成されており、導体回路の一部
を構成している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG.
It will be described with reference to FIG. As shown in FIGS. 1 and 2A, a plurality of pads 3 are formed on an insulating substrate 2 that constitutes the printed wiring board 1. The pads 3 are arranged in parallel in two rows with four pads in one row. Arrangement dimension (width) of the two pads 3a located inside each row and dimension (length) in the direction orthogonal to the arrangement direction
Two pads 3b located on the outer side, that is, at the outermost end
Are formed so that the respective dimensions become larger. That is, the pad 3a has a certain width (about 0.7 mm) and a length (about 1.5 mm) necessary for connecting the lead 5 of the SOP 4 as an electronic component mounted on the printed wiring board 1. There is. The pad 3b has a width (about 1.0 mm) and a length (about 2.0 m) larger than the width and length of the pad 3a.
m). Wiring portions 6 are connected to the pads 3a and 3b, respectively, and form a part of a conductor circuit.

【0011】そして、プリント配線板1にSOP4を実
装する際には、図2(a)、図2(b)に示すように、
パッド3a、3b上にクリーム半田7を塗布し、その上
にSOP4のリード5を位置決めして載置する。このと
き、パッド3aよりもパッド3bが幅及び長さが大きい
ためその面積も大きくなっている。従って、パッド3b
に塗布される半田7の量も多くなる。続いて、リフロー
ソルダリングにより半田7を溶融させて、リード5とパ
ッド3a、3bとを接続させる。このとき、パッド3b
に塗布される半田7の量が多いため、リード5とパッド
3bとが強固に固着される。又、パッド3bの面積が大
きいためパッド3bと絶縁基板2との接着力も高まる。
この結果、外部からの衝撃や振動によってSOP4がプ
リント配線板1から離脱するのを防止することができ
る。
When the SOP 4 is mounted on the printed wiring board 1, as shown in FIGS. 2 (a) and 2 (b),
The cream solder 7 is applied on the pads 3a and 3b, and the leads 5 of the SOP 4 are positioned and placed thereon. At this time, since the width and length of the pad 3b are larger than that of the pad 3a, the area thereof is also larger. Therefore, the pad 3b
The amount of the solder 7 applied to is also large. Subsequently, the solder 7 is melted by reflow soldering to connect the lead 5 and the pads 3a and 3b. At this time, the pad 3b
Since a large amount of solder 7 is applied to the lead 5, the lead 5 and the pad 3b are firmly fixed to each other. Further, since the area of the pad 3b is large, the adhesive force between the pad 3b and the insulating substrate 2 is also increased.
As a result, it is possible to prevent the SOP 4 from separating from the printed wiring board 1 due to external impact or vibration.

【0012】パッド3bに塗布される半田7の量が多く
ても、パッド3bの面積が大きいためはみ出すことがな
く、リフロー時において溶融した半田7により隣接する
パッド3aとの間で半田ブリッジが発生するのを防止す
ることができる。
Even if the amount of the solder 7 applied to the pad 3b is large, the area of the pad 3b is large so that it does not protrude, and a solder bridge is generated between the adjacent pad 3a by the melted solder 7 during reflow. Can be prevented.

【0013】又、SOP4を実装する際にSOP4自体
がその中心を軸として回動するようにずれてもパッド3
bの面積が大きいため、その両パッド3bと最外側の両
リード5とが確実に接続される。従って、電子部品実装
の信頼性を向上させることができる。
Further, when the SOP 4 is mounted, even if the SOP 4 itself shifts so as to rotate about its center, the pad 3
Since the area of b is large, both pads 3b and the outermost leads 5 are reliably connected. Therefore, the reliability of electronic component mounting can be improved.

【0014】更に、パッド3bの面積が大きいため、幅
の狭いパッド3aと比較してリード5を位置決めする際
のパッドとのズレチェック及び実装後のリード5のズレ
チェックを容易に行うことができる。
Further, since the area of the pad 3b is large, it is possible to easily perform the displacement check with the pad when positioning the lead 5 and the displacement check of the lead 5 after mounting as compared with the narrow pad 3a. .

【0015】尚、本発明は上記実施例のみに限定される
ことはなく、本発明の趣旨を逸脱しない範囲で構成の一
部を変更してもよい。 (1)上記実施例では、SOP4の実装用パッド3a、
3bに具体化したが、図3に示すように、QFP8のよ
うな4方向リード5に対応して4列に亘ってパッド3
a、3bを形成してもよい。この場合、面積の大きなパ
ッド3bは8箇所形成されることになる。 (2)図4に示すように、リードが千鳥状の半導体パッ
ケージ9に対応してパッド3a、3bも千鳥状に配置さ
れたプリント配線板1において、そのパッド列の最端部
に位置するパッド3bの寸法を大きくしてもよい。
The present invention is not limited to the above-mentioned embodiments, and a part of the constitution may be modified within the scope of the present invention. (1) In the above embodiment, the mounting pad 3a for the SOP4,
3b, as shown in FIG. 3, as shown in FIG. 3, the pads 3 are arranged in four rows corresponding to the four-way leads 5 such as the QFP8.
You may form a, 3b. In this case, eight pads 3b having a large area are formed. (2) As shown in FIG. 4, in the printed wiring board 1 in which the pads 3a and 3b are also arranged in a zigzag pattern corresponding to the semiconductor package 9 having zigzag leads, the pad located at the end of the pad row. The size of 3b may be increased.

【0016】[0016]

【発明の効果】以上詳述したように、本発明によれば、
パッド列の最端部に位置するパッドの配列方向寸法及び
配列方向と直交する方向の寸法を、パッド列内の他の電
子部品搭載用パッドの寸法より大きくしたことにより、
リードとパッドとが強固に固着され、外部からの衝撃や
振動によって半導体パッケージが配線板から離脱するの
を防止するとともに、最端部に位置するパッドに塗布す
る半田量が増加してもパッドの面積が大きいため半田の
はみ出しがなく、半田ブリッジの発生を防止することが
でき、更には、電子部品実装の信頼性を向上させること
ができるという優れた効果を奏する。
As described in detail above, according to the present invention,
By arranging the dimension of the pad located at the extreme end of the pad row and the dimension in the direction orthogonal to the array direction to be larger than the dimensions of other electronic component mounting pads in the pad row,
The leads and pads are firmly fixed to prevent the semiconductor package from coming off from the wiring board due to external impact or vibration, and even if the amount of solder applied to the pad located at the outermost end increases, Since the area is large, the solder does not squeeze out, the occurrence of solder bridges can be prevented, and further, the reliability of electronic component mounting can be improved, which is an excellent effect.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例のプリント配線板を示す模式部
分平面図である。
FIG. 1 is a schematic partial plan view showing a printed wiring board according to an embodiment of the present invention.

【図2】同じく、SOPが実装されたプリント配線板を
示し、(a)は模式部分平面図であり、(b)は模式部
分断面図である。
2A and 2B also show a printed wiring board on which an SOP is mounted, FIG. 2A is a schematic partial plan view, and FIG. 2B is a schematic partial sectional view.

【図3】他の実施例のQFPが実装されたプリント配線
板を示す模式部分平面図である。
FIG. 3 is a schematic partial plan view showing a printed wiring board on which a QFP of another embodiment is mounted.

【図4】別の他の実施例の千鳥状の半導体パッケージが
実装されたプリント配線板を示す模式部分平面図であ
る。
FIG. 4 is a schematic partial plan view showing a printed wiring board on which a staggered semiconductor package of another embodiment is mounted.

【図5】従来例のプリント配線板を示す模式部分平面図
である。
FIG. 5 is a schematic partial plan view showing a conventional printed wiring board.

【図6】同じく、SOPが実装されたプリント配線板を
示す模式部分平面図である。
FIG. 6 is also a schematic partial plan view showing a printed wiring board on which an SOP is mounted.

【符号の説明】[Explanation of symbols]

1…プリント配線板、3a,3b…パッド、4…電子部
品としてのSOP。
1 ... Printed wiring board, 3a, 3b ... Pad, 4 ... SOP as an electronic component.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電子部品を実装するための複数の電子部
品搭載用パッドによりパッド列が構成され、前記複数の
電子部品搭載用パッドのうち、パッド列の最端部に位置
する電子部品搭載用パッドの配列方向寸法及び配列方向
と直交する方向の寸法を、パッド列内の他の電子部品搭
載用パッドの前記各方向の寸法よりそれぞれ大きくした
ことを特徴とするプリント配線板。
1. A pad row is composed of a plurality of electronic component mounting pads for mounting electronic components, and among the plurality of electronic component mounting pads, the electronic component mounting pad located at the end of the pad row. A printed wiring board, wherein the dimension of the pads in the array direction and the dimension in the direction orthogonal to the array direction are made larger than the dimensions of other electronic component mounting pads in the pad row in the respective directions.
JP32101492A 1992-11-30 1992-11-30 Printed wiring board Pending JPH06169153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32101492A JPH06169153A (en) 1992-11-30 1992-11-30 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32101492A JPH06169153A (en) 1992-11-30 1992-11-30 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH06169153A true JPH06169153A (en) 1994-06-14

Family

ID=18127831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32101492A Pending JPH06169153A (en) 1992-11-30 1992-11-30 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH06169153A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441477B2 (en) 2000-07-24 2002-08-27 Mitsubishi Denki Kabushiki Kaisha Substrate mounting an integrated circuit package with a deformed lead
JP2012185112A (en) * 2011-03-08 2012-09-27 Seiko Epson Corp Electronic device and method for manufacturing electronic device
JP2015159253A (en) * 2014-02-25 2015-09-03 ファナック株式会社 printed circuit board
JP2017069333A (en) * 2015-09-29 2017-04-06 ファナック株式会社 Printed circuit board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441477B2 (en) 2000-07-24 2002-08-27 Mitsubishi Denki Kabushiki Kaisha Substrate mounting an integrated circuit package with a deformed lead
JP2012185112A (en) * 2011-03-08 2012-09-27 Seiko Epson Corp Electronic device and method for manufacturing electronic device
JP2015159253A (en) * 2014-02-25 2015-09-03 ファナック株式会社 printed circuit board
US9872388B2 (en) 2014-02-25 2018-01-16 Fanuc Corporation Printed wiring board
DE102015102505B4 (en) * 2014-02-25 2020-01-30 Fanuc Corporation circuit board
JP2017069333A (en) * 2015-09-29 2017-04-06 ファナック株式会社 Printed circuit board

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