JP2005064274A - Printed circuit board and manufacturing method thereof - Google Patents

Printed circuit board and manufacturing method thereof Download PDF

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Publication number
JP2005064274A
JP2005064274A JP2003293148A JP2003293148A JP2005064274A JP 2005064274 A JP2005064274 A JP 2005064274A JP 2003293148 A JP2003293148 A JP 2003293148A JP 2003293148 A JP2003293148 A JP 2003293148A JP 2005064274 A JP2005064274 A JP 2005064274A
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circuit board
printed circuit
connection
wiring board
semiconductor package
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Japanese (ja)
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Shinya Hattori
新哉 服部
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To prevent breaking of a joining part between a printed wiring board and corners of a semiconductor element even at application of a stress. <P>SOLUTION: In a printed circuit board 1 wherein the nearly rectangular semiconductor element 2 is surface-mounted on the printed wiring board 3 on which wiring patterns are formed, connection pads 5 to be soldered to pads 7 formed on the printed wiring board 3 are arranged on a connection face 2a of the semiconductor element 2 to the printed wiring board 3 except each corner 6 of the connection face 2a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体パッケージ等が表面実装されたプリント回路板に関し、特に、ＢＧＡ（ball grid array）等のパッケージの下面全体を電極として用いる半導体パッケージが実装されるプリント回路板に関する。   The present invention relates to a printed circuit board on which a semiconductor package or the like is surface-mounted, and more particularly to a printed circuit board on which a semiconductor package using an entire lower surface of a package such as a BGA (ball grid array) as an electrode is mounted.

従来より、電子機器の小型化、高密度化に伴い、プリント回路板に表面実装される半導体パッケージは、ＱＦＰ（quad flat package）やＳＯＰ（small outline package）等の周辺にリード端子が設けられたペリフェラル型（peripheral）から、ＢＧＡ（ball grid array）やＬＧＡ（land grid array）等のパッケージの下面全体を電極として用いるエリアアレイ型（area array type）に移行しつつある。また、最近では携帯情報端末機器を中心に、チップと同じか又は同等の大きさを持つインターポーザー上にチップを搭載しパッケージした、ＢＧＡよりさらに狭ピッチに形成したＣＳＰ（chip size package）が用いられるようになっている。   Conventionally, as electronic devices have become smaller and higher in density, semiconductor packages that are surface-mounted on printed circuit boards have been provided with lead terminals around the QFP (quad flat package), SOP (small outline package), etc. A peripheral type (peripheral) is shifting to an area array type (BGA (ball grid array), LGA (land grid array), etc.) that uses the entire lower surface of a package as an electrode. Recently, a CSP (chip size package) formed with a narrower pitch than the BGA, which is mounted and packaged on an interposer having the same size or the same size as the chip, mainly in portable information terminal devices, is used. It is supposed to be.

これらＬＧＡやＣＳＰ等に代表されるエリアアレイ型の半導体パッケージは、下面全体に電極が配列されると共に、この電極上にはんだボールあるいははんだバンプが形成されている。そして、この半導体パッケージは、プリント配線基板上に形成されクリームはんだが塗布されたパッド上に搭載され、リフロー工程を経て基板表面に実装される。   In these area array type semiconductor packages represented by LGA, CSP, etc., electrodes are arranged on the entire lower surface, and solder balls or solder bumps are formed on the electrodes. The semiconductor package is mounted on a pad formed on a printed wiring board and coated with cream solder, and is mounted on the surface of the board through a reflow process.

一般に、このようなＢＧＡ接続構造の半導体パッケージ５０は、図７に示すように、略矩形状に形成され、下面５０ａには複数の電極５１がパッケージの形状に応じて格子状に配列されている。この電極５１は、半導体パッケージ５０の下面５０ａの形状に応じて配列されることにより、下面５０ａの各コーナ部５２，５２，５２，５２に、格子状に配列された電極５１のコーナ部の電極５１ａ，５１ａ，５１ａ，５１ａが位置されている。   In general, as shown in FIG. 7, the semiconductor package 50 having such a BGA connection structure is formed in a substantially rectangular shape, and a plurality of electrodes 51 are arranged in a lattice shape on the lower surface 50a according to the shape of the package. . The electrodes 51 are arranged in accordance with the shape of the lower surface 50a of the semiconductor package 50, so that the corner portions 52, 52, 52, 52 of the lower surface 50a have corner electrodes of the electrodes 51 arranged in a lattice pattern. 51a, 51a, 51a, 51a are located.

そして、各電極５１には、プリント配線基板５３へ実装するためのはんだボールあるいははんだバンプが形成される。その後、半導体パッケージ５０は、図８に示すように、プリント配線基板５３のパッド５４上に搭載される。このパッド５４には予めクリームはんだが塗布されており、半導体パッケージ５０が搭載された後、リフロー工程を経ることにより半導体パッケージ５０の電極５１がプリント配線基板５３のパッド５４と接続される。これにより、半導体パッケージ５０が表面実装されたプリント回路板５５が形成される。   Each electrode 51 is formed with solder balls or solder bumps for mounting on the printed wiring board 53. Thereafter, the semiconductor package 50 is mounted on the pads 54 of the printed wiring board 53 as shown in FIG. Cream solder is applied to the pads 54 in advance, and after the semiconductor package 50 is mounted, the electrodes 51 of the semiconductor package 50 are connected to the pads 54 of the printed wiring board 53 through a reflow process. Thereby, the printed circuit board 55 on which the semiconductor package 50 is surface-mounted is formed.

ところで、このようなプリント回路板５５は、各種電子機器に組み込まれる作業工程や、各種電子機器に組み込まれた後の実使用時等において、曲げや引っ張り等の様々な外力による応力を受けることがある。その際、プリント回路板５５は、半導体パッケージ５０の下面５０ａに形成された複数の電極５１の内、各コーナ部５２，５２，５２，５２に位置する電極５１ａの接続部分に最もストレスが加わる。   By the way, such a printed circuit board 55 is subjected to stresses caused by various external forces such as bending and pulling in a working process incorporated in various electronic devices or in actual use after being incorporated in various electronic devices. is there. At that time, the printed circuit board 55 is most stressed at the connection portions of the electrodes 51 a located at the corners 52, 52, 52, 52 among the plurality of electrodes 51 formed on the lower surface 50 a of the semiconductor package 50.

すなわち、半導体パッケージ５０の下面５０ａに形成された複数の電極５１は、当該半導体パッケージ５０の形状に応じて格子状に配列され、下面５０ａの各コーナ部５２，５２，５２，５２に、格子のコーナ部の電極５１ａ，５１ａ，５１ａ，５１ａが位置されている。また、半導体パッケージ５０が実装されるプリント配線基板５３のパッド５４も、格子状に配列された電極５１に応じて略矩形状に形成されている。したがって、プリント回路板５５が応力を受けると、図９に示すように、半導体パッケージ５０とプリント配線基板５３との接続部の端部となる、下面５０ａの各コーナ部５２，５２，５２，５２に位置する電極５１ａ，５１ａ，５１ａ，５１ａとパッド５４との接合部分にこの応力が集中してしまう。このため、従来のプリント回路板５５においては、半導体パッケージ５０の電極５１ａ，５１ａ，５１ａ，５１ａとパッド５４との接合部分が破断してしまう問題があった。   That is, the plurality of electrodes 51 formed on the lower surface 50a of the semiconductor package 50 are arranged in a lattice shape according to the shape of the semiconductor package 50, and each corner portion 52, 52, 52, 52 of the lower surface 50a has a lattice shape. Corner electrodes 51a, 51a, 51a, 51a are located. Further, the pads 54 of the printed wiring board 53 on which the semiconductor package 50 is mounted are also formed in a substantially rectangular shape according to the electrodes 51 arranged in a lattice shape. Therefore, when the printed circuit board 55 is subjected to stress, as shown in FIG. 9, each corner portion 52, 52, 52, 52 of the lower surface 50 a that becomes the end portion of the connection portion between the semiconductor package 50 and the printed wiring board 53. This stress is concentrated at the joint portion between the electrode 51a, 51a, 51a, 51a and the pad 54 located at the same position. For this reason, in the conventional printed circuit board 55, there existed a problem that the junction part of the electrodes 51a, 51a, 51a, 51a and the pad 54 of the semiconductor package 50 will fracture | rupture.

特開２００３−１００９４９号公報JP2003-1000094A

そこで、本願は、応力が加わった場合でも半導体素子のコーナ部とプリント配線基板との接合部分の破断を防止することができるプリント回路板及びプリント回路板の製造方法を提供することを目的とする。   Therefore, the present application aims to provide a printed circuit board and a printed circuit board manufacturing method capable of preventing breakage of a joint portion between a corner portion of a semiconductor element and a printed wiring board even when stress is applied. .

上述した課題を解決するために、本発明に係るプリント回路板は、配線パターンが形成されたプリント配線基板上に略矩形状の半導体素子が表面実装されたプリント回路板において、上記半導体素子は、上記プリント配線基板との接続面に、該接続面の各コーナ部を除いて上記プリント配線基板上に形成されたパッドにはんだ付けされる接続パッドが配列されているものである。   In order to solve the above-described problem, a printed circuit board according to the present invention is a printed circuit board in which a substantially rectangular semiconductor element is surface-mounted on a printed wiring board on which a wiring pattern is formed. Connection pads that are soldered to pads formed on the printed wiring board are arranged on the connection surface with the printed wiring board except for each corner portion of the connection surface.

また、本発明に係るプリント回路板の製造方法は、略矩形状に形成された半導体素子のプリント配線基板との接続面に、該接続面の各コーナ部を除いて上記プリント配線基板との接続を図る接続パッドを配列する工程と、上記半導体素子の接続パッドと接続されるパッドが形成された上記プリント配線基板上に上記半導体素子を実装する工程とを有するものである。   Further, the printed circuit board manufacturing method according to the present invention provides a connection surface of the semiconductor element formed in a substantially rectangular shape with the printed wiring board except for each corner portion of the connection surface. And a step of arranging the semiconductor element on the printed wiring board on which the pad connected to the connection pad of the semiconductor element is formed.

このようなプリント回路板及びプリント回路板の製造方法によれば、プリント回路板が曲げや引っ張り等の様々な外力による応力を受けた場合においても、半導体パッケージに配列された複数の接続パッドの一部に応力が集中することはない。   According to such a printed circuit board and a printed circuit board manufacturing method, even when the printed circuit board is subjected to stress due to various external forces such as bending and pulling, one of the plurality of connection pads arranged in the semiconductor package. Stress does not concentrate on the part.

すなわち、プリント回路板の半導体パッケージは、プリント配線基板との接続部となる接続パッドがその配列形状においてコーナ部が設けられていない。したがって、接続パッドは、略矩形状に形成された半導体パッケージの各コーナ部には設けられていない。このため、半導体パッケージは、プリント回路板が曲げられる等により何れかの方向から応力を受けた際にも各接続パッドに均等に応力を受けることができる。したがって、プリント回路板は、どの方向から応力を受けた場合でも、一部の接続パッドに当該応力が集中することを防ぎ、各接続パッドに加わる応力を分散することにより緩和させることができる。これにより、プリント回路板は、組み込まれた電子機器等の製品寿命を延ばすことができる。   That is, in the semiconductor package of the printed circuit board, the corner portion is not provided in the arrangement shape of the connection pads that become the connection portion with the printed wiring board. Therefore, the connection pad is not provided in each corner portion of the semiconductor package formed in a substantially rectangular shape. For this reason, the semiconductor package can receive stress evenly on each connection pad even when the printed circuit board is stressed from any direction due to bending or the like. Therefore, even if the printed circuit board receives stress from any direction, the stress can be prevented from concentrating on some of the connection pads, and the stress applied to each connection pad can be relaxed. Thereby, the printed circuit board can prolong the product life of the incorporated electronic device or the like.

以下、本発明が適用されたプリント回路板及びこのプリント回路板の製造方法について図面を参照しながら詳細に説明する。このプリント回路板１は、図１に示すように、半導体素子が収納された半導体パッケージ２と、この半導体パッケージ２が表面実装されたプリント配線基板３とを有する。   Hereinafter, a printed circuit board to which the present invention is applied and a method of manufacturing the printed circuit board will be described in detail with reference to the drawings. As shown in FIG. 1, the printed circuit board 1 includes a semiconductor package 2 in which semiconductor elements are accommodated, and a printed wiring board 3 on which the semiconductor package 2 is surface-mounted.

半導体パッケージ２は、半導体のベアチップをセラミック材や有機絶縁基板のパッケージに収容するとともに、略矩形状に形成されたパッケージの下面２ａを電極として用いるエリアアレイ型の半導体素子である。また、半導体パッケージ２は、図２に示すように、下面全体にボール型のはんだバンプ４が設けられた接続パッド５が複数形成されたＢＧＡあるいはＣＳＰタイプの接続構造を備え、各接続パッド５には図示を省略する微細配線あるいは微小バイアが連続されている。   The semiconductor package 2 is an area array type semiconductor element in which a semiconductor bare chip is accommodated in a ceramic material or an organic insulating substrate package, and the lower surface 2a of the package formed in a substantially rectangular shape is used as an electrode. Further, as shown in FIG. 2, the semiconductor package 2 has a BGA or CSP type connection structure in which a plurality of connection pads 5 having ball-type solder bumps 4 provided on the entire lower surface are formed. Are continuous with fine wirings or micro vias (not shown).

この半導体パッケージ２の下面２ａに複数形成されている接続パッド５は、略円形状に配設され、その配列形状においてはコーナ部が設けられていない。これにより、接続パッド５は、略矩形状に形成された下面２ａの各コーナ部６，６，６，６には設けられていない。   A plurality of connection pads 5 formed on the lower surface 2a of the semiconductor package 2 are arranged in a substantially circular shape, and no corner portion is provided in the arrangement shape. Thereby, the connection pad 5 is not provided in each corner part 6,6,6,6 of the lower surface 2a formed in the substantially rectangular shape.

このような半導体パッケージ２が実装されるプリント配線基板３は、例えばガラスエポキシ樹脂を用いた銅張積層板であり、公知のフォトリソグラフィを用いたプリントエッチ法等によって、一面又は両面に回路パターンが形成されている。   A printed wiring board 3 on which such a semiconductor package 2 is mounted is, for example, a copper-clad laminate using glass epoxy resin, and a circuit pattern is formed on one or both sides by a print etching method using known photolithography. Is formed.

また、プリント配線基板３は、半導体パッケージ２の実装面側の回路パターンに、半導体パッケージ２が接続されるパッド７が形成されている。このパッド７には、プリント配線基板３上にパッド７のパターンに応じた開口部が形成されたメタルマスクが密着された後はんだペーストが印刷されることにより、適量のはんだが塗布され、次いで、半導体パッケージ２が搭載される。その後、プリント配線基板３のリフロー工程を経ることにより、接続パッド５上に設けられたはんだバンプ４がパッド７に塗布されたはんだペーストと接合され、半導体パッケージ２がプリント配線基板３に実装される。   In the printed wiring board 3, pads 7 to which the semiconductor package 2 is connected are formed on the circuit pattern on the mounting surface side of the semiconductor package 2. An appropriate amount of solder is applied to the pad 7 by printing a solder paste after the metal mask having an opening corresponding to the pattern of the pad 7 formed on the printed wiring board 3 is adhered to the pad 7. A semiconductor package 2 is mounted. Thereafter, through a reflow process of the printed wiring board 3, the solder bumps 4 provided on the connection pads 5 are joined to the solder paste applied to the pads 7, and the semiconductor package 2 is mounted on the printed wiring board 3. .

このようなプリント回路板１によれば、各種電子機器に組み込まれる作業工程や、各種電子機器に組み込まれた後の実使用時等において、曲げや引っ張り等の様々な外力による応力を受けた場合においても、半導体パッケージ２の下面２ａに形成された複数の接続パッド５の一部に応力が集中することはない。   According to such a printed circuit board 1, when subjected to stress due to various external forces such as bending and pulling in a working process incorporated in various electronic devices or in actual use after being incorporated in various electronic devices. However, stress does not concentrate on a part of the plurality of connection pads 5 formed on the lower surface 2 a of the semiconductor package 2.

すなわち、プリント回路板１の半導体パッケージ２は、下面２ａに形成されプリント配線基板３との接続部となる接続パッド５が略円形状に配設され、その配列形状においてコーナ部が設けられていない。したがって、接続パッド５は、略矩形状に形成された半導体パッケージ２の下面２ａの各コーナ部６，６，６，６には設けられていない。このため、半導体パッケージ２は、プリント回路板１が曲げられる等により何れかの方向から応力を受けた際にも各接続パッド５に均等に応力を受けることができる。したがって、プリント回路板１は、どの方向から応力を受けた場合でも、一部の接続パッド５に当該応力が集中することを防ぎ、各接続パッド５に加わる応力を分散することにより緩和させることができる。これにより、プリント回路板１は、組み込まれた電子機器等の製品寿命を延ばすことができる。   That is, in the semiconductor package 2 of the printed circuit board 1, the connection pads 5 that are formed on the lower surface 2a and serve as connection portions with the printed wiring board 3 are arranged in a substantially circular shape, and no corner portion is provided in the arrangement shape. . Therefore, the connection pad 5 is not provided in each corner part 6, 6, 6, 6 of the lower surface 2a of the semiconductor package 2 formed in a substantially rectangular shape. For this reason, the semiconductor package 2 can be equally stressed by the connection pads 5 even when the printed circuit board 1 is subjected to stress from any direction due to bending or the like. Therefore, the printed circuit board 1 can prevent the stress from being concentrated on some of the connection pads 5 regardless of the direction from which the stress is applied, and can relax the stress by dispersing the stress applied to the connection pads 5. it can. Thereby, the printed circuit board 1 can prolong the product life of the electronic device etc. which were incorporated.

このようなプリント回路板１は次のようにして製造される。先ず、半導体パッケージ２の製造方法について説明すると、図３（Ａ）に示すように、セラミック材や有機絶縁基板等のパッケージ基板１０に、接続パッド５を含む所定の配線パターンを形成する。このとき、接続パッド５は、図２に示すように、略円形状に配列され、その配列形状においてはコーナ部が設けられていない。   Such a printed circuit board 1 is manufactured as follows. First, a manufacturing method of the semiconductor package 2 will be described. As shown in FIG. 3A, a predetermined wiring pattern including the connection pads 5 is formed on a package substrate 10 such as a ceramic material or an organic insulating substrate. At this time, as shown in FIG. 2, the connection pads 5 are arranged in a substantially circular shape, and no corner portion is provided in the arrangement shape.

次いで、図３（Ｂ）に示すように、パッケージ基板１０上にＬＳＩやＵＬＳＩ等の半導体チップ１１を接着し、ワイヤーボンディング、ＴＡＢ等により配線パターンと接続する。その後、金属、セラミック、モールド樹脂等によってパッケージがされる。   Next, as shown in FIG. 3B, a semiconductor chip 11 such as LSI or ULSI is bonded onto the package substrate 10 and connected to the wiring pattern by wire bonding, TAB, or the like. Thereafter, the package is made of metal, ceramic, mold resin, or the like.

次いで、図３（Ｃ）に示すように、接続パッド５が形成された面に、パッドの配列形状に応じた開口部が形成されたマスクを貼着し、クリームはんだを印刷することにより、各接続パッド５上にはんだバンプ４を形成する。   Next, as shown in FIG. 3C, a mask having openings formed in accordance with the arrangement shape of the pads is adhered to the surface on which the connection pads 5 are formed, and cream solder is printed. Solder bumps 4 are formed on the connection pads 5.

このようにして形成される半導体パッケージ２が実装されるプリント配線基板３は、図４（Ａ）に示すように、ガラスエポキシ樹脂基板に銅箔を貼着した銅張積層板１２に、公知のフォトリソグラフィを用いたプリントエッチ法等によって、一面又は両面にパッド７を含む回路パターンが形成される。   As shown in FIG. 4A, a printed wiring board 3 on which the semiconductor package 2 formed in this way is mounted on a copper-clad laminate 12 in which a copper foil is bonded to a glass epoxy resin substrate. A circuit pattern including pads 7 is formed on one or both sides by a print etching method using photolithography or the like.

次いで、パッド７が形成された面に、パッド７のパターンに応じた開口部が形成されたメタルマスクが密着される。その後、図４（Ｂ）に示すように、はんだペーストが印刷されることにより、適量のはんだが塗布される。   Next, a metal mask having an opening corresponding to the pattern of the pad 7 is brought into close contact with the surface on which the pad 7 is formed. Thereafter, as shown in FIG. 4B, an appropriate amount of solder is applied by printing a solder paste.

次いで、図５（Ａ）に示すように、プリント配線基板３のパッド７上に半導体パッケージ２が搭載される。その後、プリント配線基板３は、リフロー炉を通されることにより、半導体パッケージ２の接続パッド５に設けられたはんだバンプ４とプリント配線基板３のパッド７に塗布されたはんだペーストとが溶融し接合される。これにより、図５（Ｂ）に示すように、半導体パッケージ２がプリント配線基板３上に実装されたプリント回路板１が製造される。   Next, as shown in FIG. 5A, the semiconductor package 2 is mounted on the pad 7 of the printed wiring board 3. Thereafter, the printed wiring board 3 is passed through a reflow furnace, whereby the solder bumps 4 provided on the connection pads 5 of the semiconductor package 2 and the solder paste applied to the pads 7 of the printed wiring board 3 are melted and joined. Is done. Thereby, as shown in FIG. 5B, the printed circuit board 1 in which the semiconductor package 2 is mounted on the printed wiring board 3 is manufactured.

このようにして製造されるプリント回路板１は、その後、各種電子機器に組み込まれていく。このとき、プリント回路板１は、電子機器の組み立て工程や実使用時において、曲げ等の外力により応力を受けた場合にも、半導体パッケージ２の下面２ａに形成された複数の接続パッド５の一部に応力が集中することはない。   The printed circuit board 1 manufactured in this way is then incorporated into various electronic devices. At this time, the printed circuit board 1 is one of the plurality of connection pads 5 formed on the lower surface 2a of the semiconductor package 2 even when subjected to stress due to an external force such as bending during an electronic device assembly process or actual use. Stress does not concentrate on the part.

すなわち、プリント回路板１の半導体パッケージ２は、下面２ａに形成されプリント配線基板３との接続部となる各接続パッド５が略円形状に配設され、その配列形状においてコーナ部が設けられていない。したがって、接続パッド５は、略矩形状に形成された半導体パッケージ２の下面２ａの各コーナ部６，６，６，６には設けられていない。このため、半導体パッケージ２は、プリント回路板１が曲げられる等により応力を受けた際にも接続パッド５に均等に応力を受けることができる。したがって、プリント回路板１は、どの方向から応力を受けた場合でも、一部の接続パッド５に応力が集中することを防ぎ、各接続パッド５に加わる応力を分散することにより緩和させることができる。これにより、プリント回路板１は、組み込まれた電子機器等の製品寿命を延ばすことができる。   That is, in the semiconductor package 2 of the printed circuit board 1, each connection pad 5 that is formed on the lower surface 2a and serves as a connection portion with the printed wiring board 3 is arranged in a substantially circular shape, and a corner portion is provided in the array shape. Absent. Therefore, the connection pad 5 is not provided in each corner part 6, 6, 6, 6 of the lower surface 2a of the semiconductor package 2 formed in a substantially rectangular shape. For this reason, the semiconductor package 2 can receive the stress evenly on the connection pads 5 even when the printed circuit board 1 is stressed by bending or the like. Accordingly, the printed circuit board 1 can prevent stress from being concentrated on some of the connection pads 5 and can relax the stress by dispersing the stress applied to the connection pads 5 regardless of the direction from which the stress is applied. . Thereby, the printed circuit board 1 can prolong the product life of the electronic device etc. which were incorporated.

以上、本発明が適用されたプリント回路板及びプリント回路板の製造方法について詳細に説明したが、本発明は、上述した構成に限られず、例えば、半導体パッケージ２の下面２ａに形成される接続パッド５は、略円形状以外にも、図６に示すように、略八角形状に形成してもよい。この場合、接続パッド５の配列形状においてコーナ部が生じてしまうが、当該コーナ部は鈍角となるため、当該コーナ部に加わる応力がコーナ部周辺の複数の接続パッド５に分散され、各接続パッド５にかかる応力を緩和させることができる。したがって、図６に示す、接続パッド５が略八角形状に配列された半導体パッケージ２を有するプリント回路板によっても、組み込まれた電子機器の製品寿命を延ばすことができる。なお、接続パッド５の配列形状は、八角形状に限らず、より多くのコーナ部を有する多角形状であればさらに応力を分散させることができる。特に、各コーナが備える角度が鈍角となる形状に配列することにより、各コーナ部にかかる応力を分散させることができる。   As described above, the printed circuit board to which the present invention is applied and the method for manufacturing the printed circuit board have been described in detail. However, the present invention is not limited to the above-described configuration. For example, the connection pad formed on the lower surface 2a of the semiconductor package 2 In addition to the substantially circular shape, 5 may be formed in a substantially octagonal shape as shown in FIG. In this case, corner portions are generated in the arrangement shape of the connection pads 5. However, since the corner portions have an obtuse angle, the stress applied to the corner portions is distributed to the plurality of connection pads 5 around the corner portions. 5 can be relieved. Therefore, the printed circuit board having the semiconductor package 2 in which the connection pads 5 are arranged in a substantially octagonal shape shown in FIG. 6 can also extend the product life of the incorporated electronic device. Note that the arrangement shape of the connection pads 5 is not limited to the octagonal shape, and the stress can be further dispersed if the polygonal shape has more corner portions. In particular, the stress applied to each corner portion can be dispersed by arranging the corners in an obtuse angle.

その他、半導体パッケージ２の接続パッド５の配列形状は、角のない形状であれば、特定の接続パッドに応力が集中することなく、半導体パッケージ２とプリント配線基板３との接続箇所が破断することを防止することができる。   In addition, if the arrangement shape of the connection pads 5 of the semiconductor package 2 is a shape having no corners, stress is not concentrated on a specific connection pad, and the connection portion between the semiconductor package 2 and the printed wiring board 3 is broken. Can be prevented.

また、図６に示すように、半導体パッケージ２の下面２ａの中央部に接続パッド５の配列スペースがある場合は、下面２ａのコーナ部６周辺に設けられていた接続パッド５の換わりに、中央部に接続パッド５を配列することができる。したがって、接続パッド５をコーナ部６を除く領域に配列した場合にも、パッケージサイズ大きくすることなく必要な数の接続パッド５を設けることができる。   In addition, as shown in FIG. 6, when there is a space for arranging the connection pads 5 in the central portion of the lower surface 2a of the semiconductor package 2, the central portion is replaced with the connection pads 5 provided around the corner portion 6 of the lower surface 2a. The connection pads 5 can be arranged in the part. Therefore, even when the connection pads 5 are arranged in a region excluding the corner portion 6, the necessary number of connection pads 5 can be provided without increasing the package size.

なお、プリント配線基板３に実装される半導体素子は、パッケージされたもの以外にも、ベアチップを用いてもよい。すなわち、下面に接続端子が略円形状に配列された当該ベアチップをプリント配線基板３のパッド７上に直接搭載する方式を用いても同様の作用、効果を有する。   Note that the semiconductor element mounted on the printed wiring board 3 may be a bare chip other than the packaged one. That is, even if a method of directly mounting the bare chip having connection terminals arranged in a substantially circular shape on the lower surface on the pad 7 of the printed wiring board 3 has the same operation and effect.

本発明が適用されたプリント回路板を示す断面図である。It is sectional drawing which shows the printed circuit board to which this invention was applied. 半導体パッケージの接続パッドの配列形状を示す底面図である。It is a bottom view which shows the arrangement | sequence shape of the connection pad of a semiconductor package. 半導体パッケージの製造工程を示す図である。It is a figure which shows the manufacturing process of a semiconductor package. プリント配線基板の製造工程を示す図である。It is a figure which shows the manufacturing process of a printed wiring board. 半導体パッケージをプリント配線基板に実装する工程を示す図である。It is a figure which shows the process of mounting a semiconductor package on a printed wiring board. 他の半導体パッケージの接続パッドの配列形状を示す図である。It is a figure which shows the arrangement | sequence shape of the connection pad of another semiconductor package. 従来のＢＧＡ接続構造の半導体パッケージを示す底面図である。It is a bottom view which shows the semiconductor package of the conventional BGA connection structure. 従来の半導体パッケージが実装されたプリント回路板を示す側面図である。It is a side view which shows the printed circuit board with which the conventional semiconductor package was mounted. 応力が加わった従来のプリント回路板を示す側面図である。It is a side view which shows the conventional printed circuit board to which the stress was added.

符号の説明Explanation of symbols

１ プリント回路板、２ 半導体パッケージ、３ プリント配線基板、４ はんだバンプ、５ 接続パッド、６ コーナ部、７ パッド、１０ パッケージ基板、１１ 半導体チップ、１２ 銅張積層板
DESCRIPTION OF SYMBOLS 1 Printed circuit board, 2 Semiconductor package, 3 Printed wiring board, 4 Solder bump, 5 Connection pad, 6 Corner part, 7 Pad, 10 Package board, 11 Semiconductor chip, 12 Copper clad laminated board

Claims (6)

配線パターンが形成されたプリント配線基板上に略矩形状の半導体素子が表面実装されたプリント回路板において、
上記半導体素子は、上記プリント配線基板との接続面に、該接続面の各コーナ部を除いて上記プリント配線基板上に形成されたパッドにはんだ付けされる接続パッドが配列されていることを特徴とするプリント回路板。 In a printed circuit board in which a substantially rectangular semiconductor element is surface-mounted on a printed wiring board on which a wiring pattern is formed,
In the semiconductor element, connection pads to be soldered to pads formed on the printed wiring board except for each corner portion of the connection surface are arranged on a connection surface with the printed wiring board. Printed circuit board. 上記半導体素子は、上記接続パッドが略円形状に配列されていることを特徴とする請求項１記載のプリント回路板。   2. The printed circuit board according to claim 1, wherein in the semiconductor element, the connection pads are arranged in a substantially circular shape. 上記半導体素子は、上記接続パッドが多角形状に配列されていることを特徴とする請求項１記載のプリント回路板。   The printed circuit board according to claim 1, wherein the semiconductor element has the connection pads arranged in a polygonal shape. 略矩形状に形成された半導体素子のプリント配線基板との接続面に、該接続面の各コーナ部を除いて上記プリント配線基板との接続を図る接続パッドを配列する工程と、
上記半導体素子の接続パッドと接続されるパッドが形成された上記プリント配線基板上に上記半導体素子を実装する工程とを有するプリント回路板の製造方法。 Arranging a connection pad for connection with the printed wiring board except for each corner portion of the connection surface on a connection surface with the printed wiring board of the semiconductor element formed in a substantially rectangular shape;
And a step of mounting the semiconductor element on the printed wiring board on which a pad connected to the connection pad of the semiconductor element is formed. 上記半導体素子は、上記接続パッドが略円形状に配列されていることを特徴とする請求項４記載のプリント回路板の製造方法。   5. The method of manufacturing a printed circuit board according to claim 4, wherein the connection pads of the semiconductor element are arranged in a substantially circular shape. 上記半導体素子は、上記接続パッドが多角形状に配列されていることを特徴とする請求項４記載のプリント回路板の製造方法。
5. The method of manufacturing a printed circuit board according to claim 4, wherein the connection pads of the semiconductor element are arranged in a polygonal shape.
JP2003293148A 2003-08-13 2003-08-13 Printed circuit board and manufacturing method thereof Withdrawn JP2005064274A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009200274A (en) * 2008-02-22 2009-09-03 Toshiba Corp Integrated semiconductor apparatus
CN102378484A (en) * 2010-08-13 2012-03-14 雅达电子有限公司 Method for improving solder joint reliability, printed circuit board, packaging device and packaging module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009200274A (en) * 2008-02-22 2009-09-03 Toshiba Corp Integrated semiconductor apparatus
JP4568337B2 (en) * 2008-02-22 2010-10-27 株式会社東芝 Integrated semiconductor device
CN102378484A (en) * 2010-08-13 2012-03-14 雅达电子有限公司 Method for improving solder joint reliability, printed circuit board, packaging device and packaging module

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