JP4568337B2 - Integrated semiconductor device - Google Patents

Description

  The present invention relates to an integrated semiconductor device configured by mounting a plurality of semiconductor elements.

  In recent years, high integration technology has progressed in integrated semiconductor devices, and high integration density is also required for the integration technology of semiconductor elements constituting the integrated semiconductor devices. In particular, recent high integration technologies for integrated semiconductor devices require integration technologies for electromechanical elements (MEMS) as well as high-performance semiconductor element (LSI) integration technologies.

  A micro electro mechanical system (MEMS) is an electromechanical element having a micro structure manufactured using a silicon micromachining process. MEMS is expected to be applied in a wide range of electronic parts such as pressure sensors, acceleration sensors, and RF filters. As a technology for integrating such MEMS together with LSI, there is a high-density three-dimensional mounting technology in which a plurality of LSIs and MEMS are stacked, but it is necessary to form vertical through holes in the LSI and MEMS. Therefore, there is a problem that the process cost is high, and there is a demand for a technology for high integration on the same plane.

As a method of highly integrating on the same plane, there are typically two systems, SOC (System on a Chip) and SIP ( System in a Package ). The SOC is a method of integrating a plurality of devices by forming them on one chip. Although it is possible to increase the degree of device integration in the SOC, there is a problem that there are limitations on the types of devices that can be integrated. For example, it is difficult to form a device made of another crystal system such as GaAs on a Si substrate due to process differences. In addition, the SOC has a problem that the design period for realizing a new device is long and the development cost becomes high.

  On the other hand, in SIP, after a plurality of LSI chips and MEMS chips are individually formed, each is mounted on an integrated substrate. In SIP, since each device can be formed individually, there is no restriction on the devices to be integrated. Further, when a new system is realized, there is an advantage that the development cost can be reduced because the existing chip can be used and the design period can be shortened. However, since the element integration density depends on an integrated substrate on which a plurality of LSI chips and MEMS chips are mounted, there is a problem that it is difficult to increase the device arrangement density.

  For example, in Patent Document 1, a plurality of LSI and MEMS wafers, each completed with their own manufacturing technology, are inspected and sorted into individual chips by dicing, and then adjacent to each other. It has been proposed to rearrange and reconstruct as a MEMS integrated wafer. This MEMS reconstructed wafer makes it possible to integrate different types of devices having different device manufacturing techniques, and to reduce the manufacturing cost by reintegrating only the inspection-selected operation devices in a large area. Further, the plurality of LSIs mounted on the MEMS reconstructed wafer and the MEMS are electrically connected by a fine wiring layer. As described above, the pseudo SOC technology in which a plurality of LSIs and MEMSs are rearranged at a chip level and reconstructed as a MEMS integrated wafer has a high integration that cannot be achieved by conventional SIP and a composite that cannot be achieved by SOC. Make it feasible in a short period of time.

JP 2007-260866 A

  However, in the pseudo SOC technology, when the pseudo SOC chip is flip-chip mounted on the circuit wiring board, the pseudo SOC chip is deformed due to the difference in thermal expansion coefficient between the circuit wiring board and the pseudo SOC chip, so that the insulation between different devices is fixed. There was a problem that the organic resin as a material was destroyed. Specifically, this is caused by a difference in thermal expansion coefficient between a pseudo SOC chip that is flip-chip mounted using a bump electrode arranged in the periphery (Peripheral) on the pseudo SOC and a circuit wiring board on which the pseudo SOC chip is mounted. Due to the difference in displacement, the pseudo SOC chip is warped, and the organic resin disposed between different devices of the pseudo SOC chip is stress-destructed. This is mainly because the I / O electrodes are arranged on the periphery of the pseudo SOC chip (Peripheral) for the purpose of relaxing the bump electrode pitch.

  The present invention has been made in view of the above, and eliminates stress breakdown in an organic resin portion, which is an insulating material that fixes different devices, and improves connection reliability of an integrated semiconductor device that is a pseudo SOC chip. An object of the present invention is to provide an integrated semiconductor device that can do this.

In order to solve the above-described problems and achieve the object, the present invention includes an integrated element circuit or a plurality of semiconductor elements having different element outer dimensions, and an insulating material disposed between the plurality of semiconductor elements, The plurality of semiconductor elements, an organic insulating film disposed entirely on the insulating material, a fine thin film wiring disposed on the organic insulating film and connecting the plurality of semiconductor elements to each other, and the plurality An I / O electrode selectively disposed only on a region where the semiconductor element is disposed, and a bump electrode formed on the I / O electrode, wherein the I / O electrode includes the semiconductor It is characterized by being arranged excluding the corners of the element.

  According to the present invention, the I / O electrode of the integrated semiconductor device which is a pseudo SOC chip is arranged on the upper side of the dissimilar device, and is further fixed to the circuit wiring board by the bump electrode formed on the I / O electrode. Therefore, since the integrated semiconductor device fixed with the dissimilar device is effectively relieved of stress by the insulating material that fixes the dissimilar devices, the integrated semiconductor device due to the difference in thermal expansion coefficient between the integrated semiconductor device and the circuit wiring board Overall stress deformation can be prevented. As a result, it is possible to prevent stress breakdown in the organic resin portion which is an insulating material for fixing different devices, and the effect of improving the connection reliability is achieved.

  Exemplary embodiments of an integrated semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the drawings shown below, for convenience of explanation, the scales of the members of the drawings may be described differently. FIG. 1 is a top view of an integrated semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line AA in FIG. In FIG. 1, for convenience of explanation, the LSI chip 2, the MEMS chip 3, and the insulating material 4 existing inside the integrated semiconductor device 1 and the bump electrodes 5 existing on the surface of the integrated semiconductor device 1 are drawn with solid lines. ing. Further, in FIG. 2, the number of bump electrodes 5 is smaller than the number actually present in the cross-sectional view taken along the line AA in FIG.

  An integrated semiconductor device (pseudo-SOC chip) 1 is obtained by rearranging an LSI chip 2 and a MEMS chip 3 at a chip level and reconstructing them as a MEMS integrated wafer, and is manufactured by a pseudo-SOC technology. Therefore, there is no wiring substrate (interposer substrate) that electrically connects the LSI chip 2 and the MEMS chip 3 or the like. Actually, an integrated semiconductor device (pseudo SOC chip) 1 is obtained by dicing a pseudo SOC wafer, which is a MEMS integrated wafer, into individual chips. An integrated semiconductor device (pseudo SOC chip) 1 includes an LSI chip 2, a MEMS chip 3, an insulating material 4, a bump electrode 5, a contact portion 6, an organic insulating film 7, a fine thin film wiring 8, an organic insulating film 9, and an I / O electrode. 10, a MEMS sealing material 11, and a MEMS cavity 12.

  The LSI chip 2 is obtained by dicing a wafer on which an LSI as a semiconductor element is formed into an individual chip after inspection and sorting. The MEMS chip 3 is obtained by dicing a wafer on which a MEMS, which is an electromechanical element, is formed into individual chips after inspection and sorting. In this example, the integrated semiconductor device (pseudo SOC chip) 1 includes five LSI chips 2 (CPU: 2, Driver: 2, Memory: 1) and one MEMS chip 3. However, each LSI chip 2 and MEMS chip 3 are different devices. However, in this example, the above-described configuration is used for explanation. However, the LSI chip 2 and the MEMS chip 3 mounted on the integrated semiconductor device (pseudo SOC chip) 1 are not necessarily limited to this example.

  The insulating material 4 is disposed between the LSI chip 2 and the MEMS chip 3, and if necessary, on the lower surface of the LSI chip 2 and the MEMS chip 3 and on the outer peripheral portion as the integrated semiconductor device (pseudo SOC chip) 1. 2 and the MEMS chip 3 are insulated and fixed to each other. The gap between the LSI chip 2 and the MEMS chip 3 is designed to be as narrow as possible so that the thermal displacement in the insulating material 4 becomes small after the integrated semiconductor device (pseudo SOC chip) 1 and the circuit wiring board 200 are connected. It is preferable to do. In particular, it is more preferable to design the gap between a chip (for example, CPU) that generates a large amount of heat and another chip as narrow as possible. The insulating material 4 is an organic resin, and specifically, it is preferably composed of at least one of an epoxy resin containing at least silica filler, a polyimide resin, and benzocyclobutene (BCB). .

  The bump electrode 5 electrically and mechanically connects the integrated semiconductor device (pseudo SOC chip) 1 and a circuit wiring board 200 described later. The bump electrode 5 is formed on the upper surface of the I / O electrode 10 formed on the LSI chip 2 and the MEMS chip 3 of the integrated semiconductor device (pseudo SOC chip) 1. Depending on the design, an organic insulating film 7, a fine thin film wiring 8, an organic insulating film 9 and the like are formed between the bump electrode 5 (I / O electrode 10) and the LSI chip 2 and the MEMS chip 3. In some cases, the bump electrode 5 (I / O electrode 10) is always selectively formed above the LSI chip 2 and the MEMS chip 3 for the purpose of the present invention.

  As shown in the figure, it can be seen that the bump electrodes 5 (I / O electrodes 10) are not arranged at the corners of the LSI chip 2 and the MEMS chip 3. Therefore, the bump electrode 5 (I / O electrode 10) is not arranged at the corner of the integrated semiconductor device (pseudo SOC chip) 1. This is because when the bump electrodes 5 (I / O electrodes 10) are arranged at the corners of the LSI chip 2 and the MEMS chip 3, the integrated semiconductor device (pseudo SOC chip) 1 and the circuit wiring board 200 are connected to each other. Since stress due to the difference in thermal expansion coefficient between the semiconductor device (pseudo SOC chip) 1 and the circuit wiring board 200 is concentrated on these bump electrodes 5 (I / O electrodes 10), it is possible to prevent a problem that peeling occurs at this portion. Because. Specifically, the bump electrode 5 is preferably made of at least a metal including Ti, Ni, Al, Cu, Au, Ag, Pb, Sn, Pd, and W, or an alloy thereof.

  The contact portion 6 is provided on the upper surface of the LSI chip 2 and the MEMS chip 3 in order to electrically connect the LSI chip 2 and the fine thin film wiring 8 and to electrically connect the MEMS chip 3 and the fine thin film wiring 8. It has been.

  The organic insulating film 7 electrically insulates the LSI chip 2 and the MEMS chip 3 from the fine thin film wiring 8. The organic insulating film 7 is entirely provided on the upper surface other than the contact part 6 of the LSI chip 2 and the contact part 6 of the MEMS chip 3. For example, polyimide resin is used for the organic insulating film 7.

  The fine thin film wiring 8 is provided on the upper surface of the contact portion 6 and the organic insulating film 7 in order to electrically connect the LSI chip 2 and the MEMS chip 3. Specifically, the fine thin film wiring 8 is preferably made of a metal containing at least Ti, Ni, Al, Cu, Au, Pb, Sn, Pd, and W, or an alloy thereof.

  The organic insulating film 9 is entirely provided on the upper surface of the fine thin film wiring 8 other than the portion where the I / O electrode 10 is formed in order to protect the fine thin film wiring 8. For example, a polyimide resin is used for the organic insulating film 9. Depending on the design, the fine thin film wiring 8 and the organic insulating film 9 are not limited to one layer on the organic insulating film 7 but may be a plurality of layers as a multilayer wiring layer.

  The I / O electrode 10 is provided on the upper surface of the fine thin film wiring 8 in order to form the bump electrode 5, and electrically connects the bump electrode 5 and the fine thin film wiring 8. More specifically, the I / O electrode 10 is formed above the LSI chip 2 and the MEMS chip 3 of the integrated semiconductor device (pseudo SOC chip) 1. In addition, Cu / Ni / Ti or Cu / Ti is used for the barrier metal of the bump electrode 5 formed on the upper surface of the I / O electrode 10.

  The MEMS sealing material 11 seals the MEMS movable part of the MEMS chip 3, and the MEMS cavity 12 is a cavity part in which the MEMS movable part surrounded by the MEMS chip 3 and the MEMS sealing material 11 is arranged. It is.

  Next, the reason why the integrated semiconductor device (pseudo SOC chip) 1 is formed as described above will be described in comparison with a conventional integrated semiconductor device. FIG. 3 is a top view of a conventional integrated semiconductor device, and FIG. 4 is a cross-sectional view taken along line AA in FIG. In FIG. 3, for convenience of explanation, the LSI chip 2, the MEMS chip 3, and the insulating material 4 existing in the conventional integrated semiconductor device (pseudo SOC chip) 100 and the integrated semiconductor device (pseudo SOC chip) 100 are shown. The bump electrode 5 existing on the surface is drawn by a solid line.

  Similar to the integrated semiconductor device (pseudo SOC chip) 1 according to the present embodiment, the conventional integrated semiconductor device (pseudo SOC chip) 100 is an LSI chip 2, a MEMS chip 3, an insulating material 4, a bump electrode 5, and a contact portion. 6, an organic insulating film 7, a fine thin film wiring 8, an organic insulating film 9, an I / O electrode 10, a MEMS sealing material 11, and a MEMS cavity 12.

  The conventional integrated semiconductor device (pseudo SOC chip) 100 differs from the integrated semiconductor device (pseudo SOC chip) 1 in the position where the I / O electrode 10 (bump electrode 5) is disposed. In the integrated semiconductor device (pseudo SOC chip) 1, as described above, the I / O electrode 10 (bump electrode 5) is selectively provided above the LSI chip 2 and the MEMS chip 3 of the integrated semiconductor device (pseudo SOC chip) 1. Has been placed. On the other hand, in the conventional integrated semiconductor device (pseudo SOC chip) 100, the I / O electrode 10 (bump electrode 5) is the upper surface of the insulating material 4 region in the outer peripheral portion of the integrated semiconductor device (pseudo SOC chip) 100. It is arranged only (above).

  Here, a case where the conventional integrated semiconductor device (pseudo SOC chip) 100 is flip-chip mounted on the circuit wiring board 200 will be described. FIG. 5 is a cross-sectional view when a conventional integrated semiconductor device (pseudo SOC chip) 100 is flip-chip mounted on a circuit wiring board.

  In this case, since the coefficient of thermal expansion of the conventional integrated semiconductor device (pseudo SOC chip) 100 and the coefficient of thermal expansion of the circuit wiring board 200 are different, there is a difference in displacement between the integrated semiconductor device and the circuit wiring board due to the difference. Arise. In particular, the I / O electrode 10 (bump electrode 5) connected to the circuit wiring board 200 is disposed only on the upper surface (directly above) of the insulating material 4 on the outer periphery of the integrated semiconductor device (pseudo SOC chip) 100. Therefore, a warp (stress deformation) 300 occurs in the integrated semiconductor device (pseudo-SOC chip) 100, and a portion of the integrated semiconductor device (pseudo-SOC chip) 100 disposed between the LSI chip 2 and the MEMS chip 3 There was a problem that the insulating material 4 was subjected to stress fracture.

  Further, on the other hand, a case where the integrated semiconductor device (pseudo SOC chip) 1 according to the present embodiment is flip-chip mounted on the circuit wiring board 200 will be described. FIG. 6 is a cross-sectional view when the integrated semiconductor device (pseudo SOC chip) 1 according to the present embodiment is flip-chip mounted on a circuit wiring board. Also in this case, since the thermal expansion coefficient of the integrated semiconductor device (pseudo SOC chip) 1 and the thermal expansion coefficient of the circuit wiring board 200 are different, a difference in displacement occurs between the integrated semiconductor device and the circuit wiring board due to the difference. . However, the I / O electrode 10 (bump electrode 5) connected to the circuit wiring board 200 is selectively disposed above the LSI chip 2 and the MEMS chip 3 of the integrated semiconductor device (pseudo SOC chip) 1. Therefore, the warp (stress deformation) 300 generated in the integrated semiconductor device (pseudo SOC chip) 1 is relieved by the insulating material 4 disposed in the gap between the LSI chip 2 and the MEMS chip 3. Therefore, the warp (stress deformation) 300 of the integrated semiconductor device (pseudo SOC chip) 1 can be effectively suppressed, and the integrated semiconductor device (pseudo SOC chip) 1 is disposed in the gap between the LSI chip 2 and the MEMS chip 3. It is possible to solve the problem that the portion of the insulating material 4 is subjected to stress fracture due to warpage (stress deformation) of the integrated semiconductor device (pseudo SOC chip) 1. Therefore, the integrated semiconductor device (pseudo SOC chip) 1 according to the present embodiment can improve the connection reliability with the circuit wiring board 200 that is flip-chip mounted.

  In addition, as the circuit wiring board 200, for example, a printed SLC (Surface) of a system in which an insulating layer and a conductor layer are built up on a substrate described in US Pat. No. 4,811,082 or a normal glass epoxy substrate. Laminar Circuit) substrate can be used. Furthermore, it is also possible to use a known flexible substrate having a copper wiring formed on the surface using polyimide resin as a main material of the substrate, and the circuit wiring substrate 200 constituting the electronic circuit device is not particularly limited.

(Method for manufacturing integrated semiconductor device)
Next, a method for manufacturing the integrated semiconductor device according to the present embodiment will be described. 7A to 7C are process cross-sectional views of the integrated semiconductor device (pseudo SOC chip) 1 according to the present embodiment, and correspond to a cross-sectional view taken along line AA in FIG.

  First, as shown in FIG. 7A, an LSI chip 2, a MEMS chip 3, and a glass mask (integrated transfer substrate) 13 are prepared. The glass mask 13 has an organic insulating film 7 having a difference in adhesive strength formed on the surface on which the LSI chip 2 and the MEMS chip 3 are mounted, and a fine wiring pattern 14 is formed on the opposite surface. Yes. In this example, for the purpose of explanation, polyimide (Toray: UR3140) resin, which is a photosensitive resin, is used for the organic insulating film 7.

  Then, as shown in FIG. 7B, the LSI chip 2 and the MEMS chip 3 are mounted on the glass mask 13, and the surfaces of the LSI chip 2 and the MEMS chip 3 (lower surface in the figure) are arranged on the same plane. In practice, a large number of LSI chips 2 and MEMS chips 3 are arranged on the glass mask 13 to constitute a pseudo SOC wafer as a whole.

  Next, as shown in FIG. 7C, the back surfaces (upper surfaces in the drawing) of the LSI chip 2 and the MEMS chip 3 are covered with an insulating material 4. In this example, an epoxy resin containing silica filler is used for the insulating material 4 for explanation. For forming the coating of the insulating material 4, it is preferable to use a vacuum printing technique because the insulating material is disposed without forming voids in the fine regions between the semiconductor elements.

Next, as shown in FIG. 7-4, the surface on which the fine wiring pattern 14 of the glass mask 13 is formed in a state where the LSI chip 2 and the MEMS chip 3 are aligned and mounted on the glass mask 13. To exposure energy 15. The exposure amount is adjusted according to the sensitivity of the photosensitive resin that will be the organic insulating film 7. When using the polyimide (Toray: UR3140) resin described in this example, about 100 mJ / cm ² is preferable.

  Next, as shown in FIG. 7-5, after the glass mask 13 is peeled off, development is performed to selectively open the organic insulating film 7 existing on the surface (lower surface in the drawing) region of the contact portion 6 to form contact vias. 16 is formed. Development was performed using a developer (Toray: DV-505). Note that the surface of the organic insulating film 7 (the lower surface in the drawing) is structurally flat by the manufacturing steps so far in this example.

  Next, as shown in FIG. 7-6, a fine thin film wiring 8 is formed on the surface of the organic insulating film 7 (upper surface in the figure) by a known technique such as EB (electron beam) evaporation or sputtering, and contact is made. The contact portion 6, that is, the LSI chip 2 and the MEMS chip 3 are electrically connected through the via 16. In this example, Al / Ti is used for the fine thin film wiring 8. Since the surface of the organic insulating film 7 (upper surface in the figure) is flat, the fine thin film wiring 8 does not cause disconnection due to a step, and the layers stacked in the subsequent steps also become flat. Finally, the flat I / O electrode 10 can be formed, and the bump electrode 5 can be formed on the I / O electrode 10 with high accuracy.

  Next, as shown in FIG. 7-7, the surface of the fine thin film wiring 8 (upper surface in the figure) is covered with the organic insulating film 9, and the fine thin film wiring 8 and the organic insulating film 9 are formed so as to overlap each other. Therefore, the fine thin film wiring 8 and the organic insulating film 9 are formed in two layers on the organic insulating film 7 in this example. Further, an opening 17 to be the I / O electrode 10 is formed in the organic insulating film 9 on the outermost surface (uppermost surface in the drawing). Here, the opening size of the opening 17 is 50 μm in diameter, and the fine thin film wiring 8 exposed from the opening 17 becomes a part of the I / O electrode 10. In this example, a polyimide (Toray: UR3140) resin that is a photosensitive resin is used for the organic insulating film 9.

  Next, as shown in FIGS. 7-8, the surface of the organic insulating film 9 (upper surface in the figure) is covered with a multilayer metal layer 18 of Cu / Ti by EB (electron beam) deposition. The multilayer metal layer 18 has a multilayer structure in which Cu is formed on the surface of Ti (upper surface in the figure). Finally, the multilayer metal layer 18 formed in the opening 17 is a part of the I / O electrode 10. Thus, it serves as a barrier metal for the bump electrode 5.

  Next, as shown in FIG. 7-9, a resist film 19 having a thickness of 50 μm is formed on the surface of the multilayer metal layer 18 (upper surface in the figure) by spin coating, and then exposed and developed from the opening dimension of the opening 17. An opening 20 having a large diameter of 80 μm is formed. The exposure is performed by irradiating a sufficient amount of energy with respect to the film thickness of the resist film 19, and the development is performed using a developer (AZ400K developer: Hoechst Japan) in this example. In this example, a thick film resist (Hoechst Japan Co., Ltd .: AZ4903) was used for the resist film 19.

Next, as shown in FIG. 7-10, a pseudo SOC wafer in which a portion of the resist film 19 corresponding to the I / O electrode 10 (opening 17) is opened by the opening 20 is formed in the following example. It is immersed in a Pb / Sn plating solution (sulfonic acid solder plating solution) having a composition as described above, and electroplating is performed using Cu / Ti as a cathode and a high-purity eutectic solder plate as an anode. The current density is 1 to 4 (A / dm ² ), and while gently stirring at a bath temperature of 25 ° C., the solder composition (Pb / Sn) is almost equal to the eutectic composition, or slightly on the Pb side or Sn side. The PbSn solder alloy 21 having the transferred composition is deposited on the multilayer metal layer 18 in the opening 20 by 50 μm. Finally, the PbSn solder alloy 21 becomes the bump electrode 5.

Composition of sulfonic acid solder plating solution
Tin ion (Sn2 +) 12Vol%
Lead ion (Pb2 +) 30Vol%
Aliphatic sulfonic acid 41 Vol%
Nonionic surfactant 5Vol%
Cationic surfactant 5Vol%
Isopropyl alcohol 7Vol%

  Next, as shown in FIGS. 7-11, the resist film 19 made of AZ4903 formed as a resist for electroplating is removed with acetone.

  Next, as shown in FIGS. 7-12, Cu is etched away by dipping in a solution composed of citric acid / hydrogen peroxide solution, and further, diamine amine 4 acetic acid / ammonia / hydrogen peroxide solution / pure water. The multilayer metal layer 18 is removed by immersing it in a mixed solution consisting of the above and etching away Ti. As a result, all but the multilayer metal layer 18 existing on the back surface (lower surface in the figure) of the PbSn solder alloy 21 is removed.

  Next, as shown in FIG. 7-13, the PbSn solder alloy 21 becomes a spherical bump electrode 5 by reflowing the pseudo-SOC wafer.

  Finally, the integrated semiconductor device (pseudo SOC chip) 1 is completed by dicing the pseudo SOC wafer completed through the above steps into individual chips.

(Flip chip mounting)
Further, a method of flip-chip mounting the integrated semiconductor device (pseudo SOC chip) 1 manufactured by the integrated semiconductor device manufacturing method described with reference to FIGS. 7-1 to 7-13 on the circuit wiring board 200 will be described. Specifically, using a flip chip bonder that has a half mirror, which is a known technique, and performs alignment, the electrode terminals of the circuit wiring board 200 and the bump electrodes 5 of the integrated semiconductor device (pseudo SOC chip) 1 are used. Perform alignment. The integrated semiconductor device (pseudo SOC chip) 1 is held by a collet having a heating mechanism and preheated in a nitrogen atmosphere at 350 ° C.

Next, with the bump electrode 5 of the integrated semiconductor device (pseudo SOC chip) 1 and the electrode terminal of the circuit wiring board 200 being in contact with each other, the collet is further moved downward to apply a pressure of 30 kg / mm ^2. In this state, the temperature is raised to 370 ° C. to melt the solder, and the integrated semiconductor device (pseudo SOC chip) 1 and the electrode terminal of the circuit wiring board 200 are connected. By performing the steps as described above, the integrated semiconductor device (pseudo SOC chip) 1 can be flip-chip mounted on the circuit wiring board 200 as shown in FIG.

  In addition, it is also possible to arrange sealing resin, which is a known technique, in a gap portion between the integrated semiconductor device (pseudo SOC chip) 1 and the circuit wiring board 200 as necessary. As the resin to be sealed, for example, an epoxy resin containing 45 wt% of a bisphenol-based epoxy and an imidazole effect catalyst, an acid anhydride effect agent, and a spherical quartz filler can be used.

  Further, for example, 100 parts by weight of a cresol novolak type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.), 54 parts by weight of phenol resin as a curing agent, 100 parts by weight of fused silica as a filler, benzyldimethylamine 0 as a catalyst It is also possible to use an epoxy resin melt obtained by pulverizing, mixing and melting 3 parts by weight of carbon black and 3 parts by weight of a silane coupling agent as other additives, and the material is not particularly limited. Absent.

  Next, connection reliability when the conventional integrated semiconductor device (pseudo SOC chip) 100 is flip-chip mounted on the circuit wiring board 200 by the method described above, and the integrated semiconductor device described with reference to FIGS. The result of comparative evaluation of connection reliability when the integrated semiconductor device (pseudo SOC chip) 1 manufactured by the above manufacturing method is flip-chip mounted on the circuit wiring board 200 by the above-described method will be described.

  Specifically, the conventional integrated semiconductor device (pseudo SOC chip) 100 having 256 pins of bump electrodes 5 within a dimension of 20 mm × 5 mm and the present embodiment having 256 pins of bump electrodes 5 within a dimension of 20 mm × 5 mm. The connection reliability of the sample when the integrated semiconductor device (pseudo SOC chip) 1 according to the above was flip-chip mounted on the circuit wiring board 200 was evaluated. The number of samples was 1000, and the temperature cycle test conditions were “-55 ° C. (30 min) to 25 ° C. (5 min) to 125 ° C. (30 min) to 25 ° C. (5 min)” in any case. A case where the connection was opened even at one of the 256 pins was regarded as defective.

  As a result, in the conventional integrated semiconductor device (pseudo SOC chip) 100, the insulating material of the portion disposed between the LSI chip 2 and the MEMS chip 3 of the integrated semiconductor device (pseudo SOC chip) 100 at the end of 1500 cycles. Failure due to stress fracture of 4 was confirmed at a rate of 100%.

  In contrast, in the integrated semiconductor device (pseudo SOC chip) 1 according to the present embodiment, the integrated semiconductor device (pseudo SOC chip) 1 is arranged between the LSI chip 2 and the MEMS chip 3 of the integrated semiconductor device (pseudo SOC chip) 1 even at the end of the 3000 cycles. It was confirmed that the failure due to the stress fracture of the insulating material 4 in the existing portion was not confirmed, and the connection reliability was extremely improved.

  As described above, according to the integrated semiconductor device according to the present embodiment, the I / O electrode of the integrated semiconductor device which is a pseudo SOC chip is selectively arranged on the upper side of the different device, and further on the I / O electrode. Because the structure is fixed to the circuit wiring board by the formed bump electrodes, the integrated semiconductor device fixed by the dissimilar device is relieved of stress by the insulating material that fixes between the dissimilar devices. The entire integrated semiconductor device is not subjected to stress deformation due to the difference in thermal expansion coefficient of the substrate, and it is possible to prevent stress breakdown in the insulating material part that fixes between different devices, thereby easily improving the connection reliability of the integrated semiconductor device It becomes possible to improve.

  The present invention is not limited to the above embodiments, but is effective for all integrated semiconductor devices configured by mounting a plurality of semiconductor elements.

1 is a top view of an integrated semiconductor device according to an embodiment of the present invention. AA arrow sectional drawing of FIG. The top view of the conventional integrated semiconductor device. AA arrow sectional drawing of FIG. Sectional drawing at the time of flip-chip mounting the conventional integrated semiconductor device on a circuit wiring board. Sectional drawing at the time of flip-chip mounting the integrated semiconductor device concerning this Embodiment on a circuit wiring board. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment. FIG. 10 is a process cross-sectional view of the integrated semiconductor device according to the embodiment.

Explanation of symbols

1, 31 Integrated semiconductor device (pseudo SOC chip)
2 LSI chip 3 MEMS chip 4 Insulating material 5 Bump electrode 6 Contact part 7, 9 Organic insulating film 8 Fine thin film wiring 10 I / O electrode 11 MEMS sealing material 12 MEMS cavity 13 Glass mask (integrated transfer substrate)
DESCRIPTION OF SYMBOLS 14 Fine wiring pattern 15 Exposure energy 16 Contact via | veer 17, 20 Opening part 18 Multilayer metal layer 19 Resist film 21 PbSn solder alloy 100 Conventional integrated semiconductor device (pseudo SOC chip)
200 Circuit wiring board 300 Warpage (stress deformation)

Claims (5)

A plurality of semiconductor devices having different integrated device circuits or device outer dimensions;
An insulating material disposed between the plurality of semiconductor elements;
An organic insulating film disposed entirely on the plurality of semiconductor elements and the insulating material;
A fine thin film wiring disposed on the organic insulating film and connecting the semiconductor elements to each other;
An I / O electrode selectively disposed only on a region where the plurality of semiconductor elements are disposed;
A bump electrode formed on the I / O electrode,
The I / O electrode is disposed excluding a corner of the semiconductor element;
An integrated semiconductor device characterized by the above.   The integrated semiconductor device according to claim 1, wherein at least one of the plurality of semiconductor elements is an electromechanical element. The integrated semiconductor device includes:
3. The integrated semiconductor device according to claim 1, wherein the bump electrode is flip-chip mounted on a circuit wiring board.   4. The insulating material according to claim 1, wherein the insulating material is composed of at least one of an epoxy resin containing at least silica filler, a polyimide resin, and benzocyclobutene (BCB). The integrated semiconductor device according to one item.   The bump electrode is made of a metal containing at least Ti, Ni, Al, Cu, Au, Ag, Pb, Sn, Pd, or W, or an alloy thereof. The integrated semiconductor device according to any one of the above.

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