JP3410199B2 - Device for preventing bridging of connection member, semiconductor integrated circuit having the same, and mounting substrate - Google Patents

Device for preventing bridging of connection member, semiconductor integrated circuit having the same, and mounting substrate

Info

Publication number
JP3410199B2
JP3410199B2 JP05326494A JP5326494A JP3410199B2 JP 3410199 B2 JP3410199 B2 JP 3410199B2 JP 05326494 A JP05326494 A JP 05326494A JP 5326494 A JP5326494 A JP 5326494A JP 3410199 B2 JP3410199 B2 JP 3410199B2
Authority
JP
Japan
Prior art keywords
connecting member
land
gear
substrate
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP05326494A
Other languages
Japanese (ja)
Other versions
JPH07235761A (en
Inventor
貴志 赤坂
明彦 奥洞
裕司 尾崎
夏也 石川
睦禎 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP05326494A priority Critical patent/JP3410199B2/en
Publication of JPH07235761A publication Critical patent/JPH07235761A/en
Application granted granted Critical
Publication of JP3410199B2 publication Critical patent/JP3410199B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【目次】以下の順序で本発明を説明する。 産業上の利用分野 従来の技術(図7及び図8) 発明が解決しようとする課題(図9〜図11) 課題を解決するための手段(図1及び図3) 作用(図1及び図3) 実施例(図1〜図6) 発明の効果[Table of Contents] The present invention will be described in the following order. Industrial applications Conventional technology (Figs. 7 and 8) Problems to be Solved by the Invention (FIGS. 9 to 11) Means for Solving the Problems (FIGS. 1 and 3) Action (Figs. 1 and 3) Example (FIGS. 1 to 6) The invention's effect

【0002】[0002]

【産業上の利用分野】本発明は接続部材の橋絡防止装置
並びにこれを有する半導体集積回路及び実装基板に関
し、例えばチツプ部品を基板上に形成された導体パター
ンに接続する際に適用して好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bridging prevention device for a connecting member, a semiconductor integrated circuit having the same, and a mounting board, and is suitable for application when, for example, a chip part is connected to a conductor pattern formed on the board. It is something.

【0003】[0003]

【従来の技術】従来、端子数の増大に対応するため集積
回路が形成されたベアチツプのままで基板に直接接続さ
れるものがある。図7に示すように、フリツプチツプボ
ンデイング方式の半導体集積回路チツプ(以下チツプと
いう)1は、外周部に一列に電極2を形成されている。
この電極2上には、はんだ等の金属材料をほぼ球状に盛
り上げたバンプ3があらかじめ形成される。
2. Description of the Related Art Conventionally, in order to cope with an increase in the number of terminals, there is a device in which an integrated circuit is directly connected to a substrate in a bare chip. As shown in FIG. 7, a flip chip bonding type semiconductor integrated circuit chip (hereinafter referred to as a chip) 1 has electrodes 2 formed in a line on the outer peripheral portion.
On the electrode 2, a bump 3 in which a metal material such as solder is raised in a substantially spherical shape is formed in advance.

【0004】アルミナ等でなる基板4上には、ほぼ正方
形の銅パターンでなるランド5がチツプ1の電極2と同
一のピツチと所定のギヤツプとを有するように一列に形
成されている。このランド5上にもあらかじめバンプ6
が形成される。この後、チツプ1は電極2側を下に向け
られ、電極2とランド5との位置を合わせて基板4上に
載置される。続いて、上下のバンプ3及び6は加熱さ
れ、流動化して一体となる。この後、冷却すると、図8
に示すように、チツプ1と基板4とは電気的及び物理的
に接続される。
On a substrate 4 made of alumina or the like, lands 5 made of a substantially square copper pattern are formed in a line so as to have the same pitch as the electrode 2 of the chip 1 and a predetermined gear. The bumps 6 are also previously formed on this land 5.
Is formed. After that, the chip 1 is placed on the substrate 4 with the electrode 2 side facing downward and the electrode 2 and the land 5 aligned with each other. Subsequently, the upper and lower bumps 3 and 6 are heated and fluidized to be integrated. After this, when cooled, FIG.
As shown in, the chip 1 and the substrate 4 are electrically and physically connected.

【0005】[0005]

【発明が解決しようとする課題】ところで上述のフリツ
プチツプボンデイング方式では、図9に示すように、ラ
ンド5相互のギヤツプD1が十分に大きい場合、上下の
バンプ3及び6が溶融するとき、隣接するランド5上の
バンプ3及び6が相互に接触することはない。
By the way, in the flip chip bonding method described above, as shown in FIG. 9, when the gap D1 between the lands 5 is sufficiently large, when the upper and lower bumps 3 and 6 are melted, they are adjacent to each other. The bumps 3 and 6 on the land 5 are not in contact with each other.

【0006】ところがランド5相互のピツチが狭く、従
つてギヤツプD1が狭い場合、図10に示すように、バ
ンプ3及び6を流動化したとき、隣接するランド5より
はみ出したはんだによつてバンプ3及び6は橋絡するお
それが高くなるという問題があつた。
However, when the pitch between the lands 5 is narrow and therefore the gear D1 is narrow, as shown in FIG. 10, when the bumps 3 and 6 are fluidized, the bumps 3 are formed by the solder protruding from the adjacent lands 5. In Nos. 6 and 6, there was a problem that the risk of bridging increased.

【0007】また図11に示すように、あらかじめ長手
方向がバンプ6の並び方向と直角方向に向く長方形のラ
ンド8を形成すれば、バンプ3及び6を加熱して流動化
したとき、余分のはんだはランド8の長手方向に流れ、
隣合うランド8上のバンプ3及び6が相互に橋絡するこ
とを防止し得る。ところがこの方法では、ランド8上に
あらかじめバンプ6を形成するとき、はんだがランド8
の長手方向に流れてしまう。このためバンプ6がそれぞ
れ異なる形状に形成されて、チツプ1を接続するとき接
続不良が発生するおそれがあるという欠点がある。
Also, as shown in FIG. 11, if a rectangular land 8 whose longitudinal direction is oriented in a direction perpendicular to the direction in which the bumps 6 are arranged is formed beforehand, excess solder is applied when the bumps 3 and 6 are heated and fluidized. Flows in the longitudinal direction of the land 8,
It is possible to prevent the bumps 3 and 6 on the adjacent lands 8 from bridging each other. However, in this method, when the bumps 6 are formed on the lands 8 in advance, the solder is
Will flow in the longitudinal direction. For this reason, the bumps 6 are formed in different shapes, and there is a drawback in that connection failure may occur when the chips 1 are connected.

【0008】本発明は以上の点を考慮してなされたもの
で、チツプ部品を基板に接続するとき、隣合うバンプが
余分な接続部材で相互に橋絡することを防止し得る接続
部材の橋絡防止装置並びにこれを有する半導体集積回路
及び実装基板を提案しようとするものである。
The present invention has been made in consideration of the above points, and when connecting a chip component to a substrate, a bridge of connecting members which can prevent adjacent bumps from bridging each other with an extra connecting member. The present invention intends to propose a leakage prevention device, a semiconductor integrated circuit having the same, and a mounting board.

【0009】[0009]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、基板11上に、相互に第1のギヤ
ツプD1を介して一列に配列された導電性材料でなり、
それぞれ導電性の接続部材が付着される複数のランド5
と、基板11上に、ランド5と隣合いかつランド5の配
列方向とほぼ直交する方向に形成された接続部材誘導手
段17とを設けた。そして、接続部材誘導手段17とラ
ンド5との第2のギヤツプD2を第1のギヤツプD1に
比して狭く設定するとともに、接続部材誘導手段17は
基板11の表面の一部が凹状に形成された誘導溝でな
り、当該誘導溝の底面がランドから離れるに従つて深く
なるように形成した。
In order to solve the above problems, in the present invention, the conductive material is arranged in a line on the substrate 11 with the first gear D1 interposed therebetween.
A plurality of lands 5 to which conductive connecting members are attached respectively
Then, the connecting member guiding means 17 formed adjacent to the land 5 and in a direction substantially orthogonal to the arrangement direction of the lands 5 was provided on the substrate 11. The second gear D2 between the connecting member guiding means 17 and the land 5 is set narrower than the first gear D1 and the connecting member guiding means 17 is formed such that a part of the surface of the substrate 11 is concave. The guide groove is formed such that the bottom surface of the guide groove becomes deeper as it goes away from the land.

【0010】[0010]

【作用】基板11上に、ランド5と隣合いかつランド5
相互の配列方向とほぼ直交する方向に、ランド5に対す
るギヤツプD2をランド相互のギヤツプD1に比して狭
く設定した接続部材誘導手段17を配し、当該接続部材
誘導手段17を、基板11の表面の一部を凹状に形成し
て構成し、その底面がランドから離れるに従つて深くな
るようにしたことにより、バンプ3及び6のうち余分な
接続部材は隣合うバンプ3及び6に到達する前に、接続
部材誘導手段17に到達して誘導される。これにより隣
合うバンプ3及び6が余分な接続部材で相互に短絡する
ことを防止し得る。
Operation: The land 5 is adjacent to the land 5 on the substrate 11.
The connecting member guiding means 17 in which the gear D2 for the land 5 is set narrower than the mutual gear D1 is arranged in a direction substantially orthogonal to the mutual arrangement direction, and the connecting member guiding means 17 is arranged on the surface of the substrate 11. Part of the bumps 3 and 6 is formed in a concave shape, and the bottom surface thereof becomes deeper as it goes away from the land, so that the excess connection member of the bumps 3 and 6 reaches the adjacent bumps 3 and 6. Then, the connecting member guiding means 17 is reached and guided. This can prevent the adjacent bumps 3 and 6 from being short-circuited to each other by an extra connecting member.

【0011】[0011]

【実施例】以下図面について、本発明の一実施例を詳述
する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

【0012】図7との対応部分に同一符号を付して示す
図1において、10は全体としてチツプ1をフリツプチ
ツプボンデイング方式で接続する基板11側のはんだ付
け部を示す。はんだ付け部10は、従来の場合と同様に
ほぼ正方形の銅パターンでなるランド5が基板11上に
一列に形成されている。これに加えて、はんだ付け部1
0は、基板11の表面の一部が凹状に形成された長方形
のはんだ誘導溝12がそれぞれのランド5の近くに形成
されている。
In FIG. 1 in which parts corresponding to those in FIG. 7 are designated by the same reference numerals, reference numeral 10 indicates a soldering portion on the side of the substrate 11 for connecting the chip 1 as a whole by flip chip bonding. In the soldering portion 10, lands 5 each having a substantially square copper pattern are formed in a line on the substrate 11 as in the conventional case. In addition to this, the soldering part 1
In No. 0, a rectangular solder guiding groove 12 in which a part of the surface of the substrate 11 is formed in a concave shape is formed near each land 5.

【0013】はんだ誘導溝12は、ランド5から見てラ
ンド5の配列方向と直交する方向に形成されている。ま
たはんだ誘導溝12は、長辺がランド5の配列方向と直
交する方向に形成され、短辺がランド5の対向する辺と
同一の長さに形成されている。はんだ誘導溝12の底面
12Aは基板11の面と平行に形成されている。
The solder guiding groove 12 is formed in a direction orthogonal to the arrangement direction of the lands 5 when viewed from the lands 5. The solder guiding groove 12 has a long side formed in a direction orthogonal to the arrangement direction of the lands 5 and a short side formed to have the same length as the facing sides of the lands 5. The bottom surface 12A of the solder guiding groove 12 is formed parallel to the surface of the substrate 11.

【0014】さらにはんだ誘導溝12はランド5との間
に平行なギヤツプD2を設けられている。このギヤツプ
D2はランド5相互のギヤツプD1に比して一段と小さ
く形成されている。これにより基板11とチツプ1との
はんだ付けのときの流動化した余分なはんだは、水平に
張り出して隣合うランド5上のバンプ6と接触する前
に、はんだ誘導溝12に達して流れ込むようになされて
いる。
Further, the solder guide groove 12 is provided with a parallel gap D2 between itself and the land 5. This gear D2 is formed to be much smaller than the gear D1 of each land 5. As a result, excess solder that has been fluidized during soldering of the substrate 11 and the chip 1 reaches the solder guiding groove 12 before flowing out horizontally before coming into contact with the bumps 6 on the adjacent lands 5. Has been done.

【0015】以上の構成において、ランド5上に予めバ
ンプ6を形成するとき、それぞれのランド5上には所定
量に調整したはんだが付着される。これによりはんだは
表面張力によつて正方形のランド5上面の境界以内に止
まる。従つてバンプ6はランド5の外に流れ出ず、従来
と同様のほぼ球状に形成される。この後、図2に示すよ
うに、基板11の上には、バンプ3及び6の位置を合わ
せてチツプ1が載置される。続いて、上下のバンプ3及
び6は加熱されて溶融する。
In the above structure, when the bumps 6 are formed on the lands 5 in advance, the solder adjusted to a predetermined amount is attached to each of the lands 5. As a result, the solder stops within the boundary of the upper surface of the square land 5 due to surface tension. Therefore, the bump 6 does not flow out of the land 5 and is formed into a substantially spherical shape similar to the conventional one. After that, as shown in FIG. 2, the chip 1 is placed on the substrate 11 with the bumps 3 and 6 aligned with each other. Subsequently, the upper and lower bumps 3 and 6 are heated and melted.

【0016】このとき図3に示すように、溶融したバン
プ3及び6がランド5から張り出した場合、溶融したバ
ンプ3及び6のうち接続に必要でない余分なはんだは、
隣合うバンプ3及び6に接触する前に、はんだ誘導溝1
2に到達して重力により流れ込む。従つて隣合うバンプ
3及び6が余分なはんだで相互に橋絡することが防止さ
れる。
At this time, as shown in FIG. 3, when the melted bumps 3 and 6 are projected from the land 5, extra solder not necessary for connection among the melted bumps 3 and 6 is
Before contacting the adjacent bumps 3 and 6, the solder guiding groove 1
It reaches 2 and flows in by gravity. Therefore, the adjacent bumps 3 and 6 are prevented from bridging each other with extra solder.

【0017】以上の構成によれば、基板11上に、ラン
ド5と隣合いかつランド5相互の配列方向とほぼ直交す
る方向に、ランド5に対するギヤツプD2をランド5相
互のギヤツプD1に比して狭く設定したはんだ誘導溝1
2を配したことによつて、バンプ3及び6がランド5か
ら張り出した場合、バンプ3及び6のうち余分なはんだ
は隣合うバンプ3及び6に到達する前に、はんだ誘導溝
12に到達して重力により流れ込む。これにより隣合う
バンプ3及び6が余分なはんだで相互に橋絡することが
防止できる。
According to the above structure, the gear D2 for the land 5 is arranged on the substrate 11 in the direction adjacent to the land 5 and substantially orthogonal to the arrangement direction of the lands 5, as compared with the gear D1 of the lands 5. Narrowly set solder guide groove 1
As a result of arranging 2, when the bumps 3 and 6 are projected from the land 5, excess solder of the bumps 3 and 6 reaches the solder guiding groove 12 before reaching the adjacent bumps 3 and 6. Flows by gravity. This can prevent adjacent bumps 3 and 6 from bridging each other with extra solder.

【0018】またランド5上に予めバンプ6を形成する
とき、従来の場合と同様のほぼ正方形のランド5を基板
11上に形成することによつて、長いランド8上にバン
プ6を形成する場合のはんだの流れを防止して、ほぼ均
一な形状のバンプ6を形成できる。
When the bumps 6 are formed on the lands 5 in advance, the bumps 6 are formed on the long lands 8 by forming the substantially square lands 5 on the substrate 11 as in the conventional case. The solder flow can be prevented and the bumps 6 having a substantially uniform shape can be formed.

【0019】なお上述の実施例においては、はんだ誘導
溝12の底面12Aが基板11の面と平行に形成されて
いる場合について述べたが、本発明はこれに限らず、図
4に示すように、はんだ付け部15のはんだ誘導溝17
をすべり台状に形成しても良い。この場合にも上述と同
様の効果を得ることができる。
In the above embodiment, the case where the bottom surface 12A of the solder guiding groove 12 is formed parallel to the surface of the substrate 11 has been described, but the present invention is not limited to this, and as shown in FIG. , The solder guiding groove 17 of the soldering portion 15
May be formed in a slide shape. Also in this case, the same effect as described above can be obtained.

【0020】また上述の実施例においては、ギヤツプD
2を設ける場合について述べたが、本発明はこれに限ら
ず、予めバンプ6を形成するとき、はんだが表面張力に
よつて正方形のランド5上面の境界以内に止まることに
より、ギヤツプD2はなくても良い。
In the above embodiment, the gear D
However, the present invention is not limited to this, and when the bumps 6 are formed in advance, the solder stops within the boundary of the upper surface of the square land 5 due to surface tension, so that the gear tape D2 is eliminated. Is also good.

【0021】さらに上述の実施例においては、はんだ誘
導溝12の表面にはんだとのぬれ性を良くする処理をし
ていない場合について述べたが、本発明はこれに限ら
ず、はんだ誘導溝の表面に銅パターン等のはんだとのぬ
れ性を良くする部材を配設しても良い。
Further, in the above-mentioned embodiment, the case where the surface of the solder guiding groove 12 is not treated to improve the wettability with the solder has been described, but the present invention is not limited to this, and the surface of the solder guiding groove is not limited to this. Alternatively, a member such as a copper pattern that improves wettability with solder may be provided.

【0022】さらに上述の実施例においては、接続に余
分なはんだが平行なギヤツプD2上を通過してはんだ誘
導溝12に流れ込むようにした場合について述べたが、
本発明はこれに限らず、ランドの端面のうちはんだ誘導
溝側の形状を直線以外の形状に形成することによつて余
分なはんだがはんだ誘導溝に容易に流れ込むようにして
も良い。
Further, in the above-mentioned embodiment, the case has been described in which the excess solder for connection passes over the parallel gap D2 and flows into the solder guiding groove 12.
The present invention is not limited to this, and excess solder may easily flow into the solder guiding groove by forming the shape of the end surface of the land on the side of the solder guiding groove other than a straight line.

【0023】図5に示すように、はんだ付け部19は、
基板20上に従来の場合と同様にほぼ正方形のランド5
が形成されていると共に、はんだ誘導溝21がランド5
との間にギヤツプを設けずに形成されている。またラン
ド5とはんだ誘導溝21との間には、スルーホール(こ
こでは半円筒形状)22が開けられている。これにより
溶融したバンプがランドから張り出した場合、余分なは
んだはスルーホール22を通じてはんだ誘導溝21の底
面21Aに配された銅パターン等のぬれ性のよい部材2
3に容易に流れ込むようになされている。
As shown in FIG. 5, the soldering portion 19 is
The land 5 of a substantially square shape is formed on the substrate 20 as in the conventional case.
And the solder guide groove 21 is formed on the land 5.
It is formed without providing a gear gap between and. Further, a through hole (here, a semi-cylindrical shape) 22 is opened between the land 5 and the solder guiding groove 21. When the melted bumps are projected from the land as a result of this, excess solder is provided on the bottom surface 21A of the solder guiding groove 21 through the through hole 22 and has a good wettability, such as a copper pattern.
It is designed to easily flow into 3.

【0024】さらに上述の実施例においては、接続に余
分なはんだを誘導するためはんだ誘導溝12を配設する
場合について述べたが、本発明はこれに限らず、溝以外
の手段で余分なはんだを誘導するようにしても良い。例
えば図6に示すように、はんだ付け部25は、正方形の
ランド5の近くの基板26上に、銅パターンでなる正方
形のはんだ誘導ランド27が形成されている。ランド5
とはんだ誘導ランド27とのギヤツプD3はランド5相
互のギヤツプD1に比して狭く形成されている。これに
より溶融したバンプがランドから張り出した場合、余分
なはんだは、隣合うバンプと橋絡する前に、基板11に
比してぬれ性が高いはんだ誘導ランド27に流れ込む。
Further, in the above-described embodiment, the case where the solder guiding groove 12 is provided for guiding the excessive solder to the connection has been described, but the present invention is not limited to this, and the extra solder may be formed by means other than the groove. May be guided. For example, as shown in FIG. 6, in the soldering portion 25, a square solder guiding land 27 having a copper pattern is formed on the substrate 26 near the square land 5. Land 5
The gear D3 between the solder guiding land 27 and the solder guiding land 27 is formed narrower than the gear D1 between the lands 5. When the melted bump protrudes from the land by this, the excess solder flows into the solder guiding land 27 having higher wettability than the substrate 11 before bridging with the adjacent bump.

【0025】さらに上述の実施例においては、ランド5
がほぼ正方形に形成され、ランド5の近くに長方形のは
んだ誘導溝12や正方形のはんだ誘導ランド27を形成
する場合について述べたが、本発明はこれに限らず、は
んだ誘導溝の形状は長方形以外の形状でも良く、はんだ
誘導ランドの形状は正方形以外の形状でも良い。またラ
ンドをほぼ円形に形成する場合にも適用できる。この場
合にもバンプがほぼ球状に形成できる。さらにこのほぼ
円形のランドに沿うような形状のはんだ誘導溝やはんだ
誘導ランドを形成する場合にも適用できる。
Further, in the above embodiment, the land 5
Has been described as having a substantially square shape, and the rectangular solder guiding groove 12 and the square solder guiding land 27 are formed near the land 5, but the present invention is not limited to this, and the shape of the solder guiding groove is not rectangular. The shape of the solder induction land may be a shape other than a square. It can also be applied to the case where the land is formed into a substantially circular shape. Also in this case, the bumps can be formed into a substantially spherical shape. Further, it can be applied to the case of forming a solder guiding groove or a solder guiding land having a shape along the substantially circular land.

【0026】上述の実施例においては、チツプ1をはん
だで接続する場合について述べたが、本発明はこれに限
らず、例えば抵抗やコンデンサ等、半導体集積回路以外
の単体のチツプ部品を接続する場合や、はんだ以外の接
続部材でなるバンプのうち流動化した余分な接続部材を
誘導する場合にも適用できる。
In the above-described embodiments, the case where the chip 1 is connected by solder has been described, but the present invention is not limited to this, and in the case of connecting a single chip component other than the semiconductor integrated circuit such as a resistor or a capacitor. Alternatively, the invention can be applied to the case of guiding a fluidized extra connection member of a bump made of a connection member other than solder.

【0027】[0027]

【発明の効果】上述のように本発明によれば、基板上
に、ランドと隣合いかつランド相互の配列方向とほぼ直
交する方向に、ランドに対するギヤツプをランド相互の
ギヤツプに比して狭く設定した接続部材誘導手段を配
し、当該接続部材誘導手段を、基板の表面の一部を凹状
に形成して構成し、その底面がランドから離れるに従つ
て深くなるようにしたことにより、バンプがランドから
張り出した場合、バンプのうちの余分な接続部材は隣合
うバンプに到達する前に、接続部材誘導手段に到達して
誘導される。これにより隣合うバンプが余分な接続部材
で相互に短絡することを防止し得る接続部材の橋絡防止
装置を実現できる。
As described above, according to the present invention, the gear gap for the land is set narrower than the gear gap for the lands in the direction adjacent to the lands and substantially orthogonal to the arrangement direction of the lands on the substrate. By disposing the connecting member guiding means, the connecting member guiding means is formed by forming a part of the surface of the substrate in a concave shape, and the bottom surface becomes deeper as the distance from the land increases. When protruding from the land, the extra connection member of the bump reaches and is guided to the connection member guiding means before reaching the adjacent bump. As a result, it is possible to realize a bridging prevention device for connecting members, which can prevent adjacent bumps from being short-circuited by an extra connecting member.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による接続部材の橋絡防止装置の一実施
例による基板側のはんだ付け部の構成を示す略線図であ
る。
FIG. 1 is a schematic diagram showing a structure of a soldering portion on a board side according to an embodiment of a bridging prevention device for a connecting member according to the present invention.

【図2】溶融前の上下のバンプの状態を示す略線図であ
る。
FIG. 2 is a schematic diagram showing a state of upper and lower bumps before melting.

【図3】溶融したバンプのうち余分なはんだがはんだ誘
導溝に流れ込んだ状態を示す略線図である。
FIG. 3 is a schematic diagram showing a state in which excessive solder in a melted bump has flowed into a solder guide groove.

【図4】他の実施例による基板側のはんだ付け部の構成
を示す略線図である。
FIG. 4 is a schematic diagram showing a structure of a soldering portion on a board side according to another embodiment.

【図5】他の実施例による基板側のはんだ付け部の構成
を示す略線図である。
FIG. 5 is a schematic diagram showing a configuration of a soldering portion on a board side according to another embodiment.

【図6】他の実施例による基板側のはんだ付け部の構成
を示す略線図である。
FIG. 6 is a schematic diagram showing a structure of a soldering portion on a board side according to another embodiment.

【図7】従来の基板側のはんだ付け部の構成及び位置合
わせのときの上下のバンプの形状を示す略線図である。
FIG. 7 is a schematic diagram showing a configuration of a conventional soldering portion on a substrate side and shapes of upper and lower bumps at the time of alignment.

【図8】溶融して一体となつたときの上下のバンプの形
状を示す略線図である。
FIG. 8 is a schematic diagram showing the shapes of upper and lower bumps when they are melted and integrated.

【図9】基板上のランドの形状及びバンプの形状を示す
略線図である。
FIG. 9 is a schematic diagram showing the shapes of lands and bumps on a substrate.

【図10】溶融して橋絡したバンプを示す略線図であ
る。
FIG. 10 is a schematic diagram showing a fused and bridged bump.

【図11】長方形のランド上に形成されるバンプの形状
がそれぞれ異なつていることを示す略線図である。
FIG. 11 is a schematic diagram showing that bumps formed on rectangular lands have different shapes.

【符号の説明】[Explanation of symbols]

1……半導体集積回路チツプ、2……電極、バンプ3…
…、4、11、16、20、26……基板、5、8……
ランド、6……バンプ、10、15、19、25……は
んだ付け部、12、17、21……はんだ誘導溝、12
A、21A……底面、22……スルーホール、27……
はんだ誘導ランド、D1、D2、D3……ギヤツプ。
1 ... Semiconductor integrated circuit chip, 2 ... Electrode, bump 3 ...
... 4, 11, 16, 20, 26 ... substrate, 5, 8 ...
Land, 6 ... Bump, 10, 15, 19, 25 ... Soldering part, 12, 17, 21 ... Solder guide groove, 12
A, 21A ... bottom, 22 ... through hole, 27 ...
Solder induction land, D1, D2, D3 ... Gear cup.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 石川 夏也 東京都品川区北品川6丁目7番35号ソニ ー株式会社内 (72)発明者 伊藤 睦禎 東京都品川区北品川6丁目7番35号ソニ ー株式会社内 (56)参考文献 特開 平5−327196(JP,A) 実開 平5−4545(JP,U) (58)調査した分野(Int.Cl.7,DB名) H05K 3/34 H01L 21/60 H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Natsuya Ishikawa 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Mutsu Ito 6-7 Kita-Shinagawa, Shinagawa-ku, Tokyo No. 35 in Sony Corporation (56) References JP-A-5-327196 (JP, A) Actual development 5-4545 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H05K 3/34 H01L 21/60 H01L 23/12

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基板上に、相互に第1のギヤツプを介して
一列に配列された導電性材料でなり、それぞれ導電性の
接続部材が付着される複数のランドと 上記基板上に、上記ランドと隣合いかつ上記ランドの配
列方向とほぼ直交する方向に形成された接続部材誘導手
段とを具え、 上記接続部材誘導手段と上記ランドとの第2のギヤツプ
が上記第1のギヤツプに比して狭く設定されており、 上記接続部材誘導手段は、上記基板の表面の一部が凹状
に形成された誘導溝でなり、当該誘導溝の底面が上記ラ
ンドから離れるに従つて深くなるように形成されている
ことを特徴とする接続部材の橋絡防止装置。
1. On a substrate, a first gear gap is provided between the substrates.
Made of conductive material arranged in a row,
Multiple lands to which connection members are attached, Arrangement of the land adjacent to the land and on the board.
Connecting member guide hand formed in a direction substantially orthogonal to the row direction
With steps, Second gear cup between the connecting member guiding means and the land
Is narrower than the first gearCage, The connecting member guiding means has a concave part of the surface of the substrate.
The guide groove is formed on the bottom of the guide groove.
Is formed so that it becomes deeper as it moves away from the
A bridging prevention device for a connecting member.
【請求項2】上記ランドと上記誘導溝とは、接続に余分
な上記接続部材を誘導する誘導材料で連結されている
とを特徴とする請求項1に記載の接続部材の橋絡防止装
置。
2. The land and the guide groove have an extra connection.
This it is attached in inducing material that induces a said connecting member
The bridging prevention device for a connecting member according to claim 1, wherein:
【請求項3】上記底面には、接続に余分な上記接続部材
を誘導する誘導材料が配されている ことを特徴とする請
求項1に記載の接続部材の橋絡防止装置。
3. The connection member on the bottom surface is redundant for connection.
A contract characterized by being provided with an induction material for inducing
The bridging prevention device for a connecting member according to claim 1 .
【請求項4】上記接続部材誘導手段は、上記基板上に、
接続に余分な上記接続部材を誘導する誘導材料で形成さ
れた誘導ランドを有する ことを特徴とする請求項1に記
載の接続部材の橋絡防止装置。
4. The connecting member guiding means is provided on the substrate,
Made of inductive material to guide the extra above connecting member into the connection
2. The method according to claim 1, further comprising a guided land.
Bridging prevention device for connecting members.
【請求項5】基板上に、相互に第1のギヤツプを介して
一列に配列された導電性材料でなり、それぞれ導電性の
接続部材が付着される複数のランドと、 上記基板上に、上記ランドと隣合いかつ上記ランドの配
列方向とほぼ直交する方向に形成された接続部材誘導手
段と を具え、 上記接続部材誘導手段と上記ランドとの第2のギヤツプ
が上記第1のギヤツプに比して狭く設定されており、 上記接続部材誘導手段は、上記基板の表面の一部が凹状
に形成された誘導溝でなり、当該誘導溝の底面が上記ラ
ンドから離れるに従つて深くなるように形成されている
ことを特徴とする接続部材の橋絡防止装置を有する半導
体集積回路。
5.On the board, mutually via the first gear
Made of conductive material arranged in a row,
A plurality of lands to which the connecting members are attached, Arrangement of the land adjacent to the land and on the board.
Connecting member guide hand formed in a direction substantially orthogonal to the row direction
Step With Second gear cup between the connecting member guiding means and the land
Is set narrower than the first gear, The connecting member guiding means has a concave part of the surface of the substrate.
The guide groove is formed on the bottom of the guide groove.
Is formed so that it becomes deeper as it moves away from the
A semi-conductor having a bridging prevention device for a connecting member, characterized in that
Body integrated circuit.
【請求項6】基板上に、相互に第1のギヤツプを介して
一列に配列された導電性材料でなり、それぞれ導電性の
接続部材が付着される複数のランドと、 上記基板上に、上記ランドと隣合いかつ上記ランドの配
列方向とほぼ直交する方向に形成された接続部材誘導手
段と を具え、 上記接続部材誘導手段と上記ランドとの第2のギヤツプ
が上記第1のギヤツプに比して狭く設定されており、 上記接続部材誘導手段は、上記基板の表面の一部が凹状
に形成された誘導溝でなり、当該誘導溝の底面が上記ラ
ンドから離れるに従つて深くなるように形成されている
ことを特徴とする接続部材の橋絡防止装置を有する実装
基板。
6.On the board, mutually via the first gear
Made of conductive material arranged in a row,
A plurality of lands to which the connecting members are attached, Arrangement of the land adjacent to the land and on the board.
Connecting member guide hand formed in a direction substantially orthogonal to the row direction
Step With Second gear cup between the connecting member guiding means and the land
Is set narrower than the first gear, The connecting member guiding means has a concave part of the surface of the substrate.
The guide groove is formed on the bottom of the guide groove.
Is formed so that it becomes deeper as it moves away from the
Mounting having a bridging prevention device for a connecting member characterized by
substrate.
JP05326494A 1994-02-24 1994-02-24 Device for preventing bridging of connection member, semiconductor integrated circuit having the same, and mounting substrate Expired - Fee Related JP3410199B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP05326494A JP3410199B2 (en) 1994-02-24 1994-02-24 Device for preventing bridging of connection member, semiconductor integrated circuit having the same, and mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05326494A JP3410199B2 (en) 1994-02-24 1994-02-24 Device for preventing bridging of connection member, semiconductor integrated circuit having the same, and mounting substrate

Publications (2)

Publication Number Publication Date
JPH07235761A JPH07235761A (en) 1995-09-05
JP3410199B2 true JP3410199B2 (en) 2003-05-26

Family

ID=12937915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP05326494A Expired - Fee Related JP3410199B2 (en) 1994-02-24 1994-02-24 Device for preventing bridging of connection member, semiconductor integrated circuit having the same, and mounting substrate

Country Status (1)

Country Link
JP (1) JP3410199B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011160231A (en) * 2010-02-01 2011-08-18 Mitsubishi Electric Corp High frequency transmission line

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4753539B2 (en) * 2003-08-27 2011-08-24 京セラ株式会社 Electronic component mounting substrate and electronic device using the same
JP4211986B2 (en) * 2004-12-02 2009-01-21 パナソニック株式会社 Printed circuit board and printed circuit board design method, IC package connection terminal design method, and IC package connection method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011160231A (en) * 2010-02-01 2011-08-18 Mitsubishi Electric Corp High frequency transmission line

Also Published As

Publication number Publication date
JPH07235761A (en) 1995-09-05

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