JP2013183059A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which, even if a junction bump is raised by stable jointing, insufficient junction does not occur, an internal stress caused by thermal stress is reduced, and a damage on a passivation film is eliminated.SOLUTION: On a gold-plated bonding land 21 which is an upper layer of a peripheral type interposer 17, a single stage of gold bump 24 is formed, and a resist 23 is formed on a dummy land 22 disposed at a central portion. In a semiconductor element 10, a single stage of gold bump 24 is respectively formed on a dummy bonding pad 25 and a bonding pad 11 of which an upper layer is gold-plated. A flip chip jointing of a multi-stage bump is performed by the bumps 24. A GGI method using heat, ultrasonic wave, or pressure is applied to the jointing.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for reducing the internal stress in an apparatus for flip-chip bonding an interposer and a semiconductor element.

  Communication equipment, video equipment, audio equipment, etc. have become smaller and thinner due to mobile and wearable technologies based on ubiquitous society, and semiconductor devices used in these equipment are also becoming smaller and thinner. The demand is further increased, and a semiconductor device such as a CSP (Chip Scale Package) is manufactured in response to such a demand.

  The CSP interposer uses materials such as metal lead frames, ceramics, and organic materials, and can be properly used depending on the application in consideration of factors such as heat conduction, wiring routing, thickness, and cost. A copper lead frame is used in the direction of cost reduction and high heat dissipation, and a ceramic or organic (plastic) material is used in the direction of downsizing. The reason why this organic material interposer is used is that there is no need for a mold for VIA (hole) processing, that it can respond to the demand for a small variety of products, and that organic processing technology has been improved to enable fine processing equivalent to ceramics. And raw materials are cheap.

  The interposer is generally used in a collective substrate in which a plurality of semiconductor devices are arranged in a matrix, and is applied as one that exhibits excellent productivity. In the metallization by electroless plating in this interposer, for example, a base wiring such as copper (Cu), tungsten (W), etc. is subjected to nickel plating of about 3 to 7 μm by reduction plating, and then on the reduction plating or displacement plating. This is done by applying gold plating. The reason why the above nickel plating is used as the intermediate layer is that it can be used as a diffusion preventing material for the base wiring and the gold plating because of its high density, relatively few pinholes, and a high melting point. .

Also, the bonding land of the interposer is caused by the fact that gold plating as the final plating has relatively many pinholes, resulting in an inhibitory factor such as Ni (OH) ₂ from the diffusion of nickel according to the stage heating temperature and time. As a result, there is an inconvenience that the bonding force is remarkably reduced. In order to reduce the influence of this inhibitory factor, it is most effective to lower the stage heating temperature. However, lowering the stage heating temperature, which is used as part of the bonding energy, lowers the bonding strength and increases the bonding quality. Has a limit to 100 to 150 ° C.

  As a method for connecting the interposer and the semiconductor element as described above, there are a wire bonding method for connecting with metal thin wires, a flip chip bonding (bump bonding) method for connecting with metal bumps, and the like. In this flip chip bonding, for example, bumps are formed on electrodes such as gold (Au) and aluminum (Al) on the surface of a semiconductor element by using a plating method or a wire bonding method, and the bumps are formed on the bonding land of the interposer. Bonding is performed by performing bonding while performing image or machine alignment.

  Further, in the flip chip method, depending on the connection material and the connection energy, a method of melting solder by heat, a method of using an anisotropic conductive material as an intermediate medium, and bonding between bumps and bonding lands by a thermocompression bonding method, There are many methods such as a method of bonding metal bumps by thermocompression bonding, a method of bonding by ultrasonic waves and heat, and a method of combining the above connection methods. Among them, there is a GGI (GGI: Gold to Gold Interconnection) method in which a gold bump is used and a gold bonding land (electrode) is directly connected using ultrasonic waves, heat and pressure, and this GGI method is It is actively used for many advantages such as no brittle alloy layer growth even in harsh environments such as high temperatures, low joint resistance, short joining time, and no additional steps such as cleaning steps. Yes. In particular, in applications that handle high-frequency signals in the gigahertz (GHz) band such as communication parts, it is a necessary condition to employ a bonding method with low resistance.

  Next, an outline of a general CSP assembly process using the above GGI method will be described. First, the semiconductor elements to be mounted are gold bumps on the electrodes using an SBB (Stud Bump Bonding) method or the like that applies plating or wire bonding in the state of an assembled substrate (wafer) before being singulated. Is formed. The collective substrate on which the gold bumps are formed is divided into individual semiconductor elements by dicing, and each semiconductor element is taken out by another facility and held by suction with a collet. When the collet is inverted (flip), the semiconductor element is delivered to the bonding tool, and the semiconductor element is held in a state of being adsorbed to the bonding tool, and finally heated at a stage of about 80 to 200 ° C. Bumps are aligned on the gold bonding lands that are plating by image alignment, and then bump bonding is performed by applying ultrasonic waves and a load to the semiconductor element.

  Immediately before the bump bonding, the metal interface after gold plating of the bonding land of the interposer is high and easily contaminated by bonding inhibiting factors. Therefore, bonding of sulfur compounds adsorbed on the bonding land by plasma treatment with Ar or the like In some cases, the bonding strength is stabilized by removing the contaminants that become an inhibitory factor and performing the bonding after the reactivation.

  Applying large ultrasonic energy by the GGI method is effective for destroying the inhibitor layer, but the semiconductor element mounted on a recent thin semiconductor device tends to be as thin as 80 to 150 μm. Therefore, it is difficult to apply excessive ultrasonic energy accompanied by deformation in the Z-axis direction.

  By the way, in the flip chip bonding described above, there is a problem in that stress is applied to the periphery of the bump due to a difference in linear expansion coefficient between the semiconductor element and the interposer, and the bump is broken or bridged. That is, the linear thermal expansion coefficient (CTE: Coefficient Thermal Expansion) of the semiconductor element is, for example, about 2.4 ppm for silicon (Si), about 7 ppm for gallium arsenide (GaAs), and about 4 ppm for silicon carbide (SiC). Whereas it is about 5 ppm, the CTE of the interposer is relatively large, about 15 to 18 ppm for the copper lead frame and about 10 to 20 ppm for the organic substrate. The ceramic that has been actively used in the past is about 2 to 11 ppm, which is close to the CTE of the semiconductor element, and the stress applied to the periphery of the bump after bonding is small, but a copper lead frame or an organic substrate is often selected as an interposer. In recent semiconductor devices, the stress inherent in the periphery of the bump after bonding is large, and the proof stress against an environmental load such as a temperature cycle is reduced, so that the bump is likely to break. The gold CTE used as a bump material during GGI bonding is about 15 ppm, which is the same as that of a copper lead frame and an organic substrate, but the elastic modulus of gold is as small as 1/2 to 1/3 of the stress. Has little effect on

For this reason, conventionally, as disclosed in Patent Documents 1 and 2 below, a method of separating the distance between a semiconductor element having a large CTE difference and an interposer by providing multiple bumps has been proposed.
FIG. 7 shows the configuration of the semiconductor device of Patent Document 1. In FIG. 7, three-level gold bumps 5 are formed on either the electrode 2 of the semiconductor element 1 or the electrode 4 of the circuit board 3. The semiconductor element 1 is bonded to the circuit board 3 by the gold bumps 5 by applying heat and pressure. According to this, the space | interval of the semiconductor element 1 after mounting and the circuit board 3 can be enlarged, and the stress concerning a bump periphery can be reduced.

JP 2003-273148 A JP 2006-108408 A Japanese Patent Laid-Open No. 5-218135

  However, as shown in FIG. 7, if the distance (interval) between the semiconductor element 1 and the circuit board 3 is increased by multi-stage bumps, the stress is reduced. For example, in the case of the GGI method using gold multi-stage bumps, Since the elastic modulus is low, ultrasonic vibrations are not transmitted at bump heights of 50 μm or more, reliability is significantly reduced due to insufficient bonding, and stable flip chip bonding cannot be performed except for one-step bumps. It was. In bump bonding, ultrasonic vibration is given by the bonding tool, but the displacement amount of this bonding tool is likely to vary in characteristics due to the relationship with the transducer that oscillates ultrasonic vibration, and excessive ultrasonic vibration is generated. If given, inclination (attitude change) occurs in the planar direction or Z direction of the semiconductor element, and the bumps are not joined at a specific location, making it difficult to stabilize the quality. In addition, if the gold bumps are uniquely increased, the bump diameter must be increased in conjunction with it, so the pad size and pad pitch tend to be reduced, making it difficult to cope with recent mounting designs. Yes.

  In addition, as a method for forming multi-stage bumps, for example, it is common to form multi-stage bumps on the semiconductor element side in advance as in, for example, Patent Document 2, but the periphery of a multi-layered semiconductor element bonding pad is particularly vulnerable to stress. Since the semiconductor element is destroyed by accumulating mechanical damage due to the bonding load when stacking the bumps one by one, it is preferable not to apply the bonding load to the bonding pad of the semiconductor element many times. It is preferable to form multi-stage bumps.

  Furthermore, in the GGI method, since gold bumps are formed on all the bonding pads of a plurality of semiconductor elements and then flip chip bonding is performed, the flatness of the gold bumps and the parallelism between the semiconductor elements and the interposer are extremely important. However, only a variation of about 3 to 5 μm is allowed, and even within that range, there is a problem that the bonding strength varies for each bump due to a slight difference in flatness and parallelism.

  Conventionally, as shown in Patent Document 3, a hardened layer of photoresist is provided at the mounting position of the IC chip on the substrate, the height of the IC chip on the substrate is regulated, and the side of the solder joint is There are some that prevent the spread to prevent the occurrence of bridging, secure the height and improve the mounting reliability.

  FIG. 8 shows the structure of a peripheral type (type in which electrodes are arranged in the periphery) semiconductor device that performs flip-chip bonding. FIG. 9 shows the application of Patent Document 3 to this peripheral type semiconductor device. Possible configurations are shown. FIG. 8A shows the surface of the interposer 7. On the surface of the interposer 7, the bonding lands (electrodes) 9 are connected to a plurality of connection vias (holes) 8 in the periphery of the interposer 7, and the positions of the semiconductor elements are arranged. 8B shows the back surface of the semiconductor element 10. On the back surface of the semiconductor element 10, a plurality of bonding pads (electrodes) 11 are formed in the periphery. Then, the bonding pad 11 of the semiconductor element 10 and the bonding land 9 of the interposer 7 are bonded together by bumps as shown in FIG.

  In such a semiconductor device, as shown in FIG. 9A, a resist (cured layer) 14 is provided on the wiring 13 at the center of the interposer 7, and the bonding pad 11 of the semiconductor element 10 is soldered. Bumps (gold bumps in the GGI method) 15 are formed and joined by solder bumps 15 in a state as shown in FIG.

  As described above, in the peripheral type semiconductor device in which the electrodes are arranged in the periphery, the bump junction point between the bonding ground 9 of the interposer 7 and the bonding pad 11 of the semiconductor element 10 is closer to the center of the package (semiconductor device) than the connection VIA8. (Fan Out) and has the advantage that the electrode can be easily routed. In other words, in the array type semiconductor device that is not a peripheral type, the connection VIA8 is disposed closer to the center of the package than the bump junction, and in order to route from the bump junction to the electrode at the center of the package, the connection VIA8 is connected. However, in the peripheral type, there is an advantage that a sufficiently wide space is secured as a bonding land because it is not necessary to pass the wiring between the connection VIAs 8. In particular, in the GGI bonding using the organic material as the interposer 7, the base material strength is soft, so that the bonding land 9 needs to be set to a sufficient size, and the peripheral type having a sufficient space is more advantageous. This is also consistent with the conventional manufacturing method of aligning and bonding a semiconductor element with bumps formed in advance to the bonding land, and the bump mounting position of the bonding land is determined after alignment mounting. The position does not need to be uniquely determined by the bonding land.

  However, as shown in FIG. 9, when the resist 14 is used, if the solder bump (gold bump in the GGI method) is excessively deformed, the resist 14 and the semiconductor element 10 come into contact with each other, such as SiN on the semiconductor element. The passivation film is damaged, and problems such as deterioration of reliability such as moisture resistance occur.

  The present invention has been made in view of the above-described problems, and its purpose is to achieve stable bonding, even when the bonding bump between the semiconductor element and the interposer is increased, so that insufficient bonding does not occur, and internal stress due to thermal stress occurs. It is another object of the present invention to provide a method of manufacturing a semiconductor device in which the passivation film is not damaged by contact between a resist and a semiconductor element and reliability such as moisture resistance is not lowered.

In order to achieve the above object, the invention according to claim 1 is directed to a semiconductor device manufacturing method including a bump bonding step in which a semiconductor element is bonded to the interposer by a bump (flip chip bonding). A dummy land is formed separately from the land, a resist is formed on the dummy land, a dummy bump is formed on the semiconductor element via a bonding pad at a position facing the resist of the interposer, and the bump bonding step Then, the bonding pad of the semiconductor element is bonded to the bonding land of the interposer by a multi-stage bump while the dummy bump of the semiconductor element is brought into contact with the resist on the dummy land of the interposer.
According to a second aspect of the present invention, one or more bumps are formed on a predetermined bonding land of the interposer, and one bump is formed on the semiconductor element to be connected to the bumps on the interposer side. Multi-step bump bonding is performed using the bumps on the semiconductor element and the bumps on the semiconductor element side.
The invention according to claim 3 is characterized in that the bump diameter on the interposer side is set larger than the bump diameter on the semiconductor element side.
The invention of claim 4 is characterized in that an alignment mark (positioning mark) for specifying a mounting position of the semiconductor element is displayed on the interposer.

  According to the configuration of the present invention, the joining of the multi-stage bumps is stably performed by the resist of the interposer and the dummy bumps of the semiconductor element.

  According to the method for manufacturing a semiconductor device of the present invention, even when the bonding bump between the semiconductor element and the interposer is increased, there is an effect that insufficient bonding occurs and internal stress due to thermal stress can be reduced. That is, under any bonding condition, the height of the bump after bonding is obtained by adding the thickness at the time of bonding the dummy bump (deformation thickness: about 5 μm) to the resist thickness (about 5 to 30 μm). Since the semiconductor element and the interposer having a large difference can be sufficiently separated from each other, the stress applied to the periphery of the bump is reduced, the stress caused by the thermal stress such as the temperature cycle can be relieved, and the reliability can be improved.

Moreover, since the bonding is performed stably, there is no inclination in the plane direction or the Z direction of the semiconductor element, and there is no shortage of bump bonding at a specific location, so that the quality can be stabilized, as in the past. In addition, it is not necessary to increase the bump diameter in order to cope with the stress, which is advantageous for dealing with a semiconductor element having a narrow pad size and a narrow pad pitch.
Further, by providing the dummy bumps, the resist does not come into contact with the semiconductor element, and the passivation film of the semiconductor element is damaged by the resist and reliability such as moisture resistance is not lowered.

According to the invention of claim 3, since the bump with the small diameter on the semiconductor element side is brought into contact with and bonded to the bump with the large diameter on the interposer side, the bonding of the bump is stable even when the mounting position is not high in accuracy. This is advantageous in that the mounting position accuracy can be relaxed. Further, since the stress at the peripheral electrode portion caused by the CTE difference between the semiconductor element and the interposer becomes the largest at the joint interface between the interposer and the gold bump, it is possible to avoid the joint failure that tends to occur at this interface.
According to the invention of claim 4, since the semiconductor element is accurately grasped based on the alignment mark, it is possible to easily mount the semiconductor element while performing accurate bump bonding.

1A and 1B show a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a cross-sectional view before bump bonding, and FIG. 1B is a cross-sectional view after bump bonding and resin molding. It is a figure which shows the mode of bump joining in the manufacturing method of the semiconductor device of an Example. 1A and 1B show a configuration of an interposer and a semiconductor element used in a method for manufacturing a semiconductor device according to an embodiment. FIG. 1A is a front view of the interposer, FIG. 2B is a back view of the interposer, and FIG. It is. The other structure of the interposer used for the manufacturing method of the semiconductor device of an Example and a semiconductor element is shown, a figure (A) is a surface figure of an interposer, and a figure (B) is a back view of a semiconductor element. The alignment for mounting the semiconductor element of the embodiment is shown, FIG. (A) is a surface view of the interposer, and FIG. (B) is a view when the semiconductor element is mounted on the interposer. The stress analysis result at the time of bump bonding is shown. FIG. (A) is a view when the bump height is 30 μm, and FIG. (B) is a view when the bump height is 15 μm. It is a figure which shows an example of the conventional multistage bump joining. The structure of a conventional peripheral type semiconductor device is shown, in which FIG. (A) is a front view of an interposer and FIG. (B) is a back view of a semiconductor element. FIGS. 8A and 8B show an example of a manufacturing method applicable to the peripheral type semiconductor device of FIG. 8. FIG. 9A is a cross-sectional view before bump bonding, and FIG.

  1 to 4 show the configuration of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the embodiment, the interposer 17 is formed of a substrate (core material) made of an organic material (synthetic resin material or the like). The semiconductor element 10 is flip-chip bonded. The embodiment has a peripheral type configuration in which electrodes are arranged in the periphery, and a GGI (Gold to Gold Interconnection) method in which gold bumps are used and bonded by heat and ultrasonic waves or pressure is applied.

  As shown in FIGS. 1 and 3, a plurality of connection VIAs (holes) 8 are provided around the interposer 17, and wiring and a back electrode 19 are formed through the connection VIA8. As shown in (A), a circular bonding land (electrode land whose upper layer is gold plating) 21 is formed at the bump bonding position. The bonding land 21 has a circular shape, a square shape, a rectangular shape, or the like centered on a bump center (bonding point) in order to clarify each bonding point. Simultaneously with the formation of the bonding land 21, a rectangular dummy land 22 is formed at the center of the semiconductor element mounting position 50 of the interposer 17.

  Next, a rectangular resist 23 is coated and formed on the dummy land 22, and this resist 23 is, for example, a hardened layer of photoresist, and has a thickness of about 5 to 30 μm by a printing method, a roll coater method or the like. Formed in thickness. In the interposer 17, a single gold (Au) bump 24 is formed on the bonding land 21 by a wire bonder or the like. When three or more bumps are bonded, two or more bumps are formed on the interposer 17 side.

  On the other hand, as shown in FIG. 3C, the semiconductor element 10 is provided with a plurality of bonding pads (electrode pads) 11 at the peripheral position and a dummy bonding pad 25 having the same configuration at the central position. Is formed. Then, one gold bump 24 is formed on the bonding pad 11 and one gold dummy bump 26 is formed on the dummy bonding pad 25 by a wire bonder or the like (on the semiconductor element 10 side). It is preferable that the bump has only one stage).

  As a method for producing the gold bump 24 on the interposer 17, there is a formation method using a stud bump bonder or a wire bonder. In particular, the latter formation method can be carried out relatively easily. That is, when using a wire bonder, by arranging the interposer 17 on the bonding stage and forming a spherical gold ball from the electric torch method on the tip of a gold wire of about 15-20 μm comprising 99.99%, Ball bonding is performed at a predetermined position of the interposer 17. For the formation of the first stage ball bonding, it is better to use ultrasonic waves in combination, and the formation after the second stage can be performed by thermocompression excluding ultrasonic waves as described in Patent Document 2 above. is there. This is probably because gold bumps using pure gold can be joined relatively easily. Further, the gold bump and the gold wire can be peeled by a method (pull cut method) in which a part of the gold wire is thinly crushed and then the gold wire is torn off. On the other hand, as a method for producing the gold bump 24 and the dummy bump 26 on the semiconductor element 10 side, a stud bump bonder is used. Note that the gold bumps 24 and the dummy bumps 26 on the semiconductor element 10 side are single-step bumps to avoid problems such as damage.

  FIG. 4 shows another example of bonding lands formed on the interposer 17. In this example, a square bonding land 31 is formed at a bump bonding position. The bonding land 31 also serves to clarify the center of each bonding by forming a square centered on the bump center. The bonding land 31 may be another polygon such as a rectangle or a hexagon. That is, by making the bonding land 31 circular, square, etc., and making the center position the same as the desired position for bump formation, the bump position formed on the interposer wiring is uniquely determined. It is possible to form a stable multi-stage bump without causing the bump 24 and the bump 24 on the semiconductor element 10 side to shift and damage the passivation film on the semiconductor element.

Thereafter, the semiconductor element 10 is disposed at a predetermined position of the interposer 17 and bump bonding is performed.
In the embodiment, the alignment mark Ma and the post-mounting position confirmation mark Mb in FIG. 5 are formed so that the bonding position by the bump 24 and the mounting position of the semiconductor element 10 can be easily positioned and confirmed. In FIG. 5A, alignment marks Ma are triangular positioning marks provided at the four corners of the outer (square) line of the semiconductor element mounting position 50, and the post-mounting position confirmation marks Mb are on outer lines other than the four corners ( It is a circular confirmation mark with the center point (so as to cross the line).

  That is, the bonding land 21 on the interposer 17 is arranged at a position where each position of the bonding pad 11 on the semiconductor element 10 coincides on the mirror surface with the center of the dummy bonding pad 25 as the origin using, for example, CAD data. . Therefore, when the horizontal size of the semiconductor element 10 is X and the vertical size is Y, the alignment mark Ma has the center of the dummy bonding pad 22 (the center of the semiconductor element mounting position) as the origin, and (X / 2, Y / 2), (-X / 2, Y / 2), (X / 2, -Y / 2), (-X / 2, -Y / 2) It is formed so that vertices having an internal angle of 90 degrees coincide. By measuring the coordinates of at least two of these four points, the accuracy of each bonding point formed on the interposer 17 can be confirmed. If an image device is used, the interposer 17 with high accuracy can be obtained by automatic inspection or the like. Can be supplied.

  Further, the positional accuracy of the bumps 24 on the interposer 17 is particularly important. When the gold bumps 24 are formed on the bonding lands 21, for example, at least the alignment marks Ma shown in FIG. By detecting two points, for example, (−X / 2, Y / 2), (X / 2, −Y / 2) in the coordinate order, the bump 24 is accurately bonded on the bonding land 21 according to the input coordinates. The

  In the bump bonding, the semiconductor element 10 is positioned face down to the interposer 17 side, and also in this case, the flip chip bonder uses the alignment mark Ma. For example, (−X / 2, Y / 2) , (X / 2, −Y / 2) in order of coordinates, the semiconductor element 10 and the bumps 24 of the interposer 17 are joined to each other.

  FIGS. 2A and 2B show the state of bump bonding. In this bump bonding, ultrasonic vibration, heat, and pressure are applied, but the bump bonding is formed on the semiconductor element 10 and the interposer 17. The diameter of the bump 24 is about 40 to 90 μm (φ), and the height of the bump 24 is about 5 to 50 μm. The energy given at the time of flip chip bonding is converted into the energy of bump bonding and the energy of deformation of the bump. As a result, the diameter of each bump 24 increases and its height becomes about 2/3.

  Further, in the embodiment, as shown in FIG. 2, the diameter of the bump 24 on the interposer 17 side is set larger than the diameter of the bump 24 on the semiconductor element 10 side. According to this, since the bump 24 having a small diameter of the semiconductor element 10 is brought into contact with and bonded to the bump 24 having a large diameter of the interposer 17, the bonding of the bump is stable even when the accuracy of the mounting position is not so high. Can be done.

  In the embodiment, after the bump bonding, it can be confirmed by the post-mounting position confirmation mark Mb that no positional deviation or angular deviation has occurred in the semiconductor element 10. For example, when the diameter of the circular post-mounting position confirmation mark Mb is 50 μm, the mounting position can be confirmed by visually observing the semicircle. When the diameter of the bumps 24 on the interposer 17 side is 100 μm and the diameter of the bumps 24 on the semiconductor element 10 side is 50 μm, the joining position does not deviate, and quality can be estimated by means such as initial confirmation. .

  According to the embodiment, since the bump bonding is performed with the dummy bumps 26 in contact with the resist 23, the height at the time of bonding of the bumps 24 is the thickness of the resist (about 5 to 30 μm) and the dummy bumps 26. It becomes more than the sum of the limit deformation thickness (about 5 μm). Therefore, even if excessive bonding energy is mistakenly applied, the bump height is set at the above-described height, so that stable bonding can be achieved and reliability can be ensured. That is, unlike the prior art, the multi-stage bumps do not spread sideways or bridge.

  In addition, the bump bonding of the embodiment is less affected by the underlayer and environmental contamination due to the high density of the bumps 24, relatively few pinholes, and a sufficient volume. It is possible to sufficiently bond with a small bonding energy. For example, a sufficient bonding may be obtained only by applying a load of several hundred gf. As a result, mechanical destruction around the fragile bonding pad of the semiconductor element can be prevented, and damage to the thin semiconductor element can also be prevented.

FIG. 6 shows a simulator analysis result of the package internal stress when the assembly temperature is changed from 150 ° C. to the environmental temperature −65 ° C. assuming that an environmental load is applied after the assembly is completed. 6A is a view when the height of the gold bump 24 (90 μmφ) is 30 μm (two steps), and FIG. 6B is the height of the gold bump 24 (90 μmφ) is 15 μm (one step). ). In the one-step bump of FIG. 6 (B), the region of 3.2 × 10 ⁵ mN / mm ^{2 and} the region of 4 × 10 ⁵ mN / mm ² exist, whereas the two-step bump of FIG. 6 (A). Then, it can be seen that only low stress is generated up to a region of 2.5 × 10 ⁵ mN / mm ² . In addition, when the bumps are formed in two stages, the stress between the bonding land and the bump is estimated to be reduced to about 25%. If the bumps are further formed in multiple stages, this stress is further reduced.

  According to the embodiment, by forming multi-stage bumps, the distance between the semiconductor element and the interposer having a large CTE difference can be sufficiently separated, and the internal stress due to thermal stress is reduced without the lack of bonding. It is not necessary to increase the diameter, and it is possible to cope with a semiconductor element having a narrow pad size and a narrow pad pitch. Further, the resist does not contact the semiconductor element and damage the passivation film, and reliability such as moisture resistance is maintained.

  In the embodiment, as shown in FIG. 1B, the entire semiconductor device after bump bonding is sealed with resin 28 by overcoat molding (molding process). That is, a liquid resin (epoxy resin) 28 is filled (underfilled) into the gap between the semiconductor element 10 and the interposer 17 using a capillary phenomenon to improve the mechanical strength of the bonding, and then molded or molded. An overcoat mold with resin 28 is applied. In the case of the conventional one-step bump, since the gap between the semiconductor element and the interposer is usually 30 μm or less, when the filler diameter of the epoxy resin used as the sealing material is larger than the gap, the gap may enter the gap. However, in this embodiment, after the liquid epoxy resin is filled around the bumps by a capillary phenomenon, the overcoat molding is performed to eliminate the influence of the mold characteristics. The individual semiconductor devices are manufactured by dividing the interposer 17 on which a plurality of semiconductor devices sealed with resin are mounted by a method such as dicing.

  Prior to the formation of the bumps 24 of the above-described embodiment, the bonding point is cleaned by irradiating plasma such as Ar in the wafer unit in the case of the semiconductor element 10 and in the semiconductor element aggregate substrate unit in the case of the interposer 17. . The bonding land 21 on the interposer does not cause bonding damage even when a large load is applied during bump formation. Therefore, the bonding inhibition layer on the surface of the bonding land can be efficiently destroyed, and stable bonding can be easily performed. In addition, the bonding land 21 in the case where an organic substrate is used as the interposer 17 has a low strength of the substrate. Therefore, in the conventional flip chip bonding, it is necessary to secure a sufficient area. Since bonding energy can be applied, the bonding land 21 can be set as small as the bump collapse diameter. This improves the degree of freedom of wiring routing on the interposer, reduces the gold plating area with low adhesion strength, and leads to prevention of peeling of the semiconductor device.

  In general, in multi-stage bump bonding, multi-stage bumps are formed on the semiconductor element 10 side and bonded, but the periphery of the bonding pad of the multi-layered semiconductor element 10 is vulnerable to stress, and the bumps are stacked one by one. Since the mechanical damage due to the bonding load is accumulated, the semiconductor element 10 is destroyed. Therefore, it is preferable not to apply the bonding load to the bonding pad of the semiconductor element 10 a plurality of times. In the embodiment, even in the case of multi-stage bumps, by forming the bump 24 on the interposer 17 side, the number of bumps 24 formed on the semiconductor element 10 becomes one. Therefore, the bonding load applied to the bonding pad 11 of the semiconductor element 10 Is limited to two times at the time of bump formation and at the time of flip chip bonding, and therefore has the advantage that there is no concern about damage.

  In the above-described embodiment, one or more bumps are formed on the bonding land of the interposer 17 and one bump is formed on the semiconductor element 10, but this makes it possible to form gold bumps that are essential in the GGI method. Management of flatness and parallelism between the semiconductor element 10 to be bonded and the interposer (collective substrate) 17 can be relaxed. For example, a standard that allowed only a variation of about 3 to 5 μm for a single bump is about 6 to 10 μm, which is twice that for a two-step bump, and a variation of about 9 to 15 μm, which is three times that for a three-step bump. Will come to be.

Further, when the bump 24 is previously formed on the wiring by the GGI method, the condition range for the ultrasonic energy at the time of bump formation is wide, and even if excessive power is applied, there is no fear of destruction of the semiconductor element. An inhibitor layer such as Ni (OH) ₂ resulting from the diffusion of nickel according to the heating temperature and time can be easily destroyed effectively, and the stage temperature can be reduced to 100 ° C. or lower, for example. It is also possible.

  In addition, the gold bump 24 used in the GGI method has fewer pinholes than gold plating, and in the case of a two-step bump, the thickness is about 10 to 100 μm, and the plating thickness is about 0.03 to 0.5 μm. By applying FCB bonding on the bump, it is extremely thick, so there is no influence of inhibiting factors arising from nickel diffusion under the gold plating layer. Also, the influence of contamination in the environmental atmosphere such as the formation of sulfide is also applied to gold plating. Smaller than that. Therefore, the ultrasonic energy at the time of flip-chip bonding can be set low, and the FCB bonding of a thin semiconductor element of 80 to 150 μm with a low breaking strength mounted on a recent semiconductor device is easy and transient. Since the ultrasonic energy fluctuation is small, the posture of the semiconductor element is hardly changed.

  In the above embodiment, when the flip chip bonding is performed, the bumps 24 on the interposer 17 side and the gold bumps 24 on the semiconductor element 10 side are collided at high speed, and the bonding phenomenon is instantaneously caused by the impact. In this case, the applied energy of ultrasonic waves can be reduced.

1,10 ... Semiconductor element 5,15,24 ... Bump,
7, 17 ... Interposer, 8 ... Connection VIA,
9, 21, 31 ... Bonding land,
14, 23 ... resist, 22 ... dummy land,
25 ... dummy bonding pad, 26 ... dummy bump,
28 ... mold resin, 50 ... semiconductor element mounting position,
Ma ... alignment mark,
Mb: A mark for confirming the position after mounting.

Claims (4)

In a manufacturing method of a semiconductor device having a bump bonding step of bonding a semiconductor element on an interposer by a bump,
A dummy land is formed on the interposer separately from the predetermined bonding land, and a resist is formed on the dummy land.
In the semiconductor element, a dummy bump is formed through a bonding pad at a position facing the resist of the interposer,
In the bump bonding step, the bonding pad of the semiconductor element is bonded to the bonding land of the interposer by a multi-stage bump while contacting the dummy bump of the semiconductor element to the resist on the dummy land of the interposer. A method for manufacturing a semiconductor device. Form one or more bumps on a predetermined bonding land of the interposer,
2. The semiconductor element according to claim 1, wherein a bump of one stage connected to the bump on the interposer side is formed on the semiconductor element, and multi-stage bump bonding is performed by the bump on the interposer side and the bump on the semiconductor element side. A method for manufacturing a semiconductor device.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the bump diameter on the interposer side is set larger than the bump diameter on the semiconductor element side.   4. The method of manufacturing a semiconductor device according to claim 1, wherein an alignment mark for specifying a mounting position of the semiconductor element is displayed on the interposer.

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