TW201921626A - Wiring substrate, component mounting wiring substrate, semiconductor device, and method for manufacturing wiring substrate - Google Patents

Abstract

According to an embodiment of the present disclosure, provided is a wiring substrate that includes: a substrate; an insulating layer on the substrate; a height adjustment unit provided within the insulating layer; a first electrically conductive part provided on the insulating layer; and a second electrically conductive part adjacent to the electrically conductive part, provided on the insulating layer and the height adjustment unit, wherein the height from the substrate top surface to the top surface of the first electrically conductive part and the height from the top surface of the substrate to the top surface of the second electrically conductive part approximately match. In the wiring substrate, the height adjustment unit can also be a dummy via part that is adjacent to a via part placed on a lower part wiring, and is provided within the insulating layer. Also, in the wiring substrate, the first electrically conductive part and the second electrically conductive part configure an Nth wiring layer among multi-layer wiring layers made by laminating first to Nth (where N is an integer of 2 or more) wiring layers in this order, and the height adjustment unit, at the lower part in the lamination direction of the second electrically conductive part, may be provided at least on a portion of the electrically conductive parts configuring the respective first to N-1th wiring layers.

Description

Wiring substrate, component assembly line substrate, semiconductor device, and manufacturing method of wiring substrate

The present invention relates to a wiring substrate, a semiconductor device, and a method for manufacturing a wiring substrate.

High-density mounting technology (high-density mounting technology) for mounting semiconductor elements including integrated circuits or high-frequency elements including passive elements on a substrate is widely used. In the high-density packaging technology, a wire bonding method using small leads and a flip chip method using a grid-shaped connection terminal to connect without using leads are adopted. Patent Document 1 discloses a high-density mounting technique using a flip chip method. Patent Document 2 discloses a structure of a multilayer wiring board used in high-density packaging technology. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2004-055660 [Patent Document 2] Japanese Patent Laid-Open No. 2014-179518

[Problems to be Solved by the Invention]

On the other hand, if the narrow space between the connection terminals is promoted, there is a case where unevenness in height between the connection terminals occurs. In particular, the connection terminals formed by the electrolytic plating method may have high unevenness (coplanarity). If the coplanarity is increased, there is a concern that a connection failure may occur between the wiring substrate and the semiconductor element.

In addition, in a multilayer wiring substrate, a plurality of conductor patterns must be arranged in a lamination direction or in-plane direction of each layer at a high density without shorting each other. Therefore, the arrangement pattern of the conductor patterns constituting each wiring layer must be in each layer. In different. Therefore, when the multilayer wiring substrate is viewed along the build-up direction, the area where the conductor pattern in one wiring layer exists and the area where the conductor pattern in the other wiring layer exists partially do not overlap. . In the case where wiring layers having different conductor pattern configurations are laminated via an insulating layer in order to produce such a multilayer wiring substrate, the height of the insulating layer on the area where the conductor pattern exists in each wiring layer, and The height of the insulating layer on the area where the conductor pattern does not exist becomes different. Therefore, the height positions of the electrodes provided on the surface layer of the multilayer wiring substrate are different.

In general, in a multilayer wiring substrate, in order to stably perform surface mounting of electronic components such as semiconductor wafers, it is preferable that the height positions of a plurality of electrodes provided on the surface layer are substantially the same. However, since the height positions of the plurality of electrodes provided on the surface layer do not substantially coincide with each other as described above, it becomes difficult to stably construct electronic components.

In view of the above-mentioned problems, one of the objects of the present invention is to provide a wiring board with less unevenness in the height of the connection terminals. In addition, one of the objects of the present invention is to provide a high-quality wiring substrate capable of stably mounting electronic components, and a component structure assembly line substrate. [Means for solving problems]

According to an embodiment of the present invention, there is provided a wiring substrate including a substrate, an insulating layer on the substrate, a height adjusting portion provided in the insulating layer, a first conductive portion provided on the insulating layer, and a first conductive portion. The second conductive portion adjacent to the insulating layer and the height adjustment portion is adjacent to the second conductive portion, the height from the upper surface of the substrate to the upper surface of the first conductive portion, and the height from the upper surface of the substrate to the upper surface of the second conductive portion. The height is roughly the same.

The above wiring substrate may include a lower wiring provided between the substrate and the insulating layer, and a via portion provided in the insulating layer and disposed on the lower wiring. The height adjustment portion is adjacent to the via portion and is provided on the insulating layer. The first conductive portion is not only disposed on the insulating layer and the via portion, but also electrically connected to the lower wiring.

In the above wiring substrate, the height from the upper surface of the substrate to the bottom of the via portion may be different from the height from the upper surface of the substrate to the bottom of the dummy via portion.

In the above wiring substrate, the height from the upper surface of the substrate to the bottom of the via portion may be longer than the height from the upper surface of the substrate to the bottom of the via portion.

In the above wiring substrate, a part of the lower wiring may overlap and be separated from the second electrode in a cross-sectional view.

In the above-mentioned wiring substrate, the difference between the height from the upper surface of the substrate to the uppermost part of the first electrode in a cross-sectional view and the height from the upper surface of the substrate to the uppermost part of the second electrode may be 1 μm or less.

In the above-mentioned wiring substrate, the distance between the center line of the first electrode and the center line of the second electrode may be 10 μm or more and 100 μm or less in a cross-sectional view.

In the above wiring substrate, the distance between the center of the first electrode and the center of the second electrode may be 20 μm or more and 50 μm or less.

In the above wiring substrate, the diameter of the upper portion of the via portion and the diameter of the upper portion of the dummy via portion may be 3 μm or more and 30 μm or less.

In the above wiring substrate, the distance between the center of the bottom of the via portion and the center of the bottom of the dummy via portion may be 5 μm or more and 10 μm or less.

In the above wiring substrate, the upper surfaces of the first electrode and the second electrode may be curved.

The wiring board may further include upper wiring arranged on the insulating layer, and the upper wiring is electrically connected to the second electrode.

In the above wiring substrate, the first conductive portion, the second conductive portion, the height adjustment portion, and the insulating layer are part of a multilayer wiring layer formed by sequentially stacking the first to Nth (N is an integer of 2 or more) wiring layers. And an interlayer connection portion is provided for electrically connecting at least two wiring layers in the first to Nth wiring layers to each other, and the insulating layer electrically separates the respective wiring layers in the first to Nth wiring layers, The first conductive portion and the second conductive portion constitute an N-th wiring layer, and the height adjustment portion may be provided below at least a portion of the conductive portions constituting the first to N-1th wiring layers below the stacking direction of the second conductive portion. .

In the above-mentioned wiring substrate, N is an integer of 3 or more, and a plurality of height adjustment portions may be provided below the lamination direction of at least a part of the conductor pattern constituting the N-th wiring layer.

In the above wiring substrate, the height adjustment portion may be electrically separated between the first to Nth wiring layers.

The wiring board may further include a plurality of electrodes electrically connected to the Nth wiring layer.

According to an embodiment of the present invention, a component structure assembly line substrate is provided, which includes the wiring substrate and at least one electronic component configured to be electrically connected to any one of a plurality of electrodes.

According to an embodiment of the present invention, there is provided a semiconductor device including the wiring substrate and a semiconductor element.

In the above semiconductor device, the semiconductor element may be a light emitting element.

According to an embodiment of the present invention, there is provided a method for manufacturing a wiring substrate, which includes forming lower wiring on a substrate, forming an insulating layer on the substrate and the lower wiring, and forming a via portion on the insulating layer so as to overlap the lower wiring, so as to communicate with the lower wiring. When the via portions are adjacent, a dummy via portion is formed on the insulating layer, a first electrode is formed on the via portion and the insulating layer, and a second electrode is formed on the dummy via portion and the insulating layer.

In the manufacturing method of the said wiring board, the height from the upper surface of a board | substrate to the bottom part of a via | path part in a cross-sectional view may be different from the height from the upper surface of a board | substrate to the bottom of a dummy via part.

In the manufacturing method of the above-mentioned wiring board, the via portion and the dummy via portion may be formed by a photolithography method or a laser irradiation method using a half-tone mask. [Inventive effect]

According to an embodiment of the present invention, a wiring board having less unevenness in the height of the connection terminals can be provided. In addition, according to an embodiment of the present invention, it is possible to provide a high-quality wiring substrate capable of stably mounting electronic components, and a component structure assembly line substrate.

Hereinafter, a wiring board and the like according to each embodiment of the present invention will be described in detail with reference to the drawings. In addition, each embodiment shown below is an example of the embodiment of the present invention, and the present invention is not limited to these embodiments. In addition, in the drawings referred to in this embodiment, the same part or a part having the same function is marked with the same symbol or a similar symbol (only the symbols of -1, -2, etc. are labeled after the number), and repeated descriptions are omitted. Illustrated situation. In addition, there are cases where the dimensional proportions of the drawings are different from the actual ones for convenience of explanation, or a part of the structure is omitted from the drawings.

In the drawings attached to this manual, the shapes, scales, and aspect ratios of the various parts may be changed or exaggerated from the real thing for easy understanding.

The numerical range indicated by "~" in this specification and the like means a range including numerical values described before and after "~" as the lower limit value and the upper limit value, respectively. In this manual and the like, terms such as "film", "sheet", and "board" are not distinguished from each other based on differences in titles. For example, "board" also includes the concept of a member that can be generally referred to as "sheet" and "film".

<First Embodiment> (1-1. Configuration of Light-Emitting Device) FIG. 1 is a cross-sectional view of a light-emitting device 1000 which is one of semiconductor devices. The light emitting device 1000 includes a wiring substrate 100, an external terminal 105, a conductive portion 150, a light emitting element 300, a terminal 310, a reflective material 320, a sealing material 330, a lens 340, and a protective member 350.

The light-emitting element 300 is one of semiconductor elements. In this example, a GaN-based light-emitting diode is used.

The reflecting material 320 has a function of reflecting light. The reflective material 320 includes a metal material. In this example, aluminum is used for the reflecting material 320. In addition, the reflective material 320 may be one in which metal is vapor-deposited on the surface of a resin formed by a mold.

The sealing material 330 has a function of protecting the light-emitting element from external components such as moisture. As the sealing material 330, an organic resin such as an epoxy resin or a silicone resin is used. In addition, in the sealing material 330, an inert gas may be used in addition to the organic resin.

The lens 340 has a function of diffusing or condensing light from the light emitting element. The lens 340 is made of a transparent material such as quartz.

The protective member 350 has a function of protecting the light emitting element from a physical impact. The protective member 350 has a light-transmitting property. The protective member 350 uses an organic resin such as an epoxy resin or an acrylic resin.

The wiring substrate 100 is electrically connected to the light emitting element 300. In this example, the conductive portion 150 (for example, the conductive portion 150-1 described later) of the wiring substrate 100 and the terminal 310 of the light emitting element 300 are connected by a flip chip method. At this time, 24 or more conductive portions 150 (for example, conductive portions 150-1 described later) of the wiring board are arranged. An external terminal 105 is provided on the wiring substrate 100. The external terminal 105 is connected to an external wiring board or electrode. Details of the wiring substrate 100 and the conductive portion 150 will be described below. The conductive parts, terminals, wiring, and electrodes can be used with the same meaning.

(1-2. Configuration of Wiring Board) FIG. 2 is a plan view of the wiring board 100 of FIG. 1. FIG. 3 is a cross-sectional view between A1 and A2 in the wiring substrate 100.

The wiring substrate 100 includes a substrate 110, a lower wiring 120, an insulating layer 130, a via portion 141, a dummy via portion 143, and a conductive portion 150 (conductive portion 150-1, conductive portion 150-2).

A high-resistance material is used for the substrate 110. For example, a silicon substrate is used as the substrate 110. The thickness of the substrate 110 is not particularly limited, and can be appropriately set within a range of 100 μm to 700 μm. For example, as the plate thickness of the substrate 110, 400 μm is used.

In addition, the substrate 110 may be an organic resin. For example, when the substrate 110 is an organic resin such as a polyimide resin, the thickness of the substrate 110 may be several μm or more and several tens μm or less.

The lower wiring 120 is disposed on the substrate 110. Copper (Cu) is used for the lower wiring 120. In addition, in the lower wiring 120, in addition to copper (Cu), metal materials such as aluminum (Al), titanium (Ti), tungsten (W), gold (Au), silver (Ag), or nickel (Ni) may be used. .

The insulating layer 130 is provided on the substrate 110 and the lower wiring 120. For example, polyimide resin is used for the insulating layer 130. The polyimide resin may include a photosensitive material.

The insulating layer 130 is not limited to the above. For example, an inorganic insulating material such as a silicon oxide film or a silicon nitride film may be used for the insulating layer 130. In addition, as the insulating layer 130, other organic insulating materials such as an acrylic resin and an epoxy resin may be used.

The via portion 141 is a recessed portion provided on the insulating layer 130. The via portion 141 is disposed on the lower wiring 120.

The dummy via portion 143 is a recessed portion adjacent to the via portion 141 and provided on the insulating layer 130.

The conductive portion 150 is disposed on the insulating layer 130. Among the conductive portions 150, those disposed on the insulating layer 130 and the via portion 141 are referred to as a conductive portion 150-1 (or sometimes referred to as a first conductive portion). In the above, the conductive portion 150-1 protrudes above the insulating layer 130. In addition, among the conductive portions 150, those disposed on the insulating layer 130 and the dummy via portion 143 are referred to as conductive portions 150-2 (or sometimes referred to as a second conductive portion). In the above, the conductive portion 150-2 protrudes above the insulating layer 130. The conductive portion 150-2 is disposed adjacent to the conductive portion 150-1. When it is not necessary to describe the conductive portion 150-1 and the conductive portion 150-2 separately, the conductive portion 150 will be described.

The conductive portion 150 includes a seed layer 147. Although copper (Cu) is used for the seed layer 147 and the conductive part 150, it is not limited to this, and gold (Au), silver (Ag), palladium (Pd), nickel (Ni), and tin (Sn) may be used.

In addition, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 may be uneven. In this example, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 are curved. Specifically, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 have a convex shape.

In addition, in FIG. 3, a region 150-1F of the conductive portion 150-1 provided in the via portion 141 is electrically connected to the lower wiring 120. On the other hand, the region 150-2F of the conductive portion 150-2 provided in the dummy path portion 143 and the lower wiring 120 are not electrically connected. That is, the area 150-2F may not be a constituent element of the circuit with respect to the area constituting the area 150-1F.

Next, details of the position configuration of the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2 will be described below.

FIG. 4 is a cross-sectional view showing the positional configuration of the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2 in the wiring substrate 100. As shown in FIG. 4, the distance from the upper surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141 is set as the distance DL1. Similarly, the distance from the upper surface 110A of the substrate 110 to the bottom portion 143D of the dummy path portion 143 is set as the distance DL2. At this time, the distance DL1 and the distance DL2 may be different. Specifically, the distance DL2 is preferably longer than the distance DL1.

In addition, in FIG. 4, the diameter 141W above the via portion 141 and the diameter 143W above the dummy via portion are preferably 3 μm or more and 30 μm or less, and more preferably 5 μm or more and 10 μm or less.

In addition, in FIG. 4, the distance between the center line 150-1C of the conductive portion 150-1 and the center line 150-2C of the conductive portion 150-2 in the vertical direction with respect to the substrate 110 (sometimes referred to as an interval distance) 150P is preferably 10 μm or more and 100 μm or less, and more preferably 20 μm or more and 50 μm or less.

(1-3. Regarding uneven height of terminals) The unevenness of the height of the terminals will be described below. The distance from the upper surface 110A of the substrate 110 to the uppermost portion 150-1A of the conductive portion 150-1 is set to the distance UL150-1. Similarly, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 150-2A of the conductive portion 150-2 is set to the distance UL150-2.

Here, a cross-sectional view of a conventional wiring board 90 is shown in FIG. 36. In FIG. 36, the wiring substrate 90 has the same configuration as the wiring substrate 100 except that it does not include the dummy path portion 143. Since the wiring substrate 90 does not have the dummy via portion 143, the conductive portion 150-2 is provided only on the insulating layer 130.

In the wiring board 90, it is difficult to make the shape of the conductive portion 150-1 provided in the via portion 141 and the shape of the conductive portion 150-2 without the via portion 141 the same. Therefore, the difference between the distance UL150-1 and the distance UL150-2 is about 1.5 to 3 μm, the height of the terminal is unstable, and a step is generated. Therefore, if the distance 150P between the wiring substrates 90 becomes smaller, that is, becomes a narrow interval (specifically, the distance 150P between the intervals is 100 μm or less, and more specifically 50 μm or less), the terminals of the wiring substrate 90, A connection failure with a terminal of a semiconductor element is likely to occur. In particular, the above-mentioned connection failure becomes significant when the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 have a convex shape.

On the other hand, in the case of the wiring substrate 100 shown in FIG. 4 described above, a dummy path portion 143 (also referred to as a height adjustment portion) is provided in a portion without the path portion 141, thereby reducing the distance UL150-1 and The distance from UL150-2. Specifically, in the case of the wiring substrate 100, the difference between the distance UL150-1 and the distance UL150-2 may be 1 μm or less, and more specifically, 0.5 μm or less. That is, by using this embodiment, it is possible to provide a wiring board with less unevenness in the height of the connection terminals. This prevents defective connection between the terminals of the wiring substrate and the terminals of the semiconductor element.

(1-4. Manufacturing Method of Wiring Board) Next, a manufacturing method of the wiring board 100 shown in FIGS. 2 to 4 will be described using FIGS. 5 to 12.

As shown in FIG. 5, a substrate 110 is used. For example, as the substrate 110, a high-resistance substrate such as a silicon substrate is used.

In addition, the substrate 110 is not limited to the above, and a quartz glass substrate, a soda glass substrate, a borosilicate glass substrate, an alkali-free glass substrate, a sapphire substrate, an aluminum carbide (Al ₂ O ₃ ) substrate, or aluminum nitride ( AlN) substrate, zirconia (ZrO ₂ ) substrate, resin substrate containing acrylic, polycarbonate, etc., or a laminate of these substrates.

In addition, the substrate 110 may be an organic insulating layer or an inorganic insulating layer formed on a metal substrate. In addition, the substrate 110 may be a through electrode substrate. In this case, since an electric current can flow from the upper surface 110A of the substrate 110 to the opposite side, it is preferable to separately provide the external terminal 105 shown in FIG. 1.

Next, as shown in FIG. 6, a lower wiring 120 is formed on the substrate 110. The lower wiring 120 is formed using a plating method, a screen printing method, a sputtering method, or a chemical vapor deposition (CVD) method. The lower wiring 120 is suitably processed into a predetermined shape by a photolithography method and an etching method. The lower wiring 120 is disposed on the substrate 110. Copper (Cu) is used for the lower wiring 120. In addition, in addition to copper (Cu), the lower wiring 120 may use aluminum (Al), gold (Au), silver (Ag), nickel (Ni), tungsten (W), molybdenum (Mo), or titanium (Ti). And other metal materials.

Next, as shown in FIG. 7, an insulating layer 130 is formed on the substrate 110 and the lower wiring 120. The insulating layer 130 is formed using a printing method, a coating method, or a dipping method. Organic resins such as polyimide, acrylic, epoxide, and Benzocyclobutene (BCB) can also be used for the insulating layer 130. In addition, as the insulating layer 130, an organic-inorganic mixed resin containing silicon dioxide may be used in addition to the organic resin, and an inorganic film such as silicon oxide, silicon nitride, or the like formed by a plasma CVD method may be used. When the insulating layer 130 is an organic resin, a photosensitive material may be included. For example, as the insulating layer 130, a polyimide resin containing a photosensitive material such as diazonaphthoquinone, which is formed by a coating method, is used.

Then, as shown in FIG. 8, a via portion 141 and a dummy via portion 143 are formed on the insulating layer 130. The via portion 141 is formed so as to overlap the lower wiring 120. The dummy passage portion 143 has a predetermined interval and is formed adjacent to the passage portion 141. The passage portion 141 and the dummy passage portion 143 are formed using a photolithography method.

When using the photolithography method, it is preferable to use a halftone mask. Specifically, when a polyimide resin having a positive-type photosensitive material (diazonaphthoquinone or the like) is exposed, a portion corresponding to the passage portion 141 is exposed in the same manner as usual. On the other hand, the portion corresponding to the virtual path portion 143 is exposed by a lower exposure amount than the portion corresponding to the path portion 141 by a semi-transmissive film provided on the halftone mask. Therefore, the distance DL1 from the upper surface 110A of the substrate 110 after development to the bottom portion 141D of the via portion 141 may be different from the distance DL2 from the upper surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143. Specifically, the distance DL2 is longer than the distance DL1 (in other words, it can be said that the depth of the virtual passage portion 143 is shallow compared to the depth of the passage portion 141). By the above-mentioned processing, the upper surface of the lower wiring 120 is exposed in the via portion 141.

Next, a conductive portion 150 is formed. First, as shown in FIG. 9, a seed layer 147 is formed on the insulating layer 130, the via portion 141, and the dummy via portion 143. The seed layer 147 is formed by an electroless plating method, a sputtering method, a printing method, or the like. In the seed layer 147, in addition to copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), palladium (Pd), and the like are used. For example, as the seed layer 147, a copper (Cu) film formed by an electroless plating method is used.

Next, as shown in FIG. 10, a resist film 149 is formed on the seed layer 147. The resist film 149 may be formed by a coating method, or a dry film resist may be used. The resist film 149 is processed into a predetermined shape by a photolithography method.

Next, as shown in FIG. 11, a conductive portion 150 is formed on the exposed portion of the seed layer 147. The conductive portion 150 is formed by an electrolytic plating method. At this time, a conductive portion 150-1 is formed on the insulating layer 130 and the via portion 141 in the conductive portion 150, and a conductive portion 150-2 is formed on the insulating layer 130 and the dummy via portion 143.

Finally, as shown in FIG. 12, a portion of the seed layer 147 where the resist film 149 (see FIG. 11) and the conductive portion 150 are not formed is removed. The above method is called a semi-additive method. The wiring substrate 100 is manufactured by the above method.

<Second Embodiment> Next, a wiring substrate different from the structure of the wiring substrate 100 will be described. Note that the same structure, materials, and methods as those of the wiring substrate 100 shown in the first embodiment will be referred to this description. In addition, the configurations of the respective wiring boards can be used in appropriate combination.

(2-1. Configuration of Wiring Substrate 100-1) FIG. 13 shows a plan view of the wiring substrate 100-1 and a cross-sectional view between A1-A2 of the wiring substrate 100-1 in FIG. 14. As shown in FIGS. 13 and 14, the wiring substrate 100-1 includes a substrate 110, a lower wiring 120, an insulating layer 130, a via portion 141, a dummy via portion 143, a conductive portion 150-1, and a conductive portion 150-2. It also includes an upper wiring 160.

The upper wiring 160 is disposed on the insulating layer 130. The upper wiring 160 is electrically connected to the conductive portion 150-2. In the wiring substrate 100-1, the conductive portion 150-2 can be used as a terminal. The wiring substrate 100-1 can provide the same effect as the wiring substrate 100 by including the dummy via portion 143 (the difference between the height of the conductive portion 150-1 and the height of the conductive portion 150-2 becomes smaller).

(2-2. Configuration of wiring substrate 100-2) FIG. 15 shows a plan view of the wiring substrate 100-2 and a cross-sectional view between A1-A2 of the wiring substrate 100-2 in FIG. 16. As shown in FIGS. 15 and 16, the wiring substrate 100-2 includes a substrate 110, a lower wiring 120-2, an insulating layer 130, a via portion 141, a dummy via portion 143, a conductive portion 150-1, a conductive portion 150-2, and an upper portion. Wiring 160.

The lower wiring 120-2 is extended to be electrically connected to the left conductive portion 150-1 (conductive portion 150-1L) and the right conductive portion 150-1 (conductive portion 150-1R). At this time, a portion 120-2P, which is a portion of the lower wiring 120-2, overlaps and is isolated from the conductive portion 150-2. By having this structure, the wiring substrate 100-2 can effectively use space.

(2-3. Configuration of Wiring Substrate 100-3) FIG. 17 shows a plan view of the wiring substrate 100-3 and a cross-sectional view between A1-A2 of the wiring substrate 100-3 in FIG. 18. As shown in FIG. 17 and FIG. 18, the wiring substrate 100-3 includes, in addition to the substrate 110, the lower wiring 120-3, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1 and the conductive portion 150-2. In addition, it also has an upper wiring 160-3.

In the wiring substrate 100-3, a plurality of conductive portions 150-2 are arranged around the conductive portion 150-1. Specifically, eight conductive portions 150-2 are arranged around one conductive portion 150-1.

The lower wiring 120-3 and the upper wiring 160-3R of the upper wiring 160-3 are arranged in parallel with the insulating layer 130 interposed therebetween.

(2-4. Configuration of Wiring Substrate 100-4) A cross-sectional view of the wiring substrate 100-4 is shown in FIG. 19. As shown in FIG. 19, the wiring substrate 100-4 includes insulation in addition to the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2. The layer 165, the via portion 171, the dummy via portion 173, and the conductive portion 180 (the conductive portion 180-1 and the conductive portion 180-2).

In the wiring substrate 100-4, the via portion 171 is provided on the insulating layer 165 and is disposed on the conductive portion 150-1. The dummy via portion 173 is provided on the insulating layer 165 and is arranged to overlap the conductive portion 150-2. The conductive portion 180-1 is disposed on the insulating layer 165 and the via portion 171. The conductive portion 180-2 is disposed on the insulating layer 165 and the dummy via portion 173.

The insulating layer 165 is formed using the same material and method as the insulating layer 130. The insulating layer 165 is formed flat with respect to the upper surface 110A of the substrate 110 by the conductive portion 150-2 being disposed. The passage portion 171 is formed by the same method as the passage portion 141. The virtual path section 173 is formed by the same method as the virtual path section 143. The conductive portion 180 is formed using the same material and method as the conductive portion 150.

As shown in FIG. 19, in the wiring substrate 100-5, a conductive portion 150 and a conductive portion 180 are laminated. Here, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 180-1A of the conductive portion 180-1 is defined as the distance UL180-1. Similarly, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 180-2A of the conductive portion 180-2 is set as the distance UL180-2. At this time, the difference between the distance UL180-1 and the distance UL180-2 can be set to 1 μm or less. Therefore, the wiring substrate 100-5 can be mounted at a high density similarly to the wiring substrate 100.

In addition, in the wiring substrate 100-5, the conductive portion 180-2 and the conductive portion 150-2 may be connected.

(2-5. Configuration of Wiring Substrate 100-5) A cross-sectional view of the wiring substrate 100-5 is shown in FIG. 20. As shown in FIG. 20, the wiring substrate 100-5 includes insulation in addition to the substrate 110, the lower wiring 120, the insulating layer 130, the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2. The layer 165, the via portion 171, the via portion 175, the conductive portion 183 (the conductive portion 183-1 and the conductive portion 183-2), and the conductive portion 185 (the conductive portion 185-1 and the conductive portion 185-2). The passage portion 175 is formed by the same method as the passage portion 171.

Among the conductive portions 183, the conductive portion 183-1 is disposed on the insulating layer 165 and the conductive portion 150-1. The conductive portion 183-1 is connected to the conductive portion 150-1. Similarly, in the conductive portion 183, the conductive portion 183-2 is disposed on the insulating layer 165 and the conductive portion 150-2. The conductive portion 183-2 is connected to the conductive portion 150-2.

The conductive portion 183 is formed by an electroless plating method. The conductive portion 183 is sequentially laminated with nickel (Ni), palladium (Pd), and gold (Au). In addition, the conductive portion 183 is sometimes referred to as UBM (Under Bump Metallization).

Among the conductive portions 185, the conductive portion 185-1 is disposed on the conductive portion 183-1. Among the conductive portions 185, the conductive portion 185-2 is disposed on the conductive portion 183-2.

The conductive portion 185 contains tin (Sn). The conductive portion 185 is soldered to the conductive portion 183. The conductive portion 185 is sometimes referred to as a solder bump.

In the wiring substrate 100-5 shown in FIG. 20, a conductive portion 183 and a conductive portion 185 are sequentially stacked on the conductive portion 150. Here, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 185-1A of the conductive portion 185-1 is defined as the distance UL185-1. Similarly, the distance from the upper surface 110A of the substrate 110 to the uppermost portion 185-2A of the conductive portion 185-2 is set to the distance UL185-2. At this time, the difference between the distance UL185-1 and the distance UL185-2 can be set to 1 μm or less. Therefore, in the wiring substrate 100-5, connection failure can be suppressed, and high-density mounting can be performed.

In addition, although the wiring substrate 100-5 shows an example in which the conductive portion 183 and the conductive portion 185 are laminated, only one of the conductive portion 183 and the conductive portion 185 may be arranged.

<Third Embodiment> A multilayer wiring substrate, which is one of the wiring substrates having a structure different from that of the first embodiment and the second embodiment, will be described below with reference to the drawings. Fig. 21 is a schematic cross-sectional view showing a multilayer wiring board according to a third embodiment. A schematic configuration of the multilayer wiring board 200 according to the third embodiment will be described. The multilayer wiring substrate 200 is provided on the upper surface 210H of the substrate 210 and includes a multilayer wiring layer 200A in which a first wiring layer WL1 and a second wiring layer WL2 are sequentially laminated. In the multilayer wiring layer 200A, an insulating layer 221 is positioned between the first wiring layer WL1 and the second wiring layer WL2, and an insulating layer 222 is positioned above the second wiring layer WL2. An electrode 241 (also referred to as a first electrode) and an electrode 242 (also referred to as a second electrode) are provided on the insulating layer 222 that is a surface layer of the multilayer wiring layer 200A. The electrode 242 is disposed adjacent to the electrode 241.

The first wiring layer WL1 includes a conductor pattern 211, and the second wiring layer WL2 includes a conductor pattern 212 (also referred to as a first conductive portion) and a conductor pattern 213. The conductor pattern 211 is located on the upper surface 210H of the substrate 210 together with a height adjustment pattern 250 (also referred to as a height adjustment section) described later, and the conductor pattern 211 and the height adjustment pattern 250 are located on the surface of the substrate 210 on the upper surface 210H. In the direction, they are positioned at a predetermined distance from each other. The conductive pattern 212 and the conductive pattern 213 are positioned in the in-plane direction on the insulating layer 221 and spaced apart from each other by a predetermined distance. A via 231 is provided on the conductive pattern 211 as an interlayer connection portion. The electrode 241 is continuously located on the upper surface of the conductive pattern 212, and the electrode 242 is continuously located on the upper surface of the conductive pattern 213. Each of these structures will be described in detail below. The conductive patterns 211, 212, and 213 are also referred to as conductive portions. A conductor pattern described later can also be used as a conductive portion. Furthermore, the conductive pattern 212 is also referred to as a first conductive portion, and the conductive pattern 213 is also referred to as a second conductive portion.

The “substrate” of the third embodiment is not an abbreviation of an electronic circuit substrate, and means a board that is used as a base (base) for making the multilayer wiring substrate 200. That is, as long as the wiring layer and the insulating layer are sequentially laminated to form a wiring substrate, the substrate 210 may not be a necessary configuration in the multilayer wiring substrate 200. The type of the substrate 210 is not particularly limited, and examples thereof include a glass epoxy substrate, a glass substrate, and a silicon substrate. The size and thickness of the substrate 210 can be appropriately set according to the required size of the multilayer wiring substrate 200 or the size or number of electronic components mounted on the multilayer wiring substrate 200. In addition, as the electronic components that can be mounted on the multilayer wiring board 200 according to the third embodiment, for example, in addition to active components such as relays, transistors, and integrated circuits (ICs), resistors and capacitors can also be cited. , Inductors and other passive components. In addition, in the third embodiment, a multilayer wiring board formed by arranging any one or more of the electronic parts exemplified above is referred to as a "part structure assembly line substrate".

The conductive pattern 211 and the conductive pattern 212 include conductive materials such as copper (Cu), nickel (Ni), and gold (Au). In the third embodiment, the conductor pattern 211 and the conductor pattern 212 are connected to each other via a via 231, and an electrode 241 is connected to the upper surface of the conductor pattern 212, whereby the conductor pattern 211, the conductor pattern 212, and the electrode 241 can be electrically connected to each other. Sexual connection (Figure 21).

The conductor pattern 213 is also the same as the conductor pattern 211 and the conductor pattern 212, and includes, for example, a conductive material such as copper (Cu), nickel (Ni), and gold (Au). In the third embodiment, an electrode 242 is connected to the upper surface of the conductive pattern 213, whereby the conductive pattern 212 and the electrode 242 can be electrically connected to each other (FIG. 21). In addition, the width or thickness of the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213 can be appropriately set according to the size of the multilayer wiring substrate 200, the size or number of electronic components configured on the multilayer wiring substrate 200, and the like.

The insulating layer 221 and the insulating layer 222 include, for example, insulating materials such as epoxy resin, polyimide resin, and acrylic resin. The insulating layer 221 is located on the upper surface 210H of the substrate 210 so as to cover the conductive pattern 211 and the height adjustment part 50, and the insulating layer 222 is located on the upper surface of the insulating layer 221 so as to cover the conductive pattern 212 and the conductive pattern 213. In addition, the thickness of the insulating layer 221 and the insulating layer 222 can be appropriately set according to the required size of the multilayer wiring substrate 200 or the size or number of each conductor pattern.

The via 231 is the same as each of the conductor patterns 211 to 213, and includes, for example, a conductive material such as copper (Cu), nickel (Ni), and gold (Au). The size or depth (height) of the via 231 is not particularly limited, and can be appropriately set according to the required size of the multilayer wiring substrate 200, the size and number of each of the conductor patterns 211 to 213, and the thickness of each insulating layer.

The electrodes 241 and 242 include, for example, metal materials such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), and lead-tin alloy. The electrodes 241 and 242 may be electrically connected to external terminals of electronic components such as a semiconductor wafer that is mounted on the multilayer wiring substrate 200. As long as the electronic components can be stably constructed on the multilayer wiring substrate 200, the size and thickness of the electrodes 241 and 242, or the shapes or protruding heights of the electrodes 241, 242 protruding from the upper surface of the insulating layer 222 are not limited to The form shown in FIG. 21. A portion of the electrode 241 protruding from the upper portion of the insulating layer 222 is referred to as a first protruding portion, and a portion of the electrode 242 protruding from the upper portion of the insulating layer 222 is referred to as a second protruding portion. Although not shown, UBM (Under Bump Metallization) may be provided between each of the electrodes 241 and 242 and each of the conductor patterns 212 and 213.

The height adjustment pattern 250 is located in the in-plane direction of the upper surface 210H of the substrate 210, is disposed in the insulating layer 221, and is positioned at a predetermined distance from the conductor pattern 211. The “pattern for height adjustment (also referred to as a height adjustment portion)” means a conductor pattern (directly in the third embodiment, the conductor pattern 212 and the conductor pattern 212 and The pattern in which the height position in the lamination direction of the conductive pattern 213) is adjusted. In addition, the "adjustment" here includes the following meanings: as long as the electronic components can be stably mounted on the multilayer wiring substrate 200, the electrodes for mounting the electronic components are used (in the third embodiment, the electrodes 241 and 242) In a manner that the height positions are substantially the same, adjust the height of the conductor pattern directly below the electrode. In the third embodiment, the height-adjusting pattern 250 is located directly below the layered direction of the conductor pattern 213 so as to correspond to the formation position of the conductor pattern 213 (electrode 242). The height adjustment pattern 250 has a thickness substantially the same as the thickness of the conductor pattern 211. In the third embodiment, the height-adjusting pattern 250 is provided directly below the layered direction of the conductor pattern 213, and is positioned at the same height (level) as the layered conductor pattern 211 (first wiring layer WL1), and is provided on the upper surface. The height positions in the lamination direction of the conductive pattern 212 and the conductive pattern 213 on the substantially flat insulating layer 221 are substantially the same. The material constituting the height adjustment pattern 250 may be, for example, a non-conductive material such as a photosensitive resin material, or a conductive material such as copper (Cu), nickel (Ni), or gold (Au). When the height-adjusting pattern 250 of the third embodiment includes a conductive material, it is preferably between the conductive pattern 211, the conductive pattern 212, and the conductive pattern 213 from the viewpoint of preventing a short circuit with another conductive pattern. Electrical separation. In addition, the material of the height adjustment pattern 250 is not specifically limited unless it is previously described in this specification.

FIG. 37 is a reference diagram showing a multilayer wiring board 200 ′ in which a difference in height position in the stacking direction occurs in the insulating layer 222 ′ as a surface layer without providing the height adjustment pattern 250. In addition, in FIG. 37, "difference D" is drawn exaggerated for easy understanding, but it is not drawn as a difference actually generated. Referring to FIG. 37, the operation and effect of the height adjustment pattern 250 according to the third embodiment will be described in detail based on comparison with a multilayer wiring board without the height adjustment pattern 250.

In the multilayer wiring substrate 200 ′ shown in FIG. 37, a conductor pattern 211 is provided on a portion of the upper surface 210H of the substrate 210 that is directly below the layered direction of the electrode 241, but a portion that is directly below the layered direction of the electrode 242. The conductor pattern 211 is not provided. Therefore, in the process of forming the multilayer wiring substrate 200 ′, when an insulating layer 221 ′ is provided so as to cover the conductor pattern 211, a portion of the insulating layer 221 ′ covered by the conductor pattern 211 directly below the lamination direction of the electrode 241. The height position is only higher than the thickness of the conductor pattern 211 compared with the height position of the insulating layer 221 ′ portion directly below the lamination direction of the electrode 242.

When the conductor pattern 212 connected to the conductor pattern 211 via the via 231 is provided on the insulation layer 221 'in this state, and the conductor pattern 213 is provided on the insulation layer 221' directly below the stacking direction of the electrode 242, the conductor A difference D (FIG. 37) in the height position between the patterns 212 and the conductor pattern 213 in the lamination direction occurs. Therefore, a difference in height position also occurs between the electrode 241 provided on the upper surface of the conductive pattern 212 and the electrode 242 provided on the upper surface of the conductive pattern 213. In this way, it is difficult to stably construct an electronic component via the two electrodes having a difference in height position.

On the other hand, according to the multilayer wiring board 200 according to the third embodiment, as described above, by providing the height adjustment pattern 250 at the same height position as the conductor pattern 211 directly below the lamination direction of the electrode 242, it is possible to make The upper surfaces of the insulating layers 221 provided on the upper layers are substantially flat, so that the height positions of the two conductor patterns 212 and 213 formed on the insulating layer 221 are substantially the same (FIG. 21). Therefore, the height positions of the electrode 241 and the electrode 242 of the electronic component (specifically, the height from the upper surface of the substrate 210 to the upper surface of the electrode 241 and the upper surface of the substrate 210 to the upper surface of the electrode 242 can be configured). The heights up to this point are also approximately the same. Therefore, a high-quality multilayer wiring board 200 capable of stably mounting electronic components can be realized. The height adjustment pattern 250 is preferably provided so that the difference in height position between the conductor patterns 212 and 213 is within a range of, for example, 0 μm to 3 μm, and preferably 1.5 μm or less. By adjusting the difference in the height position within the above-mentioned range, electronic components can be structured approximately parallel to the surface layer of the multilayer wiring substrate 200. If the difference between the height positions exceeds 3 μm, there is a concern that a poor connection between the electronic component and the multilayer wiring substrate 200 may easily occur when the electronic component is mounted on the multilayer wiring substrate 200.

<Fourth Embodiment> Fig. 22 is a schematic cross-sectional view showing a multilayer wiring board according to a fourth embodiment. In addition, components that are substantially the same as those in the third embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The multilayer wiring board 200 according to the fourth embodiment is different from the third embodiment in that it includes a multilayer wiring layer 200A formed by stacking three layers of first to third wiring layers WL1 to WL3, and constitutes a third wiring layer WL3. A height adjustment pattern 251 is provided directly below the layered direction of the conductor pattern 213 (electrode 242), and a height adjustment pattern 250 is provided directly below the layered direction of the height adjustment pattern 251. That is, in the multilayer wiring substrate 200 according to the fourth embodiment, a second wiring layer WL2 is provided between the first wiring layer WL1 and the third wiring layer WL3, and the second wiring layer WL2 includes a conductor pattern 214. An insulating layer 223 is positioned between the second wiring layer WL2 and the third wiring layer WL3.

The conductor pattern 214 and the height adjustment pattern 251 are located on the insulating layer 221 together, and the conductor pattern 214 and the height adjustment pattern 251 are positioned at a predetermined distance from each other in the in-plane direction on the insulation layer 221. The conductor pattern 214 is provided with a via 232 as an interlayer connection portion. The height adjustment pattern 251 has a thickness substantially the same as the thickness of the conductor pattern 214, and has a structure substantially the same as the height adjustment pattern 250.

The conductor pattern 214 is similar to the conductor pattern 211, the conductor pattern 212, and the conductor pattern 213, and includes, for example, a conductive material such as copper (Cu), nickel (Ni), and gold (Au). In the fourth embodiment, the conductor pattern 211 and the conductor pattern 214 are connected via a via 231, the conductor pattern 214 and the conductor pattern 212 are connected via a via 232, and an electrode 241 is connected to the conductor pattern 212, whereby the conductor patterns 211, The conductive pattern 214, the conductive pattern 212, and the electrode 241 can be electrically connected to each other (FIG. 22).

The insulating layer 223 is the same as the insulating layer 221 and the insulating layer 222, and may include an insulating material such as epoxy resin, polyimide resin, and acrylic resin. In addition, the thickness of the insulating layer 223 may be within a range such that there is no short circuit between adjacent wiring layers (the first wiring layer WL1 and the second wiring layer WL2, the second wiring layer WL2, and the third wiring layer WL3) in the lamination direction. Set appropriately.

The via 232 is the same as the via 231, and includes, for example, a conductive material such as copper (Cu), nickel (Ni), and gold (Au). The size (eg, width or depth) of the via 232 is not particularly limited, and can be appropriately set according to the required size of the multilayer wiring substrate 200, the size or interval of each conductor pattern, and the thickness of each insulating layer.

The height adjustment pattern 251 is positioned in the in-plane direction on the insulating layer 221 and is positioned at a predetermined distance from the conductor pattern 214. In the fourth embodiment, the conductor pattern 213 (electrode 242) is positioned above the height adjustment pattern 251, and the height adjustment pattern 250 is located below the height adjustment pattern 251. The height adjustment pattern 251 has a thickness substantially the same as the thickness of the conductor pattern 214. In the fourth embodiment, the height adjustment pattern 250 is positioned directly below the layered direction of the conductor pattern 213 (electrode 242) at the same height (level) as the conductor pattern 211 (first wiring layer WL1), and the height adjustment pattern is used. The pattern 251 is located at the same position as the conductor pattern 214 (the second wiring layer WL2), whereby the upper surface of the insulating layers 223 provided on the upper layers is substantially flat, so that the conductor patterns 212 and The height positions of the conductive patterns 213 (the third wiring layer WL3) in the lamination direction are substantially the same.

In the fourth embodiment, a multilayer wiring board 200 including a multilayer wiring layer 200A formed by stacking three wiring layers will be described, but the present invention is not limited to this, and may be formed by stacking wiring layers having four or more layers. Multilayer wiring board with multiple wiring layers.

<Fifth Embodiment> Fig. 23 is a schematic cross-sectional view showing a multilayer wiring board according to a fifth embodiment. In addition, components that are substantially the same as those in the third embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The multilayer wiring substrate 200 according to the fifth embodiment is different from the multilayer wiring substrate 200 according to the third embodiment in that the height adjustment pattern 250 is electrically connected to the conductor pattern 213 through the via 233. That is, in the fifth embodiment, the height adjustment pattern 250 includes, for example, a conductive material such as copper (Cu), nickel (Ni), and gold (Au). The via 233 is, of course, the same as the via 231, and includes, for example, a conductive material such as copper (Cu), nickel (Ni), and gold (Au).

According to the above configuration, as in the third embodiment, the upper surface of the insulating layer 221 is substantially flat, so that the conductive pattern 212 (electrode 241) and the conductive pattern 213 (electrode 242) provided on the insulating layer 221 can be stacked in the direction The height positions are substantially the same, and the height adjustment pattern 250 can be used for a part of the conductor pattern that is in conduction with the conductor pattern 213 (the electrode 242).

<Sixth Embodiment> FIG. 24 is a schematic cross-sectional view showing a multilayer wiring board according to a sixth embodiment. In addition, components that are substantially the same as those in the third embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The fourth embodiment is different from the multilayer wiring board 200 and the like in the third embodiment in that the conductor pattern 211 is located not only directly below the lamination direction of the conductor pattern 212 (electrode 241) but also the conductor pattern 213 (electrode 242). ) Is directly below the lamination direction, and is formed with a horizontally long width in the left-right direction on the diagram of the upper surface 210H of the substrate 210. That is, the conductor pattern 211 of the multilayer wiring board 200 according to the sixth embodiment also serves as a pattern for height adjustment. In the sixth embodiment, if the conductor pattern 211 of the first wiring layer WL1 is to be arranged in accordance with a general wiring rule, the conductor pattern 211 is arranged directly below the lamination direction of the electrode 241, but may be directly below the lamination direction of the electrode 242 The conductor pattern 211 is not arranged. In this case, in the third embodiment, the height positions of the conductor patterns 212 and 213 (electrodes 241 and 242) are made substantially uniform by providing the height adjustment pattern 250. In the sixth embodiment, instead of the height-adjusting pattern 250 of the third embodiment, the conductor pattern 211 that is not arranged according to the usual wiring rules is also directed downward in the direction of the lamination of the electrodes 242. This is the same as the third embodiment. The upper surface of the insulating layer 221 is substantially flat. Therefore, the height positions of the conductive pattern 212 (electrode 241) and the conductive pattern 213 (electrode 242) provided on the insulating layer 221 can be substantially the same.

<Seventh Embodiment> Fig. 25 is a schematic cross-sectional view showing a multilayer wiring board 200 according to a seventh embodiment. In addition, the same components as those of the multilayer wiring board 200 of each of the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof are omitted. In the seventh embodiment, on the upper surface 210H of the substrate 210, a conductor pattern 211 is provided in a region below the lamination direction of the electrode 241, and a height adjustment pattern 250 is provided in a region below the lamination direction of the electrode 242. Neither the conductor pattern 211 nor the height-adjusting pattern 250 is provided in a region below the stacking direction of a portion sandwiched between the electrode 241 and the electrode 242 (see FIG. 25). Therefore, when the insulating layer 221 covering the conductor pattern 211 and the height-adjusting pattern 250 is provided, a portion of the upper surface 210H of the substrate 210 is located in a region below the lamination direction of the portion sandwiched between the electrode 241 and the electrode 242. The height position of the covered insulating layer 221 portion becomes lower than the portions of the insulating layer 221 that respectively cover the conductor pattern 211 and the height adjustment pattern 250. A conductive pattern 217 is provided on the lowered insulating layer 221, and the height position of the insulating layer 223 portion covering the conductive pattern 217 becomes lower than the height of the insulating layer 223 covering the portion provided with the conductive pattern 214 and the conductive pattern 215, respectively. position. That is, in the second wiring layer WL2, the height positions of the conductor patterns 214 and 215 and the height positions of the conductor patterns 217 are staggered. A conductive pattern 218 is provided in the lower portion of the insulating layer 223 through the via 232C. Therefore, the height position of the insulating layer 222 portion covering the conductive pattern 218 becomes lower than the height position of the insulating layer 222 portion covering the conductive pattern 212 and the conductive pattern 213, respectively, and appears as a recess 222C on the upper surface of the insulating layer 222. .

In the multilayer wiring board 200 according to the seventh embodiment, a recessed portion 222C appears in the center in the plane of the surface layer of the multilayer wiring layer 200A. However, the height positions of the electrodes 241 and 242 constituting the electronic components are substantially the same. Therefore, the electronic component 270 can be stably mounted on the multilayer wiring board 200 via the electrodes 241 and 242. That is, like the multilayer wiring board 200 of the seventh embodiment, as long as it does not affect the stable placement of the electronic parts 270 such as the recessed portion 222C, the wiring layer located at the uppermost layer (as shown in FIG. 25) is constituted. In the form, the portion of each conductor pattern of the third wiring layer WL3) that is not connected to the electrode (the conductor pattern 218 shown in FIG. 25) can be lower in height than the portion that is connected to the electrode (the conductor pattern shown in FIG. 25). The height positions of 212, 213) may be substantially the same as the height positions of the electrodes capable of constructing the electronic component 270.

<Eighth Embodiment> Fig. 26 is a schematic cross-sectional view showing a multilayer wiring board 200 according to an eighth embodiment. In addition, the same components as those in the above-mentioned embodiments are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The multilayer wiring substrate 200 according to the eighth embodiment has a structure in which a via hole 210TH penetrating in a thickness direction of the substrate 210 is provided, and a multilayer wiring layer 200A is provided on an upper surface 210H of the substrate 210 and under the substrate 210. A multilayer wiring layer 200B is provided on the surface 210L. The via hole 210TH includes, for example, a conductive material such as copper (Cu), nickel (Ni), and gold (Au). The via hole 210TH functions as a conductor that electrically connects the conductor pattern 211 of the multilayer wiring layer 200A and the conductor pattern 261 of the multilayer wiring layer 200B. The multilayer wiring layer 200A has the same configuration as the multilayer wiring layer in the multilayer wiring substrate 200 of the third embodiment. As the multilayer wiring layer 200B according to the eighth embodiment, a multilayer structure in which the multilayer wiring layer 200A is inverted with the substrate 210 as a boundary is adopted. However, it is conveniently used for the sake of simplification of the description, and is not limited to this structure and can be appropriately set. Various laminated structures.

The multilayer wiring layer 200B is a first wiring layer WL200B composed of a conductor pattern 261 and a second wiring layer WL2B composed of a conductor pattern 262 and 263, which are sequentially laminated from the lower surface 210L side of the substrate 210, and are formed on the first wiring layer An insulating layer 271 is positioned between WL200B and the second wiring layer WL2B, and an insulating layer 272 is positioned so as to cover the second wiring layer WL2B. An electrode 281 and an electrode 282 are provided on a surface layer of the multilayer wiring layer 200B. The first wiring layer WL200B is composed of a conductor pattern 261, and the conductor pattern 261 is located on the lower surface 210L of the substrate 210 together with the height adjustment pattern 252. The conductive pattern 261 and the height-adjusting pattern 252 are positioned in the in-plane direction on the lower surface 210L of the substrate 210 and are positioned at a predetermined distance. The second wiring layer WL2B is composed of a conductor pattern 262 and a conductor pattern 263, and a path 34 is provided between the conductor pattern 261 and the conductor pattern 262 as an interlayer connection portion for electrically connecting the same. An electrode 281 is positioned on the upper surface of the conductive pattern 262, and an electrode 282 is continuously positioned on the upper surface of the conductive pattern 263. The height adjustment pattern 252 has a thickness substantially the same as the thickness of the conductor pattern 261, and has a configuration substantially the same as the height adjustment pattern 250. In the eighth embodiment, the height adjustment pattern 252 is located at the same height (layer) as the conductor pattern 261 (the first wiring layer WL200B), and is located directly below the layer direction of the conductor pattern 263 (the electrode 282), and Since the lower surface of the insulating layer 271 is made substantially flat, the height positions of the conductor pattern 262 (electrode 281) and the conductor pattern 263 (electrode 282) provided on the insulating layer 271 are substantially the same.

[Manufacturing Method of Multilayer Wiring Board] FIG. 27 is a step diagram showing a manufacturing method of a multilayer wiring board according to an embodiment of the present invention, and FIG. 28 is a step diagram showing steps subsequent to the manufacturing step of FIG. 27. Hereinafter, a manufacturing method of the multilayer wiring board 200 according to the third embodiment will be described as an example.

First, as the substrate 210, a substrate having glass epoxy as a main material having a desired thickness and size is prepared, and a conductor pattern 211 and a height adjustment pattern 250 are formed on the upper surface 210H of the substrate 210 (FIG. 27 (A)) . Examples of the method for forming the conductor pattern 211 include a method of forming a conductive layer on the upper surface 210H of the substrate 210, forming a resist pattern on the conductive layer, and then etching the resist pattern as a photomask. . Examples of the method for forming a conductive layer on the upper surface 210H of the substrate 210 include, for example, a vacuum film formation method such as sputtering, or a plating method (electroless plating method, via seeds formed on the upper surface 210H of the substrate 210). Layer electrolytic plating method, etc.). The resist pattern may be formed by an exposure / development process for a dry film resist or a liquid resist. The height adjustment pattern 250 may be formed in a predetermined region (the region where the height adjustment pattern 250 should be formed) in the upper surface 210H of the substrate 210 after the conductor pattern 211 is formed, or may be formed before the conductor pattern 211 is formed. When the height adjustment pattern 250 includes a conductive material, the height adjustment pattern 250 may be formed at the same time as the conductive pattern 211 is formed. Examples of a method for forming the height-adjusting pattern 250 including a non-conductive material such as a photosensitive resin material include a method of forming a photosensitive resin layer by a spin coating method, and exposing / developing the photosensitive resin layer. In addition, the substrate 210 is not limited to the substrate using glass epoxy as a main material, and a substrate using glass, silicon, or the like as a main material may also be suitably used.

Next, an insulating layer 221 is formed so as to cover the conductor pattern 211 and the height adjustment pattern 250 (FIG. 27 (B)). The insulating layer 221 can be formed by a so-called coating method, that is, an epoxy resin solution or the like is applied by a method such as spin coating, dip coating, spray coating, or bar coating, etc., and dried and then heat-hardened. In this embodiment, the height position of the insulating layer 221 on the conductor pattern 211 and the height position of the insulating layer 221 on the height adjustment pattern 250 are substantially the same. As the resin material constituting the insulating layer 221, a polyimide resin, an acrylic resin, or the like is used in addition to the epoxy resin. In addition, the insulating layer 221 may have a single-layer structure or a multilayer structure of two or more layers.

Next, a through hole 231 ′ penetrating the insulating layer 221 in the thickness direction is formed so that a part of the upper surface of the conductor pattern 211 is exposed (FIG. 27 (C)). The through hole 231 ′ can be formed by, for example, a method such as forming a desired resist pattern on the insulating layer 221, using the resist pattern as a photomask, and performing etching with a desired etching solution.

Next, a conductive material is filled in the through hole 31 ′ to form a via 231, and a conductive pattern 212 and a conductive pattern 213 are formed on the insulating layer 221 (FIG. 27 (D)). The via 231, the conductor pattern 212, and the conductor pattern 213 can be formed in the same manner as the conductor pattern 211 described above. In the formation of the via 231, the conductor pattern 212, and the conductor pattern 213, an alloy containing copper (Cu), nickel (Ni), gold (Au), or the like is suitably used.

Then, an insulating layer 222 is formed so as to cover the conductor pattern 212 and the conductor pattern 213 (FIG. 28 (A)). The insulating layer 222 can be formed by a so-called coating method, that is, an epoxy resin solution or the like is applied by a method such as spin coating, dip coating, spray coating, or bar coating, and then dried and then heat-hardened. The resin material constituting the insulating layer 222 may be the same as the resin material constituting the insulating layer 221, or a different kind of resin material may be used.

Then, a through hole 241 ′ penetrating the insulating layer 222 in a thickness direction is formed so that a part of the upper surface of the conductor pattern 212 is exposed, and is formed in the insulating layer 222 so that a part of the upper surface of the conductor pattern 213 is exposed. A through hole 242 'penetrating in the thickness direction (FIG. 28 (B)). The through hole 241 'and the through hole 242' can be formed by a method substantially the same as the method of forming the through hole 231 '.

Next, the through hole 241 'is filled with a conductive material to form an electrode 241, and the through hole 242' is filled with a conductive material to form an electrode 242 (FIG. 28 (C)). The electrodes 241 and 242 can be formed in the same manner as the conductor patterns 211 to 213 using materials (for example, copper (Cu), nickel (Ni), gold (Au), lead-tin alloy, etc.) constituting the electrodes 241 and 42. Through the above steps, the multilayer wiring substrate 200 having the height positions of the conductor pattern 212 (electrode 241) and the conductor pattern 213 (electrode 242) that are approximately the same can be produced.

<Ninth Embodiment> In this embodiment, a semiconductor device including elements other than the light-emitting element described in the first embodiment will be described.

FIG. 29 is a cross-sectional view of the semiconductor device 500. As shown in FIG. 29, the semiconductor device 500 includes a wafered semiconductor element 600 including a transistor, a high-frequency element 620, an interposer 700, and a package substrate 800. The semiconductor device 600 has a function as a central processing unit (CPU: Central Processing Unit) or a function as a storage device. High-frequency components are passive components corresponding to high frequencies, including inductors, capacitors, and resistance elements. The interposer 700 has a function of transferring the package substrate 800 to the semiconductor element 600 and the high-frequency element 620. The semiconductor element 600 and the high-frequency element 620 are electrically connected to the interposer 700 using a terminal 650. The semiconductor element 600 and the high-frequency element 620 may be sealed with a mold resin. The interposer 700 and the package substrate 800 are connected using terminals 750. The gap between the interposer 700 and the package substrate 800 can be sealed using an underfill resin. The wiring substrate 100 can be used for the interposer 700 and the package substrate 800.

<Tenth Embodiment> In this embodiment, an example in which the wiring board 100 described in the first to eighth embodiments is applied to an electric device will be described.

FIG. 30 and FIG. 31 are diagrams for explaining electric equipment. Semiconductor devices including the wiring board 100 are used in, for example, mobile terminals (mobile phones, smartphones, notebook personal computers, game consoles, etc.), information processing devices (desktop personal computers, servers, car navigation, etc.), households Use electrical equipment (electronic stove, air conditioner, washing machine, refrigerator), automobile and other electrical equipment.

Figure 30 shows a block LED 2000. In the block LED 2000, the light emitting devices 1000 are arranged in a grid pattern, and the light emitting devices 1000 are mounted on the wiring substrate 100. By using the wiring substrate 100 described in the first to eighth embodiments, it is possible to suppress the direction deviation of the light emitting surface of the LED element, and it is difficult to visually confirm the effect of the divided seams, thereby providing a device with good display performance.

Figure 31 (A) shows a smart phone 4000. FIG. 31 (B) shows a portable game machine 5000. Figure 31 (C) shows a notebook personal computer 6000.

Among these electric devices, high-density mounting can be performed by using the wiring substrate 100. Therefore, electrical equipment can be miniaturized and high-performance.

The embodiments described above are described for easy understanding of the present invention and are not intended to limit the present invention. Therefore, the gist is that each element disclosed in the above embodiment also includes all design changes or equivalents that fall within the technical scope of the present invention.

(Modification 1) In the first embodiment of the present invention, the distance from the upper surface 110A of the substrate 110 to the dummy passage portion 143 is shown as compared to the distance DL1 from the upper surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141. The distance DL2 up to the bottom 143D is an example, but it is not limited to this. FIG. 32 is a cross-sectional view of the wiring substrate 100-6. As shown in FIG. 32, even if the distance DL2 is shorter than the distance DL1 in the wiring substrate 100-6, the same effect as that of the wiring substrate 100 can be obtained.

(Modification 2) In the first embodiment of the present invention, an example in which the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 has a convex shape is shown, but it is not limited thereto. FIG. 25 is a cross-sectional view of the wiring substrate 100-7. As shown in FIG. 33, the upper surface of the conductive portion 150-1 and the upper surface of the conductive portion 150-2 of the wiring substrate 100-7 may have recessed portions. The wiring substrate 100-7 can also have the same effects as the wiring substrate 100.

(Modification 3) In the first embodiment of the present invention, the conductive portion 150-2 is not connected to the lower wiring 120. However, the conductive portion 150-2 may be connected to a conductive portion different from the lower wiring 120. 34 is a plan view of the wiring substrate 100-8 and a cross-sectional view between A1-A2 of the wiring substrate 100-8 in FIG. 27. As shown in FIGS. 34 and 35, the wiring substrate 100-8 includes a substrate 110, a lower wiring 120, an insulating layer 130, a via portion 141, a dummy via portion 143, a conductive portion 150-1, a conductive portion 150-2, and an upper wiring. In addition to 160, a conductive portion 122 is provided.

The conductive portion 122 is disposed on the substrate 110 similarly to the lower wiring 120. The conductive portion 122 is disposed so as to overlap the dummy via portion 143 and the conductive portion 150-2. At this time, the distance DL1 from the upper surface 110A of the substrate 110 to the bottom portion 141D of the via portion 141 and the distance DL2 from the upper surface 110A of the substrate 110 to the bottom portion 143D of the dummy via portion 143 may be equal. In the above, the conductive portion 122 is connected to the conductive portion 150-2. In addition, the conductive portion 122 may not have a function as an electrode. At this time, the area 150-2F and the conductive portion 122 of the conductive portion 150-2 provided on the dummy path portion 143 may not be components of the circuit. On the other hand, a region 150-2F above the region 150-2F in the conductive portion 150-2 is connected to the upper wiring 160. At this time, the area 150-2U and the upper wiring 160 may also constitute a part of the circuit.

With the above-mentioned structure, the shapes of the via portion 141, the dummy via portion 143, the conductive portion 150-1, and the conductive portion 150-2 are stable, and the variation in height of the terminals can be reduced similarly to the wiring substrate 100.

(Modification 4) In the first embodiment of the present invention, an example has been described in which the via portion 141 and the dummy via portion 143 are formed by the photolithography method, but the invention is not limited to this. The passage portion 141 and the dummy passage portion 143 may be formed by a laser irradiation method.

In the case of laser irradiation, excimer laser, neodymium-doped yttrium aluminum garnet (Nd: YAG) laser, femtosecond laser, etc. are used in the laser. When an excimer laser is used, light in the ultraviolet region is irradiated. For example, in the case of using xenon chloride in excimer laser, light with a wavelength of 308 nm is irradiated. The apertures of the passage portion 141 and the dummy passage portion 143 are controlled by the irradiation diameter of the laser. At this time, the irradiation diameter of the laser can be set to 5 μm or more and less than 30 μm.

In the above, the output conditions of the laser when the dummy path portion 143 is formed may be smaller than the output conditions of the laser when the via portion 141 is formed.

In addition, when the insulating layer 130 is an inorganic insulating layer, a reactive ion etching method or a wet etching method may be used, or a laser irradiation method and a wet etching method may be used in combination. As the etching solution used for the wet etching method, any one of hydrofluoric acid (HF), nitric acid (HNO ₃ ), and an alkaline solution may be used.

(Modification 5) In the multilayer wiring board 200 of each of the above embodiments, as shown in FIGS. 21 to 26, a form in which a pattern for height adjustment is provided substantially directly below the layered direction of the conductor pattern on the surface layer is depicted, but It is not limited to this form. For example, as long as the height positions of the conductor patterns on the surface layer can be made substantially uniform, it is sufficient if the pattern for height adjustment is positioned below the lamination direction of at least a part of the conductor patterns on the surface layer. That is, even if it is not directly below the lamination direction of the conductor pattern on the surface layer, it can be positioned at a position shifted from the position directly below the lamination direction to the in-plane direction (left and right direction in the figure) of the predetermined layer. Those with height adjustment patterns.

(Modification 6) In the above-mentioned embodiment, a multilayer wiring board having two or three wiring layers has been described as an example, but it is not limited to this embodiment, and it may be one having four or more wiring layers.

90‧‧‧ wiring board

100‧‧‧ wiring board

105‧‧‧External terminal

110‧‧‧ substrate

110A‧‧‧ Top surface

120‧‧‧ Lower wiring

122‧‧‧Conductive Section

130‧‧‧ Insulation

141‧‧‧Access Department

143‧‧‧Virtual Access Department

147‧‧‧seed layer

149‧‧‧resist film

150, 150-1, 150-2‧‧‧ conductive section

150-1F, 150-2F‧‧‧ area

160‧‧‧ Upper wiring

165‧‧‧ Insulation

171‧‧‧Access Department

173‧‧‧Virtual Access Department

180‧‧‧ conductive section

183‧‧‧Conductive section

185‧‧‧ conductive part

200‧‧‧Multilayer wiring substrate

210‧‧‧ substrate

211, 212, 213, 214, 215, 216, 217, 218, 261, 262, 263‧‧‧ conductor pattern

221, 222, 223‧‧‧ Insulation

231, 232, 233‧‧‧ access (inter-layer connection)

241, 242, 281, 282‧‧‧ electrodes

250, 251, 252‧‧‧ height adjustment patterns

300‧‧‧Light-emitting element

310‧‧‧Terminal

320‧‧‧Reflective material

330‧‧‧sealing material

340‧‧‧lens

350‧‧‧Protective member

500‧‧‧semiconductor device

600‧‧‧Semiconductor element

620‧‧‧High-frequency components

650‧‧‧terminal

670‧‧‧semiconductor element

700‧‧‧ Interposer

750‧‧‧terminal

800‧‧‧ package substrate

1000‧‧‧light-emitting device

2000‧‧‧Segment LED

4000‧‧‧ smartphone

5000‧‧‧ Portable game console

6000‧‧‧ Notebook PC

FIG. 1 is a cross-sectional view illustrating a light-emitting device according to an embodiment of the present invention. FIG. 2 is a plan view illustrating a wiring substrate according to an embodiment of the present invention. 3 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. 5 is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present invention. 6 is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present invention. 7 is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present invention. 8 is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present invention. 11 is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 12 is a cross-sectional view illustrating a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 13 is a plan view illustrating a wiring substrate according to an embodiment of the present invention. 14 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 15 is a plan view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 16 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 17 is a plan view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 19 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 20 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 21 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. Fig. 22 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. Fig. 23 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. FIG. 24 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. Fig. 25 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. Fig. 26 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. FIG. 27 is a process chart showing a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 28 is a step diagram showing a method of manufacturing a wiring board according to an embodiment of the present invention, and is a step diagram showing steps subsequent to the step diagram of FIG. 27. FIG. 29 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Fig. 30 is a perspective view of an electric device according to an embodiment of the present invention. Fig. 31 is a perspective view of an electric device according to an embodiment of the present invention. 32 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 33 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 34 is a plan view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 35 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention. FIG. 36 is a cross-sectional view illustrating a conventional wiring board. FIG. 37 is a reference diagram showing a configuration example of a multilayer wiring board that appears as a difference in height positions in the lamination direction of two conductor patterns located on a surface layer.

Claims (22)

A wiring substrate includes: a substrate, an insulating layer on the substrate, a height adjustment portion provided in the insulating layer, a first conductive portion provided on the insulating layer, and a first conductive portion adjacent to the first conductive portion and disposed on the substrate. The insulating layer and the second conductive portion on the height adjustment portion have a height from the upper surface of the substrate to the upper surface of the first conductive portion, and a height from the upper surface of the substrate to the upper surface of the second conductive portion. The height is roughly the same. The wiring substrate according to claim 1, further comprising: a lower wiring provided between the substrate and the insulating layer; a path portion provided in the insulating layer and arranged on the lower wiring; and the height adjusting portion. It is a dummy via portion adjacent to the via portion and provided in the insulating layer. The first conductive portion is disposed on the insulating layer and the via portion, and is electrically connected to the lower wiring. The wiring substrate according to claim 2, wherein the height from the upper surface of the substrate to the bottom of the via portion is different from the height from the upper surface of the substrate to the bottom of the dummy via portion. The wiring substrate according to claim 3, wherein the height from the upper surface of the substrate to the bottom of the dummy via portion is longer than the height from the upper surface of the substrate to the bottom of the via portion. The wiring substrate according to claim 4, wherein a part of the lower wiring is overlapped and separated from the second conductive portion in a cross-sectional view. The wiring substrate according to claim 2, wherein the height from the upper surface of the substrate to the uppermost part of the first conductive portion in a cross-sectional view and the height from the upper surface of the substrate to the second conductive portion The difference in height up to the uppermost part is 1 μm or less. The wiring board according to claim 2, wherein a distance between a center line of the first conductive portion and a center line of the second conductive portion is 10 μm or more and 100 μm or less in a cross-sectional view. The wiring board according to claim 2, wherein a distance between a center line of the first conductive portion and a center line of the second conductive portion is 20 μm or more and 50 μm or less in a cross-sectional view. The wiring board according to claim 2, wherein the diameter of the upper portion of the via portion and the diameter of the upper portion of the dummy via portion are 3 μm or more and 30 μm or less. The wiring board according to claim 2, wherein the diameter of the upper portion of the via portion and the diameter of the upper portion of the dummy via portion are 5 μm or more and 10 μm or less. The wiring board according to claim 2, wherein the upper surface of the first conductive portion and the upper surface of the second conductive portion are curved. The wiring substrate according to claim 2, further comprising: an upper wiring disposed on the insulating layer, and the upper wiring is electrically connected to the second conductive portion. The wiring board according to claim 1, wherein the first conductive portion, the second conductive portion, the height adjustment portion, and the insulating layer are the first to Nth (N is an integer of 2 or more) wiring layers. An interlayer connection portion for electrically connecting at least two of the first to Nth wiring layers to each other is provided as a part of the multilayer wiring layer formed by sequential stacking, and the first to Nth wirings are connected to the insulating layer. The respective wiring layers of the layers are electrically separated. The first conductive portion and the second conductive portion constitute the N-th wiring layer, and the height adjustment portion is disposed below the stacking direction of the second conductive portion and is provided in a separate configuration. On at least a part of the conductive portions of the first to N-1th wiring layers. The wiring substrate according to claim 13, wherein N is an integer of 3 or more, and a plurality of height adjusting portions are provided below a lamination direction of at least a part of the second conductive portion. The wiring board according to claim 13, wherein the height adjustment unit is electrically separated from the first to Nth wiring layers. The wiring board according to any one of claims 13 to 15, further comprising: a plurality of electrodes electrically connected to the Nth wiring layer. A component assembly assembly line substrate includes: the wiring substrate according to claim 16; and at least one electronic component configured to be electrically connected to any one of the plurality of electrodes. A semiconductor device comprising: the wiring substrate according to any one of claims 1 to 12; and a semiconductor element. The semiconductor device according to claim 18, wherein the semiconductor element is a light emitting element. A manufacturing method of a wiring substrate, forming lower wiring on a substrate, forming an insulating layer on the substrate and the lower wiring, forming a via portion on the insulating layer so as to overlap the lower wiring, and adjoining the via portion. A dummy via portion is formed on the insulating layer, a first conductive portion is formed on the via portion and the insulating layer, and a second conductive portion is formed on the dummy via portion and the insulating layer. The method for manufacturing a wiring substrate according to claim 20, wherein the height from the upper surface of the substrate to the bottom of the via portion in a cross-sectional view, and from the upper surface of the substrate to the bottom of the dummy via portion The height so far is different. The method for manufacturing a wiring substrate according to claim 21, wherein the via portion and the dummy via portion are formed by a photolithography method or a laser irradiation method using a halftone mask.