CN205488041U - Packaging structure of copper post bump - Google Patents
Packaging structure of copper post bump Download PDFInfo
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- CN205488041U CN205488041U CN201620042419.8U CN201620042419U CN205488041U CN 205488041 U CN205488041 U CN 205488041U CN 201620042419 U CN201620042419 U CN 201620042419U CN 205488041 U CN205488041 U CN 205488041U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The utility model provides an encapsulation method and the packaging structure of copper post bump, packaging structure includes: the brazing metal dish is makeed on the device, the insulating layer, its position in desiring to prepare copper post bump has the through -hole, redox graphite alkene layer, formed at metal wiring layer surface, the copper post, formed at redox graphite alkene layer surface, the metal barrier layer, formed at copper post surface, the solder bump, formed at metal barrier layer surface. The utility model discloses an adopt electroplating process in brazing metal dish cart face preparation graphite alkene layer, metal level under the ball in the replacement traditional handicraft, then adopt and electroplate preparation copper post and solder metal, saved traditional adoption sputtering technology and photoetching the technology cost has been practiced thrift greatly to the step of etching process preparation copper post. The utility model discloses can electroplate out high -quality copper post on redox graphite alkene. Clearly, the utility model discloses can improve the performance of device, have extensive application prospect in the semiconductor device manufacture field.
Description
Technical field
This utility model belongs to field of semiconductor manufacture, particularly relates to method for packing and the encapsulating structure of a kind of copper pillar bump.
Background technology
Along with the function of integrated circuit is increasingly stronger, performance and the more and more higher and novel integrated circuit of integrated level occur, encapsulation technology plays the most important role in IC products, and ratio shared in the value of whole electronic system is increasing.Meanwhile, along with integrated circuit feature size reaches nanoscale, transistor is to more high density, the development of higher clock frequency, and encapsulation also develops to more highdensity direction.Along with packaging density improves constantly, chip and chip or chip and the narrow pitch electricity interlinkage of base plate for packaging and reliability thereof have become challenge.Traditional lead-free solder Bumping Technology is difficult to meet the further growth requirement of thin space interconnection.Copper pillar bump interconnection technique, with its good electric property, deelectric transferred ability, is just becoming the key technology of chip narrow pitch interconnection of future generation.
Microelectronics Packaging is that semiconductor chip provides the electrical connection being connected to circuit substrate, is protected by fragile sensitive chip simultaneously, it is simple to tests, reprocess, standardization input, output port, and improves the thermal mismatching of semiconductor chip and circuit substrate.In order to comply with development and the environmental conservation decree demand to microelectronics Packaging of silicon-based semiconductor chip technology, microelectronics Packaging interconnection technique (structure and material) is also constantly developing: interconnects from wire bonding to flip-chip, be interconnected to the interconnection of lead-free solder salient point from tin-lead/high kupper solder salient point, be interconnected to copper pillar bump interconnection from solder bump.As chip package interconnection technique of future generation, copper pillar bump interconnection is the most gradually used by increasing chip package designs.
In existing copper pillar bump processing technology, method generally by sputtering prepares copper post and solder metal, but, after sputtering technology, need to remove unnecessary copper and solder metal, normally, expensive photoetching process and etching technics can be used to remove unnecessary copper and solder metal, substantially increase complex process degree and process costs, and be unfavorable for the reduction of cost and the raising of production efficiency.
In view of the above, it is provided that a kind of technique is simple, the method for packing of lower-cost copper pillar bump and encapsulating structure are necessary.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide method for packing and the encapsulating structure of a kind of copper pillar bump, for solving copper pillar bump complex manufacturing technology in prior art, relatively costly problem.
For achieving the above object and other relevant purposes, this utility model provides the method for packing of a kind of copper pillar bump, described method for packing includes: 1) provide a Semiconductor substrate with metal pad, described semiconductor substrate surface is coated with insulating barrier, etches described insulating layer exposing and goes out described metal pad；2) galvanoplastic are used to form graphene oxide layer in described metal pad surface and be reduced into redox graphene layer under hydrazine hydrate steam；3) galvanoplastic are used to form copper post in described redox graphene layer surface；
4) galvanoplastic are used to form metal barrier in described copper post surface；5) use galvanoplastic to form solder metal in described metal barrier surface, and use high temperature reflow processes to form solder bump in described metal barrier surface.
As a kind of preferred version of the method for packing of copper pillar bump of the present utility model, described surface of insulating layer is also formed with polyimide layer.
As a kind of preferred version of the method for packing of copper pillar bump of the present utility model, the material of described metal pad includes Al and copper.
As a kind of preferred version of the method for packing of copper pillar bump of the present utility model, the material of described metal barrier includes nickel.
As a kind of preferred version of the method for packing of copper pillar bump of the present utility model, the upper surface of described redox graphene layer is less than the upper surface of described insulating barrier.
As a kind of preferred version of the method for packing of copper pillar bump of the present utility model, step 2) in, including step: 2-1) use spin coating proceeding in described body structure surface spin coating photoresist to be packaged；2-2) photoetching process is used to open window in the position of copper pillar bump to be prepared；2-3) based on described window, galvanoplastic are used to form graphene oxide layer in metal pad surface and be reduced into redox graphene layer under hydrazine hydrate steam.
Preferably, step 3) in, window based on described photoresist, use galvanoplastic to sequentially form copper post, metal barrier and solder metal in described redox graphene layer surface.
Further, step 4) in, after described solder metal has been electroplated, also include the step removed by described photoresist.
As a kind of preferred version of the method for packing of copper pillar bump of the present utility model, described solder metal includes a kind of in lead, stannum and silver or the alloy comprising any one solder metal above-mentioned.
This utility model also provides for the encapsulating structure of a kind of copper pillar bump, including: there is the Semiconductor substrate of metal pad；Insulating barrier, covers at described semiconductor substrate surface, and exposes described metal pad；Redox graphene layer, is formed at metal pad surface；Copper post, is formed at described redox graphene layer surface；Metal barrier, is formed at described copper post surface；And solder bump, it is formed at described metal barrier surface.
As a kind of preferred version of the encapsulating structure of copper pillar bump of the present utility model, also include polyimide layer, be formed at described surface of insulating layer.
As a kind of preferred version of the encapsulating structure of copper pillar bump of the present utility model, the material of described metal pad includes Al and copper.
As a kind of preferred version of the encapsulating structure of copper pillar bump of the present utility model, the material of described metal barrier includes nickel.
As a kind of preferred version of the encapsulating structure of copper pillar bump of the present utility model, the upper surface of described redox graphene layer is less than the upper surface of described insulating barrier.
As a kind of preferred version of the encapsulating structure of copper pillar bump of the present utility model, the material of described solder bump includes a kind of in lead, stannum and silver or the alloy comprising any one solder metal above-mentioned.
As a kind of preferred version of the encapsulating structure of copper pillar bump of the present utility model, described insulating barrier includes the one in silicon dioxide layer and silicon nitride layer or a combination thereof.
As mentioned above, the method for packing of copper pillar bump of the present utility model and encapsulating structure, have the advantages that this utility model is by using electroplating technology to make graphene layer in metal pad surface, replace the ball lower metal layer (UBM) in traditional handicraft, then plating is used to make copper post and solder metal, save conventionally employed sputtering technology and the step of photo etching process making copper post, be greatly saved process costs.It addition, Graphene has the best electric conductivity, and it is possible to Graphene powers on plates out high-quality copper post.Visible, this utility model processing step is simple, the most cost-effective, and can improve the performance of device, is with a wide range of applications in field of semiconductor manufacture.
Accompanying drawing explanation
Fig. 1～Fig. 9 is shown as the structural representation that each step of method for packing of the copper pillar bump in this utility model embodiment 1 is presented, and wherein, Fig. 9 is shown as the structural representation of the encapsulating structure of copper pillar bump of the present utility model.
Figure 10 is shown as the structural representation of the encapsulating structure of the copper pillar bump in this utility model embodiment 2.
Element numbers explanation
101 silicon substrates
102 metal pads
103 insulating barriers
104 photoresists
105 graphene layers
106 bronze medal posts
107 metal barriers
108 solder metals
109 solder bumps
110 polyimide layers
Detailed description of the invention
Below by way of specific instantiation, embodiment of the present utility model being described, those skilled in the art can be understood other advantages of the present utility model and effect easily by the content disclosed by this specification.This utility model can also be carried out by the most different detailed description of the invention or apply, and the every details in this specification can also carry out various modification or change based on different viewpoints and application under without departing from spirit of the present utility model.
Refer to Fig. 1～Figure 10.It should be noted that, diagram provided in the present embodiment illustrates basic conception of the present utility model the most in a schematic way, component count, shape and size when then only showing the assembly relevant with this utility model rather than implement according to reality in diagram are drawn, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is likely to increasingly complex.
Embodiment 1
As shown in Fig. 1～Fig. 9, the present embodiment provides the method for packing of a kind of copper pillar bump, and described method for packing includes:
As it is shown in figure 1, first carry out step 1), it is provided that having the Semiconductor substrate 101 of metal pad 102, described Semiconductor substrate 101 surface is coated with insulating barrier 103, etches described insulating barrier 103 and exposes described metal pad 102
Specifically, described Semiconductor substrate 101 can be silicon substrate, such as, and the one in monocrystal silicon, polysilicon or non-crystalline silicon, it is also possible to be silicon-on-insulator (Silicon On Insulator, SOI), it is also possible to be silicon Germanium compound.In the present embodiment, described Semiconductor substrate 101 is silicon substrate.It should be noted that already formed with semiconductor structures such as grid, source electrode and drain electrodes in the Semiconductor substrate 101 provided, those semiconductor structures can be electrically connected with the external world by metal interconnection structure and weld pad, thus realizes the various functions of device.Described Semiconductor substrate 101 can contain multiple insulation system, such as fleet plough groove isolation structure (STI) or selective oxidation silicon (LOCOS) etc. further.
As example, the material of described metal pad 102 can comprise but be not limited to copper, aluminum, aluminum bronze, copper alloy or other current-conducting materials, can be used for connecting the integrated circuit in different chip to external structure.Described Semiconductor substrate 101 surface is coated with insulating barrier 103, etches described insulating barrier 103 and exposes described metal pad 102.Described insulating barrier 103 can be silicon nitride, silicon oxynitride, silicon oxide or combinations of the above or other conventional insulant, does not limits at this.
As shown in Figure 2 to 4, then carry out step 2), use galvanoplastic form graphene oxide layer in described metal pad 102 surface and be reduced into redox graphene layer 105 under hydrazine hydrate steam.
Specifically, step 2) in, including step:
As in figure 2 it is shown, first carry out step 2-1), use spin coating proceeding in described body structure surface spin coating photoresist 104 to be packaged；
As it is shown on figure 3, then carry out step 2-2), use photoetching process to open window in the position of copper pillar bump to be prepared；
As shown in Figure 4, then carry out step 2-3), based on described window, use galvanoplastic form graphene oxide layer in described metal welding charging tray 102 surface and carry out reduction formation redox graphene layer 105 under conditions of hydrazine hydrate steam.
As example, the thickness of described redox graphene layer 105 is chosen as: the upper surface of redox graphene layer 105 is less than the upper surface of described insulating barrier 103.As it is shown in figure 5, then carry out step 3), use galvanoplastic to form copper post 106 in described redox graphene layer 105 surface.
As example, window based on described photoresist 104, galvanoplastic are used to form copper post 106 in described redox graphene layer 105 surface.
As shown in Figure 6, then carry out step 4), use galvanoplastic to form metal barrier 107 in described copper post 106 surface.
As example, the material of described metal barrier includes nickel.
As shown in Fig. 7～Fig. 9, finally carry out step 4), use galvanoplastic to form solder metal 108 in described metal barrier 107 surface, and use high temperature reflow processes to form solder bump 109 in described metal barrier 107 surface.
As example, step 4) in, after described solder metal 108 has been electroplated, also include the step removed by described photoresist 104.
As example, described solder metal 108 includes a kind of in lead, stannum and silver or the alloy comprising any one solder metal 108 above-mentioned.In the present embodiment, described solder metal 108 is stannum.
As it is shown in figure 9, the present embodiment also provides for the encapsulating structure of a kind of copper pillar bump, including: having the Semiconductor substrate 101 of metal pad 102, described metal pad is made on semiconductor device the electrical extraction of the existing device of real quasiconductor；Insulating barrier 103, is covered in described metal welding charging tray 102 surface, and described insulating barrier 103 has through hole in the position of copper pillar bump to be prepared, to expose described metal pad 102；Redox graphene layer 105, is formed at described metal welding charging tray 102 surface；Copper post 106, is formed at described redox graphene layer 105 surface；Metal barrier 107, is formed at described copper post 106 surface；And solder bump 109, it is formed at described metal barrier 107 surface.
As example, the material of described metal welding charging tray 102 includes Al and copper.
As example, described metal barrier 107 includes nickel.
As example, the upper surface of described redox graphene layer 105 is less than the upper surface of described insulating barrier 103.
As example, the material of described solder bump 109 includes a kind of in lead, stannum and silver or the alloy comprising any one solder metal above-mentioned.In the present embodiment, the material of described solder bump 109 is stannum.
Embodiment 2
As shown in Figure 10, the present embodiment provides the method for packing of a kind of copper pillar bump, its basic step such as embodiment 1, is in place of the difference with embodiment 1: insulating barrier 103 surface on described Semiconductor substrate 101 surface is also formed with polyimides (PI) layer 110.
As shown in Figure 10, the present embodiment also provides for the encapsulating structure of a kind of copper pillar bump, its basic structure such as embodiment 1, is in place of the difference with embodiment 1: the encapsulating structure of described copper pillar bump also includes polyimides (PI) layer 110, is formed at described insulating barrier 103 surface.
As it has been described above, this utility model provides method for packing and the encapsulating structure of a kind of copper pillar bump, described encapsulating structure includes: metal welding charging tray 102, is made on device the electrical extraction realizing device；Insulating barrier 103, is covered in described metal welding charging tray 102 surface, and described insulating barrier 103 has through hole in the position of copper pillar bump to be prepared；Redox graphene layer 105, is formed at described metal welding charging tray 102 surface；Copper post 106, is formed at described redox graphene layer 105 surface；Metal barrier 107, is formed at described copper post 106 surface；And solder bump 109, it is formed at described metal barrier 107 surface.This utility model makes redox graphene layer 105 by using electroplating technology in brazing metal panel surface, replace the ball lower metal layer (UBM) in traditional handicraft, then plating is used to make copper post 106 and solder metal 108, save conventionally employed sputtering technology and the step of photo etching process making copper post, be greatly saved process costs.Furthermore it is possible to power at redox graphene plate out high-quality copper post.Visible, this utility model processing step is simple, the most cost-effective, and can improve the performance of device, is with a wide range of applications in field of semiconductor manufacture.So, this utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only illustrative principle of the present utility model and effect thereof, not for limiting this utility model.Above-described embodiment all can be modified under spirit and the scope of the present utility model or change by any person skilled in the art.Therefore, art has all equivalence modification or changes that usually intellectual is completed under without departing from the spirit disclosed in this utility model and technological thought such as, must be contained by claim of the present utility model.
Claims (7)
1. the encapsulating structure of a copper pillar bump, it is characterised in that including:
There is the Semiconductor substrate of metal pad；
Insulating barrier, covers at described semiconductor substrate surface, and exposes described metal pad；
Redox graphene layer, is formed at metal pad surface；
Copper post, is formed at described redox graphene layer surface；
Metal barrier, is formed at described copper post surface；
Solder bump, is formed at described metal barrier surface.
The encapsulating structure of copper pillar bump the most according to claim 1, it is characterised in that: also include polyimide layer, be formed at described surface of insulating layer.
The encapsulating structure of copper pillar bump the most according to claim 1, it is characterised in that: described metal pad is Al pad or copper pad.
The encapsulating structure of copper pillar bump the most according to claim 1, it is characterised in that: described metal barrier includes nickel barrier layer.
The encapsulating structure of copper pillar bump the most according to claim 1, it is characterised in that: the upper surface of described redox graphene layer is less than the upper surface of described insulating barrier.
The encapsulating structure of copper pillar bump the most according to claim 1, it is characterised in that: described solder bump includes the one in kupper solder salient point, tin solder salient point and silver solder salient point or comprises any one solder metal alloy solder bump above-mentioned.
The encapsulating structure of copper pillar bump the most according to claim 1, it is characterised in that: described insulating barrier includes the one in silicon dioxide layer and silicon nitride layer or a combination thereof.
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| CN201620042419.8U CN205488041U (en) | 2016-01-15 | 2016-01-15 | Packaging structure of copper post bump |
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| CN201620042419.8U CN205488041U (en) | 2016-01-15 | 2016-01-15 | Packaging structure of copper post bump |
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| CN205488041U true CN205488041U (en) | 2016-08-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448755A (en) * | 2016-01-15 | 2016-03-30 | 中芯长电半导体（江阴）有限公司 | A packaging method for copper column salient points and a packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448755A (en) * | 2016-01-15 | 2016-03-30 | 中芯长电半导体（江阴）有限公司 | A packaging method for copper column salient points and a packaging structure |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |