CN102915978B - Semiconductor package - Google Patents
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- CN102915978B CN102915978B CN201210444097.6A CN201210444097A CN102915978B CN 102915978 B CN102915978 B CN 102915978B CN 201210444097 A CN201210444097 A CN 201210444097A CN 102915978 B CN102915978 B CN 102915978B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A kind of semiconductor package, comprising: chip, is positioned at the first bottom metal layers of described chip first surface; Be positioned at the first columnar electrode in described first bottom metal layers, around described first columnar electrode, expose part first bottom metal layers; Be positioned at first diffusion impervious layer on described first columnar electrode surface; Be positioned at the first soldered ball on described first diffusion impervious layer, described first soldered ball is at least wrapped in the surface of described first columnar electrode top and sidewall; The base plate for packaging be oppositely arranged with the first surface of chip, described flip-chip on described base plate for packaging and the solder terminal of the first soldered ball be positioned on described chip and base plate for packaging interconnect.Because described first soldered ball is formed on described first columnar electrode, the spacing between described chip and base plate for packaging is made to become large, the gap between completely described chip and base plate for packaging can be filled when being conducive to follow-up formation encapsulating material completely, avoid the stability and the reliability that affect chip.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of semiconductor package.
Background technology
Along with electronic product is to the development of miniaturization, in the large scale integrated circuit and very lagre scale integrated circuit (VLSIC) of the consumer electronics field such as notebook computer, panel computer, smart mobile phone, digital camera, more and more higher to the requirement of die size, need the semiconductor package of formation more and more less, more and more thinner.
Please refer to Fig. 1, for the structural representation of a kind of semiconductor package of prior art, specifically comprise: base plate for packaging 10, be positioned at the chip 20 on described base plate for packaging 10, and the first surface 11 of described base plate for packaging 10 is oppositely arranged with the second surface 21 of described chip 20; Be positioned at the soldered ball 22 on the second surface 21 of described chip 20, described soldered ball 22 is connected with circuit structure (not shown) electricity in chip 20, described soldered ball 22 is connected with the conducting terminal 15 of the first surface 11 of base plate for packaging 10, and the circuit in described chip 20 is connected with external circuit by described soldered ball 22, conducting terminal 15; End filler 30 between described chip 20 and base plate for packaging 10; Cover the potting resin material 40 on described chip 20 and base plate for packaging 10 surface.Because the spacing between described chip 20 and base plate for packaging 10 is very little, described spacing equals the height of soldered ball 22, therefore direct when described chip 20 and base plate for packaging 10 surface form potting resin material 40, gap between chip 20 and base plate for packaging 10 can not be filled up by described potting resin material 40, have interior void, easily cause electric charge and stemming moisture accumulation, make chip, base plate for packaging corrodes.Even if first utilize end filler 30 to fill the gap between described chip 20 and base plate for packaging 10, recycling potting resin material 40 covers described chip 20 and base plate for packaging 10 surface, can be little due to gap all too, still cavity be may form between chip 20 and base plate for packaging 10, stability and the reliability of chip affected.
More formation methods about described semiconductor package please refer to the american documentation literature that US publication is US2010/0285637A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor package, can avoid there is cavity between chip and base plate for packaging, affects stability and the reliability of chip.
For solving the problem, technical solution of the present invention provides a kind of semiconductor package, comprising: chip, and described chip has first surface and second surface, is positioned at the first bottom metal layers of described chip first surface; Be positioned at the first columnar electrode in described first bottom metal layers, around described first columnar electrode, expose part first bottom metal layers; Be positioned at first diffusion impervious layer on the first bottom metal layers surface exposed around described first columnar electrode sidewall surfaces, top surface, the first columnar electrode; Be positioned at the first soldered ball on described first diffusion impervious layer, described first soldered ball is at least wrapped in the surface of described first columnar electrode top and sidewall; The base plate for packaging be oppositely arranged with the first surface of chip, described base plate for packaging has solder terminal, the position of described solder terminal is corresponding with the position of the first soldered ball, described flip-chip on described base plate for packaging and the first soldered ball be positioned on described chip and described solder terminal interconnect.
Optionally, also comprise: the second bottom metal layers being positioned at described chip first surface, described second bottom metal layers and the first bottom metal layers electric isolation, be positioned at second columnar electrode on described second bottom metal layers surface, around described second columnar electrode, expose part second bottom metal layers; Be positioned at second diffusion impervious layer on the second bottom metal layers surface exposed around described second columnar electrode sidewall surfaces, top surface, the second columnar electrode; Be positioned at the second soldered ball on described second diffusion impervious layer, described second soldered ball is at least wrapped in the surface of described second columnar electrode top and sidewall; Be positioned at the first heating panel of described base plate for packaging, the position of described first heating panel is corresponding with the position of the second soldered ball, and described second soldered ball and described first heating panel interconnect.
Optionally, described solder terminal is positioned at the submarginal position of base plate for packaging, described first heating panel is positioned at the centre position of base plate for packaging, corresponding, the submarginal position of first surface that described first soldered ball is positioned at described chip, described second soldered ball is positioned at the first surface of chip near middle position.
Optionally, described first soldered ball also covers first diffusion impervious layer on described first bottom metal layers surface, and described second soldered ball also covers second diffusion impervious layer on described second bottom metal layers surface
Optionally, the quantity of described first heating panel is one or more, and the shape of described first heating panel is regular figure or irregular figure.
Optionally, when described first heating panel is polylith, described first heating panel is integrated distribution or dispersion distribution.
Optionally, described base plate for packaging is the one in resin substrate, ceramic substrate, glass substrate, silicon substrate, metal substrate, metal framework and alloy framework.
Optionally, also comprise: the end filler between described chip and package substrates and the potting resin material covering described chip, package substrates surface.
Optionally, also comprise: with the potting resin material covering described chip, package substrates surface between described chip and package substrates.
Optionally, described potting resin material exposes the second surface of described chip.
Optionally, also comprise, with the second heating panel that described chip second surface is bonding, described potting resin material exposes described second heating panel surface.
Optionally, the altitude range of described first columnar electrode and the second columnar electrode is 4 μm ~ 100 μm.
Compared with prior art, the present invention has the following advantages:
Described chip and base plate for packaging are interconnected by the first columnar electrode and the first soldered ball be positioned on described first columnar electrode by the embodiment of the present invention, because described first soldered ball is formed on described first columnar electrode, the spacing between described chip and base plate for packaging is made to become large, the gap between completely described chip and base plate for packaging can be filled when being conducive to follow-up formation potting resin material completely, avoid between chip and base plate for packaging, there is stability and the reliability that cavity can affect chip.
Further, when described chip having the second columnar electrode and being positioned at the second soldered ball on described columnar electrode, described base plate for packaging has the first heating panel, when in described flip-chip to described base plate for packaging, described second soldered ball and the first heating panel interconnect, utilize described second columnar electrode and the second soldered ball that the heat that described chip first surface produces is transferred directly to the first heating panel to dispel the heat, effectively can improve the radiating efficiency of semiconductor package.
Accompanying drawing explanation
Fig. 1 is the structural representation of the semiconductor package of prior art;
Fig. 2 ~ Figure 15 is the structural representation of the semiconductor package of the embodiment of the present invention.
Embodiment
As known from prior art, the size of the soldered ball formed owing to utilizing prior art is less, make the spacing between described chip and base plate for packaging too small, the potting resin material of follow-up formation effectively can not fill the space between described chip and base plate for packaging, interior void is had between described chip and base plate for packaging, easily cause electric charge and stemming moisture accumulation, make chip, base plate for packaging corrodes, affect stability and the reliability of chip.And if improve spacing between described chip and base plate for packaging by increasing the size of soldered ball, described larger-size soldered ball can occupy more chip area, reduce the quantity of packaging pin in chip, be unfavorable for forming the larger encapsulating structure of packaging pin density.
Therefore, the present invention proposes a kind of semiconductor package, comprising: chip, described chip has first surface and second surface, is positioned at the first bottom metal layers of described chip first surface; Be positioned at the first columnar electrode in described first bottom metal layers, around described first columnar electrode, expose part first bottom metal layers; Be positioned at first diffusion impervious layer on the first bottom metal layers surface exposed around described first columnar electrode sidewall surfaces, top surface, the first columnar electrode; Be positioned at the first soldered ball on described first diffusion impervious layer, described first soldered ball is at least wrapped in the surface of described first columnar electrode top and sidewall; The base plate for packaging be oppositely arranged with the first surface of chip, described base plate for packaging has solder terminal, the position of described solder terminal is corresponding with the position of the first soldered ball, described flip-chip on described base plate for packaging and the first soldered ball be positioned on described chip and described solder terminal interconnect.
Described first soldered ball is formed on described first columnar electrode, the spacing between described chip and base plate for packaging is made to become large, the gap between completely described chip and base plate for packaging can be filled when being conducive to follow-up formation encapsulating material completely, avoid between chip and base plate for packaging, there is stability and the reliability that cavity can affect chip; Owing to there is tension force effect between described first soldered ball and first diffusion impervious layer on the first columnar electrode surface, make the size finally forming the first soldered ball less; And described first diffusion impervious layer is not only formed at described first columnar electrode sidewall surfaces and top surface, also be formed in the first bottom metal layers of exposing around the first columnar electrode, described first diffusion impervious layer can improve the adhesion on the first columnar electrode and the first bottom metal layers surface, make described first columnar electrode be not easy to depart from from the first surface of chip, ensure that the stability of semiconductor package.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
Embodiments providing a kind of formation method of semiconductor package, please refer to Fig. 2 to Figure 15, is the structural representation of the forming process of described semiconductor package.
Concrete, please refer to Fig. 2, provide chip 100, described chip 100 has first surface 105 and second surface 106, and the first surface 105 of described chip 100 has pad 101, forms on described chip 100 surface the insulating barrier 110 exposing described pad 101.
Described chip 100 is silicon base, germanium substrate, silicon-on-insulator substrate one wherein, semiconductor device (not shown) and metal interconnect structure (not shown) etc. is formed in described chip 100, described semiconductor device and described pad can be positioned at the surface, the same side of chip, also can be positioned at the not same surface of chip.When described semiconductor device and described pad are positioned at the not same surface of chip, the silicon through hole running through described chip is utilized to be connected with semiconductor device electricity by pad.In the present embodiment, described semiconductor device and pad 101 are positioned at the first surface 105 of described chip, and described semiconductor device is connected with pad 101 electricity, utilize described pad 101 to be electrically connected with external circuit by the circuit structure in chip.
In the present embodiment, the plating seed layer being positioned at bond pad surface of described pad 101 and follow-up formation forms metal interconnecting layer.The first follow-up columnar electrode is formed on described pad.The material of described pad 101 is aluminium, copper, gold or silver-colored etc., and the semiconductor device in described chip utilizes described pad 101 to be connected with external circuit with first columnar electrode, the first soldered ball etc. of follow-up formation.After forming described pad 101, form insulation material layer at described chip 100 and pad 101 surface, and described insulation material layer is etched, expose described pad 101, form insulating barrier 110.Described insulating barrier 110 is silicon oxide layer, silicon nitride layer or polyimide resin layer, benzoxazine resin layer one or more layers stacked structure wherein, with protect IC.In the present embodiment, described insulating barrier 110 is silicon oxide layer.
In other embodiments, passivation layer can also be formed at described surface of insulating layer, described first passivation layer cover part pad.Because the pad of the chip produced from chip manufacturing factory is often comparatively large, make the size of the columnar electrode directly formed on described pad also larger.Therefore can form the first passivation layer again at described surface of insulating layer, described first passivation layer cover part pad, makes the area of the pad exposed reduce, and the size of follow-up formation columnar electrode is reduced, and contributes to forming the high encapsulating structure of closeness.
Please refer to Fig. 3, plating seed layer 120 is formed at described pad 101 and insulating barrier 110 surface, the second mask layer 130 is formed on described plating seed layer 120 surface, in described second mask layer 130, form the second opening 135 running through described second mask layer, described second opening 135 exposes parcel plating Seed Layer 120.
The material of described plating seed layer 120 is the mixture of aluminium, copper, gold, silver wherein one or more, and the technique forming described plating seed layer 120 is sputtering technology or physical gas-phase deposition.When the material of described plating seed layer 120 is aluminium, the technique forming described plating seed layer 120 is sputtering technology, when the material of described plating seed layer 120 is copper, gold, silver one wherein, the technique forming described plating seed layer 120 is physical gas-phase deposition.In the present embodiment, the material of described plating seed layer 120 is copper.
In other embodiments, form underbump metallization (UBM) layer at described pad and surface of insulating layer, described underbump metallization (UBM) layer is used for as plating seed layer.
In the present embodiment, described pad 101 and be positioned at described pad 101, the plating seed layer 120 on insulating barrier 110 surface forms metal interconnecting layer, follow-uply on described plating seed layer, forms the first columnar electrode and the second columnar electrode.
In other embodiments, in order to improve package quality, the spacing of the encapsulation solder joint (i.e. the first soldered ball) of final formation, position need rationally to arrange, the position of encapsulation solder joint often rule is fixing, the such as unified edge near chip, and the limited location of the pad of semiconductor chip connects up in internal circuit, the position arrangement of pad is often different from the arrangement of desirable encapsulation solder joint, therefore needs to utilize interconnection metal layer to be connected with encapsulation solder joint electricity by described pad again.After forming described plating seed layer, form interconnection metal layer again on described plating seed layer surface, follow-up at the described surface of interconnection metal layer again formation the first columnar electrode and the second columnar electrode.Described pad, be positioned at described pad and surface of insulating layer plating seed layer and be positioned at described plating seed layer surface interconnection metal layer again form metal interconnecting layer.Described interconnection metal layer again can be single layer structure or multilayer lamination structure.Described one end of interconnection metal layer is again positioned at the plating seed layer surface on described pad, the other end is positioned at the plating seed layer surface on insulating barrier, and the first columnar electrode of follow-up formation, the second columnar electrode are formed in the surface of interconnection metal layer again on described insulating barrier.In other embodiments, the second columnar electrode of follow-up formation also can form described plating seed layer surface.
Wherein in an embodiment, described in formation, the concrete technology of interconnection metal layer is again: form the 3rd mask layer on described plating seed layer surface, the groove running through described 3rd mask layer is formed in described 3rd mask layer, electroplating technology is utilized to form interconnection metal layer again in described groove, described one end of interconnection metal layer is again positioned at the plating seed layer surface on described pad, and the other end is positioned at the plating seed layer surface on insulating barrier.In other embodiments, also sputtering technology or physical gas-phase deposition can be first adopted to form aluminum metal layer, copper metal layer or aluminum bronze metal level etc. on described plating seed layer surface, then utilize dry etch process to etch described aluminum metal layer, copper metal layer or aluminum bronze metal level etc., form interconnection metal layer again.
The material of described second mask layer 130 is photoresist, silica, silicon nitride, amorphous carbon wherein one or more, and in the present embodiment, the material of described second mask layer 130 is photoresist.Utilize photoetching process in described second mask layer 130, form the second opening 135 running through described second mask layer 130, described second opening 135 is follow-up for the formation of columnar electrode.In the present embodiment, the size of overlooking visual angle of described second opening 135 can be greater than the size of described pad 101, also can be equal to or less than the size of described pad 101.
Please refer to Fig. 4, utilize electroplating technology at described second opening 135(as shown in Figure 3) in formed columnar electrode, described columnar electrode comprises the first columnar electrode 141 and the second columnar electrode 142.
The material of described columnar electrode is copper or other suitable metals.The negative electrode of described plating seed layer 120 with the DC power supply of plating is connected, the anode of DC power supply is arranged in the aqueous solution of copper sulphate, described chip is immersed in copper-bath, then logical direct current, plating seed layer 120 surface exposed at described second opening 135 forms copper post, becomes columnar electrode.The height of described columnar electrode can be identical with the degree of depth of the second opening 135, also can lower than the degree of depth of the second opening 135.
In the present embodiment, in described second opening 135, form columnar electrode and be divided into the first columnar electrode 141 and the second columnar electrode 142.In the final semiconductor package formed, described first columnar electrode is connected with pad electricity, and described first columnar electrode is connected with the solder terminal electricity in base plate for packaging, the circuit in chip is connected with external circuit by described first columnar electrode, solder terminal; Described second columnar electrode and pad, the first columnar electrode electric isolation, and described second columnar electrode is connected with the first heating panel in base plate for packaging, the delivered heat that chip surface produces can be dispelled the heat to the first heating panel by described second columnar electrode, improve the heat-sinking capability of semiconductor package, and can not impact the circuit structure of chip.
In other embodiments, in described second opening, form columnar electrode can be also only the first columnar electrode, and described chip is electrically connected with base plate for packaging by the first soldered ball of described first columnar electrode and follow-up formation.
In the present embodiment, described first columnar electrode 141 is positioned at the submarginal position of first surface 105 of described chip and is positioned on pad 101, and described second columnar electrode 142 is positioned at the first surface 105 of described chip near middle position.In other embodiments, also the first surface of chip can be positioned near middle position, the submarginal position of first surface that described second columnar electrode is positioned at chip by described first columnar electrode; Or also described first columnar electrode and the second columnar electrode interval can arrange, thus can dispel the heat better.Because described first columnar electrode is used for chip to be connected with base plate for packaging electricity, described second columnar electrode is used for the delivered heat of chip surface to dispel the heat to the first heating panel, and therefore the position of described first columnar electrode and the second columnar electrode is separate.
In the present embodiment, the altitude range of described first columnar electrode 141, second columnar electrode 142 is 4 μm ~ 100 μm.Because the first soldered ball of follow-up formation and the second soldered ball are formed on described columnar electrode, the spacing between described chip and base plate for packaging is made to be the total height of columnar electrode and soldered ball, by controlling the height of described columnar electrode, the spacing between chip and base plate for packaging can be regulated, can ensure that the gap between chip and base plate for packaging can be filled full by packed resin material, the thickness of described semiconductor package can be reduced again as much as possible.
In embodiments of the present invention, because the first soldered ball of follow-up formation and the second soldered ball are formed at the top of described columnar electrode and sidewall surfaces, in reflux course, the scolding tin of molten condition has tension force with the diffusion impervious layer surface being positioned at columnar electrode surface, described scolding tin is made to cover described diffusion impervious layer surface more equably, the area of chip shared by the soldered ball on described columnar electrode the is less than area of chip shared by soldered ball that prior art formed, be conducive to improving solder joint closeness, improve packaging density.
Please refer to Fig. 5, remove described second mask layer 130(as shown in Figure 4).
The technique removing described second mask layer 130 is cineration technics.After removing described second mask layer 130, expose described plating seed layer 120.In the present embodiment, the technique forming diffusion impervious layer and soakage layer due to subsequent technique is electroplating technology, retains plating seed layer 120 in this step.
In other embodiments, when the technique of follow-up formation diffusion impervious layer and soakage layer is chemical plating process, part plating seed layer can be removed.The technique removing described plating seed layer comprises: form the 4th mask layer (not shown) on described plating seed layer surface, described 4th mask layer covers described columnar electrode, with described 4th mask layer for mask, utilize the plating seed layer exposed described in wet-etching technology or dry etch process removal, reserve part plating seed layer around described columnar electrode, then removes described 4th mask layer.
In other embodiments, after removing described second mask layer, utilize dry etch process to return etching and remove not by plating seed layer that columnar electrode covers.Because plating seed layer is often very thin, and columnar electrode is very thick, by controlling etch period and etching power, can not affect greatly while the described plating seed layer of removing to described columnar electrode.
Please refer to Fig. 6, the first mask layer 150 is formed on described plating seed layer 120 surface, the position that described first mask layer 150 corresponds to the first columnar electrode 141, second columnar electrode 142 has the first opening 155, the size of described first opening 155 is greater than the size of described first columnar electrode 141, second columnar electrode 142, and has gap between described first opening 155 sidewall and the first columnar electrode 141, second columnar electrode 142 sidewall.
The material of described first mask layer 150 is photoresist, silica, silicon nitride, amorphous carbon wherein one or more, and in the present embodiment, described first mask layer 150 is photoresist layer.Utilize photoetching process in described photoresist layer, form the first opening 155.Owing to there is gap between the sidewall of described first opening 155 and the first columnar electrode 141, second columnar electrode 142 sidewall, make follow-up can below the sidewall of described first columnar electrode, top and the first columnar electrode around expose plating seed layer surface formed the first diffusion impervious layer, the plating seed layer surface exposed around below the sidewall of described second columnar electrode, top and the second columnar electrode forms the second diffusion impervious layer, and the first diffusion impervious layer making to be formed, the section shape of the second diffusion impervious layer are " several " font.In other embodiments, do not expose plating seed layer below described columnar electrode, described columnar electrode covers remaining plating seed layer surface completely, makes follow-uply to form diffusion impervious layer at the sidewall of described columnar electrode and top.
Please refer to Fig. 7, plating seed layer 120 surface exposed at described first columnar electrode 141, second columnar electrode 142 sidewall surfaces, top surface, the first opening 155 forms diffusion impervious layer, wherein, described first columnar electrode 141 surface forms the first diffusion impervious layer 161, and described second columnar electrode 142 surface forms the second diffusion impervious layer 162.
The tin copper interface alloy cpd of ε-phase is formed because the copper in columnar electrode and the tin in soldered ball directly contact to react, easily there is contracting tin or Non-Dewetting in alloy cpd surface, described tin copper interface, thus whole soldered ball is easily come off from the top surface of columnar electrode.Therefore the embodiment of the present invention forms diffusion impervious layer on columnar electrode surface, stops the copper in columnar electrode and the tin in soldered ball to react and forms the tin copper interface alloy cpd of ε-phase.In the present embodiment, described first diffusion impervious layer 161 and the second diffusion impervious layer 162 are nickel dam.Described nickel dam can stop the copper in columnar electrode to be diffused in soldered ball to react with the tin in soldered ball and forms the tin copper interface alloy cpd of ε-phase, make described first soldered ball, the second soldered ball is not easy to come off from columnar electrode top surface, and described nickel dam can avoid columnar electrode surface to be oxidized, and affects conducting resistance.In the present embodiment, the technique forming described first diffusion impervious layer 161, second diffusion impervious layer 162 is chemical plating process.In other embodiments, the technique forming described diffusion impervious layer also can be electroplating technology.
Because chemical plating and plating form coating in metal surface, in the present embodiment, described nickel dam is at described first columnar electrode 141, second columnar electrode 142 sidewall and top surface, plating seed layer 120 surface that first opening 155 exposes is formed, make described first diffusion impervious layer 161, the section shape of the second diffusion impervious layer 162 is " several " font, described diffusion impervious layer be parallel to bottom pad 101 surface and be connected with plating seed layer 120, the section shape of the soakage layer of follow-up formation is made also to be " several " font, make the soldered ball of follow-up formation not only can be positioned at the top surface of described columnar electrode, sidewall surfaces, also can be positioned at the diffusion impervious layer surface on described plating seed layer 120, described soldered ball and diffusion impervious layer three surface contact, improve the adhesion between soldered ball and columnar electrode, suppress soldered ball up and down or double swerve, soldered ball is made to be not easy to come off, improve the reliability of encapsulating structure.And due to the section shape of diffusion impervious layer be " several " font, described diffusion impervious layer be parallel to bottom pad 101 surface and be connected with plating seed layer 120, the upper end of described diffusion impervious layer covers described columnar electrode sidewall and top surface, utilize described diffusion impervious layer can improve adhesion between columnar electrode and plating seed layer 120, described columnar electrode is not easy from plating seed layer 120 sur-face peeling.
Please refer to Fig. 8, form soakage layer on described first diffusion impervious layer 161, second diffusion impervious layer 162 surface, wherein, described first diffusion impervious layer 161 surface forms the first soakage layer 171, and described second diffusion impervious layer 162 surface forms the second soakage layer 172.
In the present embodiment, the material of described first soakage layer 171, second soakage layer 172 at least comprises gold element, silver element, phosphide element or tin element one wherein, such as layer gold, silver layer, tin layers, sn-ag alloy layer, tin-indium alloy layer etc., the technique forming described first soakage layer 171, second soakage layer 172 is chemical plating process or electroplating technology.
Because nickel is also easier to react with the oxygen in air, and the soakage layer with gold element, silver element, phosphide element or tin element is comparatively not easy to react with the oxygen in air, described soakage layer is formed on described nickel dam surface, can avoid forming oxide layer on nickel dam surface, and the soakage layer surface that scolding tin has gold element, silver element, phosphide element or tin element has preferably wettability, the soldered ball formed after making subsequent reflow and columnar electrode have stronger adhesion, and described soldered ball is not easy to peel off.
Gold, silver, copper have lower resistance, described soakage layer in subsequent technique can to a certain degree with soldered ball, the counterdiffusion of diffusion impervious layer phase, formed alloy-layer, described containing gold, silver, copper alloy-layer effectively can reduce the interconnection resistance of encapsulating structure.
In the present embodiment, described first soakage layer 171, second soakage layer 172 is the tin layers that plating is formed, and the electroplate liquid of plating tin layers comprises sodium stannate 40 ~ 60 grams often liter, 10 ~ 16 grams often liter, NaOH, sodium acetate 20 ~ 30 grams often liter, bath temperature is 70 ~ 85 degrees Celsius.Because main component in soldered ball is tin, soldered ball is roughly the same with the composition of described tin layers, and it is lower after the fusing point of scolding tin and tin layers, in follow-up reflux technique, be positioned at after soldered ball on columnar electrode and described tin layers are dissolved and can spread mutually, form an entirety, cross-section structure due to described tin layers is " several " font, the final cross-section structure shape of described soldered ball is also " several " font, described soldered ball is wrapped in described columnar electrode top surface, soakage layer surface on the surface of sidewall and described plating seed layer, described soldered ball is not easy shake, improve the reliability of soldered ball.
In other embodiments, also can not form described soakage layer, form soldered ball on described diffusion impervious layer surface.
Please refer to Fig. 9, remove described first mask layer 150(and please refer to Fig. 8), Fig. 8 be please refer to the described plating seed layer 120(exposed) etch, form the first bottom metal layers 121 and the second bottom metal layers 122.
In the present embodiment, described metal interconnecting layer comprises pad 101 and is positioned at the plating seed layer 120 on described pad 101, insulating barrier 110 surface, after etching described plating seed layer 120, described metal interconnecting layer is divided into the first bottom metal layers 121 and the second bottom metal layers 122.Described first bottom metal layers 121 comprises pad 101(and please refer to Fig. 8) and the parcel plating Seed Layer 120(that is connected with pad electricity please refer to Fig. 8), and described first columnar electrode 141 is positioned at described first bottom metal layers 121 surface.Described second bottom metal layers 122 comprises the parcel plating Seed Layer 120 with pad 101 electric isolation, and described second columnar electrode 142 is positioned at described second bottom metal layers 122 surface.
In other embodiments, when described metal interconnecting layer comprises pad, is positioned at the plating seed layer of described pad and surface of insulating layer and is positioned at the interconnection metal layer again on described plating seed layer surface, etching removes part interconnection metal layer and parcel plating Seed Layer again, and described metal interconnecting layer is divided into the first bottom metal layers and the second bottom metal layers.Described first bottom metal layers comprises pad, be positioned at the parcel plating Seed Layer of pad and surface of insulating layer and be positioned at described parcel plating Seed Layer surface and the interconnection metal layer is again connected with pad electricity, and described first columnar electrode to be positioned at described first bottom metal layers surperficial.Described second bottom metal layers comprises and the parcel plating Seed Layer of pad electric isolation and the interconnection metal layer being again positioned at described parcel plating Seed Layer surface, and described second columnar electrode is positioned at described second bottom metal layers surface.
The technique removing described first mask layer 150 is cineration technics.
The plating seed layer exposed described in removal, again wiring metal layer process be: described plating seed layer or again interconnection metal layer surface formed the 5th mask layer (not shown), described 5th mask layer covers described first columnar electrode and the second columnar electrode, with described 5th mask layer for mask, utilize the plating seed layer, the again interconnection metal layer that expose described in wet-etching technology or dry etch process removal, then remove described 5th mask layer.In other embodiments, the technique of the plating seed layer exposed described in removal, again interconnection metal layer is: after removing described first mask layer, utilizes dry etch process to return etching and removes not by plating seed layer that columnar electrode covers.Because plating seed layer is often very thin, and diffusion impervious layer on columnar electrode or soakage layer thicker, by controlling etch period and etching power, can not affect greatly described diffusion impervious layer or soakage layer while the described plating seed layer of removing.
In other embodiments, after etching removes part plating seed layer, can also at described insulating barrier and interconnection metal layer surface formation passivation layer again, described passivation layer exposes described columnar electrode, utilize described passivation layer by described chip and extraneous electric insulation, steam insulate.The material of described passivation layer is silicon oxide layer, silicon nitride, silicon oxynitride layer, polyimides, epoxy resin, phenolic resins, benzoxazine resin wherein one or more.In other embodiments, also first can form soldered ball, then form described passivation layer.
Please refer to Figure 10, soakage layer surface on described columnar electrode forms soldered ball, wherein, the first soakage layer 171 surface on described first columnar electrode 141 forms the first soldered ball 191, and the second soakage layer 172 surface on described second columnar electrode 142 forms the second soldered ball 192.
Form described soldered ball first soldered ball 191, the technique of the second soldered ball 192 comprises solder(ing) paste formation process and reflow soldering process two steps, solder(ing) paste formation process is first utilized solder(ing) paste to be formed at described first columnar electrode 141, second columnar electrode 142 surface, described solder(ing) paste refluxes by recycling reflux technique, the first soldered ball 191 formed is wrapped in and is positioned at described first columnar electrode 141 top, the first soakage layer 171 surface on the surface of sidewall and plating seed layer, second soldered ball 192 is wrapped in and is positioned at described second columnar electrode 142 top, the second soakage layer 172 surface on the surface of sidewall and plating seed layer.Wherein, described solder is tin, tin lead mixture or other ashbury metal etc., solder(ing) paste formation process comprises screen painting tin cream, spot welding forms tin ball, chemical plating forms tin layers, plating forms tin layers etc., and reflow soldering process comprises ultrasonic wave reflow soldering process, hot air type reflow soldering process, infrared ray reflow soldering process, laser reflow Welding, gas phase reflow soldering process etc.Described solder(ing) paste formation process and reflow soldering process two steps are the known technology of those skilled in the art, and therefore not to repeat here.
Because the surface energy of described soakage layer is larger, wettability is better, in reflux technique, scolding tin not only can be positioned at the top of described columnar electrode, also can flow to sidewall and the sidewall bottom of described columnar electrode, and by controlling the amount of described solder(ing) paste, first soakage layer 171 that described first soldered ball 191 can also be made to cover on plating seed layer is surperficial, described second soldered ball 192 covers the second soakage layer 172 surface on plating seed layer.Because the soldered ball of the embodiment of the present invention and the contact-making surface of columnar electrode at least comprise top planes and sidewall cambered surface, when external force is stirred described soldered ball 192, soldered ball is not easy from columnar electrode sur-face peeling.
In other embodiments, before on chip package to base plate for packaging, also need described chip to carry out thinning, cutting and be divided into the independently technique such as chip unit.
Please refer to Figure 11, base plate for packaging 200 is provided, described base plate for packaging 200 has solder terminal 210 and the first heating panel 220, the position of described solder terminal 210 is corresponding with the position of the first soldered ball 191, the position of described first heating panel 220 is corresponding with the position of described second soldered ball 192, by the upside-down mounting of described chip 100 on described base plate for packaging 200, the first soldered ball 191 be positioned on described chip 100 interconnects with described solder terminal 210, and the second soldered ball 192 be positioned on described chip 100 interconnects with described first heating panel 220.
Described base plate for packaging 200 corresponding with chip 100, in the present embodiment, because described chip 100 has the first columnar electrode 141 and the second columnar electrode 142, described base plate for packaging 200 correspondence has solder terminal 210 and the first heating panel 220.The material of described first heating panel 220 is the metal material that heat dispersion is good, such as copper, aluminium etc.The submarginal position of first surface that described first soldered ball is positioned at described chip, described second soldered ball is positioned at the first surface of chip near middle position, corresponding, described solder terminal is positioned at the submarginal position of base plate for packaging, and described first heating panel is positioned at the centre position of base plate for packaging.In other embodiments, the position of described solder terminal and the first heating panel also can be arranged corresponding to the first soldered ball of chip and the second soldered ball.
The quantity of described first heating panel 220 is one or more.In the present embodiment, described first heating panel 220 is positioned at the middle part of described base plate for packaging 200 and several the second soldered balls 192 are all bonded on same first heating panel 220, in other embodiments, but also one or several second soldered ball corresponds to first heating panel, utilizes described first heating panel to dispel the heat.Pyrotoxin due to chip 100 is positioned at the first surface 105 being covered with circuit structure, and the packed resin material parcel of the chip of prior art, radiating effect is not good, the embodiment of the present invention utilizes described second columnar electrode 142 and the second soldered ball 192 transfer of heat that described first surface 105 produces to be dispelled the heat to the first heating panel, effectively can improve radiating efficiency.
The shape of described first heating panel 220 is regular figure, and such as square, rectangle, triangle etc., also can be irregular figure.In order to improve heat-sinking capability, first heating panel 220 can be arranged in the position not being formed with arbitrarily solder terminal 210, therefore, described first heating panel 220 can be integrated distribution and base plate for packaging centre position or marginal position, also can be dispersion distribution, described first heating panel 220 and solder terminal 210 interval be arranged.
In other embodiments, because the height of described columnar electrode is comparatively large, if the negligible amounts of described first columnar electrode, anti-extrusion ability is lower, and the first columnar electrode may be caused to occur bending and deformation.Therefore by increasing the quantity of described columnar electrode, and part there is no need for the columnar electrode of circuit connection as the second columnar electrode, can increase the anti-extrusion ability in chip package and transportation, avoids columnar electrode to occur bending and deformation or rupture.
Described base plate for packaging 200 is the one in resin substrate, ceramic substrate, glass substrate, silicon substrate, metal substrate, metal framework and alloy framework.
In the present embodiment, described base plate for packaging 200 is metal framework.In the present embodiment, described solder terminal 210 and the first heating panel 220 are positioned at described base plate for packaging 200 and run through described base plate for packaging 200, described be positioned at the first surface 201 of base plate for packaging 200 solder terminal 210 surface and the first heating panel 220 surface interconnect respectively at the first soldered ball 191 and the second soldered ball 192, follow-up described semiconductor package is mounted on pcb board time, utilize be positioned at the second surface 202 of base plate for packaging 200 solder terminal 210 surface with pcb board on interconnected.Described semiconductor package is not owing to needing additionally to form pin, and it is less that attachment occupies the area ratio conventional package of pcb board, and the aspect ratio conventional package of encapsulating structure is lower, makes the final electronic product formed can be more and more thinner.
In other embodiments, described base plate for packaging also can not have the first heating panel, corresponding, described chip does not have the first columnar electrode, utilizes described first columnar electrode to be connected with the solder terminal of base plate for packaging by described chip with the first soldered ball.
In other embodiments, the solder terminal of described base plate for packaging also can be positioned at the first surface of described base plate for packaging, the first surface of described base plate for packaging also has the pin be electrically connected with described solder terminal, utilizes described pin to be connected with pcb board by base plate for packaging.
Please refer to Figure 12, between described chip 100 and base plate for packaging 200, form potting resin material 300 with described chip 100 surface, base plate for packaging 200 surface.
In the present embodiment, because the spacing between described chip 100 and base plate for packaging 200 is larger, traditional potting resin material 300 can be utilized directly to fill the gap between described chip 100 and base plate for packaging 200 and cover described chip 100 surface, base plate for packaging 200 surface, only need a step plastic package process, technique is simple, and cost is lower.In the present embodiment, described potting resin material 300 material is epoxy resin.In other embodiments, described potting resin material can also be other suitable resin materials for semiconductor packages.
In other embodiments, first can also fill filler of the full end between described chip and base plate for packaging, then form potting resin material at described chip and base plate for packaging surface.Filler of the described end is liquid siliceous epoxide resin material, and making does not have space between described chip and base plate for packaging, ensure that the reliability of chip.
In other embodiments, please refer to Figure 13, described base plate for packaging 200 can also have opening 205, described opening 205 is in the shape of falling T, opening size near base plate for packaging first surface 201 is less, and the opening size being positioned at base plate for packaging second surface 202 is comparatively large, and fills full potting resin material or end filler in described opening 205, make described potting resin material or end filler be not easy to peel off from base plate for packaging 200, thus chip 100 is not easy to peel off from base plate for packaging.
In the present embodiment, described potting resin material 300 covers the second surface 106 of described chip 100.In other embodiments, please refer to Figure 14, described potting resin material 300 exposes the second surface 106 of described chip 100, only covers sidewall surfaces and base plate for packaging 200 surface of described chip 100, utilize the second surface of described chip to dispel the heat, be conducive to improving radiating effect.
In other embodiments, please refer to Figure 15, silver slurry thermal paste can also be utilized to be pasted with the second heating panel 400 at the second surface 106 of described chip 100, and the area due to described second heating panel 400 is greater than the area of described chip 100, is conducive to the heat-sinking capability improving semiconductor structure.The material of described second heating panel 400 is the metal material that heat dispersion is good, such as copper, aluminium etc.And described chip is by described second heating panel and potting resin material and external insulation, extraneous electric charge can be avoided, impact that the electrical property the subject of knowledge and the object of knowledge of steam on chip causes.
According to above-mentioned formation method, the embodiment of the present invention additionally provides semiconductor package, and wherein a kind of semiconductor package please refer to Figure 12, comprising: chip 100, and described chip 100 has first surface 105 and second surface 106; Be positioned at the first bottom metal layers 121 of described chip first surface 105, be positioned at the first columnar electrode 141 in described first bottom metal layers 121, expose part first bottom metal layers 121 around described first columnar electrode 141, be positioned at first diffusion impervious layer 161 on the first bottom metal layers 121 surface exposed around described first columnar electrode 141 sidewall surfaces, top surface, the first columnar electrode 141; Be positioned at first soakage layer 171 on described first diffusion impervious layer 161 surface, be positioned at the first soldered ball 191 on described first soakage layer 171, described first soldered ball 191 be wrapped in described first columnar electrode 141 top, the first soakage layer 171 surface in the first bottom metal layers 121 that the surface and being positioned at of sidewall exposes around the first columnar electrode 141; Be positioned at the second bottom metal layers 122 of described chip first surface 105, be positioned at the second columnar electrode 142 in described second bottom metal layers 122, expose part second bottom metal layers 122 around described second columnar electrode 142, be positioned at second diffusion impervious layer 162 on the second bottom metal layers 122 surface exposed around described second columnar electrode 142 sidewall surfaces, top surface, the second columnar electrode 142; Be positioned at second soakage layer 172 on described second diffusion impervious layer 162 surface, be positioned at the second soldered ball 192 on described second soakage layer 172, described second soldered ball 192 be wrapped in described second columnar electrode 142 top, the second soakage layer 172 surface in the second bottom metal layers 122 that the surface and being positioned at of sidewall exposes around the second columnar electrode 142; The base plate for packaging 200 be oppositely arranged with the first surface 105 of described chip 100, described base plate for packaging 200 has solder terminal 210 and the first heating panel 220, the position of described solder terminal 210 is corresponding with the position of the first soldered ball 191, the position of described first heating panel 220 is corresponding with the position of the second soldered ball 192, the upside-down mounting of described chip 100 is on described base plate for packaging 200, the first soldered ball 191 be positioned on described chip 100 interconnects with described solder terminal 210, and the second soldered ball 192 be positioned on described chip 100 interconnects with described first heating panel 220; With the potting resin material 300 covering described chip 100, package substrates 200 surface between described chip 100 and package substrates 200.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (18)
1. a semiconductor package, is characterized in that, comprising: chip, and described chip has first surface and second surface, is positioned at the first bottom metal layers of described chip first surface; Be positioned at the first columnar electrode in described first bottom metal layers, around described first columnar electrode, expose part first bottom metal layers; Be positioned at first diffusion impervious layer on the first bottom metal layers surface exposed around the whole surface of described first columnar electrode sidewall, top surface, the first columnar electrode, the cross-section structure of described first diffusion impervious layer is " several " font; Be positioned at first soakage layer on described first diffusion impervious layer surface, the cross-section structure of described first soakage layer is " several " font; Be positioned at cross-section structure for " several " font the first soakage layer surface on the first soldered ball, described first soldered ball is at least wrapped in the surface of described first columnar electrode top and sidewall; The base plate for packaging be oppositely arranged with the first surface of chip, described base plate for packaging has solder terminal, the position of described solder terminal is corresponding with the position of the first soldered ball, described flip-chip on described base plate for packaging and the first soldered ball be positioned on described chip and described solder terminal interconnect.
2. semiconductor package as claimed in claim 1, it is characterized in that, also comprise: the second bottom metal layers being positioned at described chip first surface, described second bottom metal layers and the first bottom metal layers electric isolation, be positioned at second columnar electrode on described second bottom metal layers surface, around described second columnar electrode, expose part second bottom metal layers; Be positioned at second diffusion impervious layer on the second bottom metal layers surface exposed around described second columnar electrode sidewall surfaces, top surface, the second columnar electrode; Be positioned at the second soldered ball on described second diffusion impervious layer, described second soldered ball is at least wrapped in the surface of described second columnar electrode top and sidewall; Be positioned at the first heating panel of described base plate for packaging, the position of described first heating panel is corresponding with the position of the second soldered ball, and described second soldered ball and described first heating panel interconnect.
3. semiconductor package as claimed in claim 2, it is characterized in that, described solder terminal is positioned at the submarginal position of base plate for packaging, described first heating panel is positioned at the centre position of base plate for packaging, corresponding, the submarginal position of first surface that described first soldered ball is positioned at described chip, described second soldered ball is positioned at the first surface of chip near middle position.
4. semiconductor package as claimed in claim 2, it is characterized in that, the quantity of described first heating panel is one or more, and the shape of described first heating panel is regular figure or irregular figure.
5. semiconductor package as claimed in claim 4, is characterized in that, when described first heating panel is polylith, described first heating panel is integrated distribution or dispersion distribution.
6. semiconductor package as claimed in claim 1, it is characterized in that, described base plate for packaging is the one in resin substrate, ceramic substrate, glass substrate, metal substrate and metal framework.
7. semiconductor package as claimed in claim 1, is characterized in that, described base plate for packaging is the one in silicon substrate and alloy framework.
8. semiconductor package as claimed in claim 2, it is characterized in that, described first soldered ball also covers first diffusion impervious layer on described first bottom metal layers surface, and described second soldered ball also covers second diffusion impervious layer on described second bottom metal layers surface.
9. semiconductor package as claimed in claim 2, it is characterized in that, described first diffusion impervious layer, the second diffusion impervious layer are nickel dam.
10. semiconductor package as claimed in claim 2, is characterized in that, also comprise, be positioned at first soakage layer on described first diffusion impervious layer surface, and described first soldered ball is formed at described first soakage layer surface; Be positioned at second soakage layer on described second diffusion impervious layer surface, described second soldered ball is formed at described second soakage layer surface.
11. semiconductor packages as claimed in claim 10, is characterized in that, the material of described first soakage layer, the second soakage layer at least comprises the one in gold element, silver element, phosphide element and tin element.
12. semiconductor packages as claimed in claim 2, is characterized in that, described first bottom metal layers comprises pad and is positioned at the plating seed layer of described bond pad surface, and described first bottom metal layers is formed with the first columnar electrode; Described second bottom metal layers comprises the plating seed layer being positioned at described chip first surface, and described second bottom metal layers is formed with the second columnar electrode.
13. semiconductor packages as claimed in claim 2, it is characterized in that, described first bottom metal layers comprises pad, is positioned at described bond pad surface and the plating seed layer be electrically connected and the interconnection metal layer being again positioned at described plating seed layer surface, and described first bottom metal layers is formed with the first columnar electrode; Described second bottom metal layers is the plating seed layer being positioned at described chip first surface, or comprise the plating seed layer being positioned at described chip first surface and the interconnection metal layer being again positioned at described plating seed layer surface, described second bottom metal layers is formed with the second columnar electrode.
14. semiconductor packages as claimed in claim 1, is characterized in that, also comprise: the end filler between described chip and base plate for packaging and the potting resin material covering described chip, base plate for packaging surface.
15. semiconductor packages as claimed in claim 1, is characterized in that, also comprise: with the potting resin material covering described chip, base plate for packaging surface between described chip and base plate for packaging.
16. semiconductor packages as described in claims 14 or 15, it is characterized in that, described potting resin material exposes the second surface of described chip.
17. semiconductor packages as described in claims 14 or 15, is characterized in that, also comprise, and with the second heating panel that described chip second surface is bonding, described potting resin material exposes described second heating panel surface.
18. semiconductor packages as claimed in claim 2, is characterized in that, the altitude range of described first columnar electrode and the second columnar electrode is 4 μm ~ 100 μm.
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| US14/074,687 US9293338B2 (en) | 2012-11-08 | 2013-11-07 | Semiconductor packaging structure and method |
| US15/014,929 US9431325B2 (en) | 2012-11-08 | 2016-02-03 | Semiconductor packaging structure |
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| CN103413769B (en) * | 2013-08-27 | 2016-02-24 | 南通富士通微电子股份有限公司 | Wafer-level chip size package method |
| CN104465571A (en) * | 2014-12-16 | 2015-03-25 | 南通富士通微电子股份有限公司 | Wafer packaging structure |
| CN107993994B (en) * | 2017-12-29 | 2023-07-25 | 长鑫存储技术有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| US11024801B2 (en) * | 2018-06-27 | 2021-06-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Diffusion layer for magnetic tunnel junctions |
| CN112885802A (en) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN114823573B (en) * | 2022-06-24 | 2022-09-09 | 威海市泓淋电力技术股份有限公司 | Heat dissipation type packaging structure and forming method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5726079A (en) * | 1996-06-19 | 1998-03-10 | International Business Machines Corporation | Thermally enhanced flip chip package and method of forming |
| CN1697148A (en) * | 2004-05-12 | 2005-11-16 | 富士通株式会社 | Semiconductor device and method of manufacturing the semiconductor device |
| CN1768434A (en) * | 2003-03-28 | 2006-05-03 | 吉尔科有限公司 | LED power package |
| CN102237316A (en) * | 2010-04-22 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit element and forming method of bumping block structure |
| CN102270590A (en) * | 2011-09-01 | 2011-12-07 | 苏州晶方半导体科技股份有限公司 | Wafer level package structure and method |
| CN202917468U (en) * | 2012-11-08 | 2013-05-01 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
Family Cites Families (2)
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5726079A (en) * | 1996-06-19 | 1998-03-10 | International Business Machines Corporation | Thermally enhanced flip chip package and method of forming |
| CN1768434A (en) * | 2003-03-28 | 2006-05-03 | 吉尔科有限公司 | LED power package |
| CN1697148A (en) * | 2004-05-12 | 2005-11-16 | 富士通株式会社 | Semiconductor device and method of manufacturing the semiconductor device |
| CN102237316A (en) * | 2010-04-22 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit element and forming method of bumping block structure |
| CN102270590A (en) * | 2011-09-01 | 2011-12-07 | 苏州晶方半导体科技股份有限公司 | Wafer level package structure and method |
| CN202917468U (en) * | 2012-11-08 | 2013-05-01 | 南通富士通微电子股份有限公司 | Semiconductor packaging structure |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |