CN107993994B - Semiconductor packaging structure and manufacturing method thereof - Google Patents

Semiconductor packaging structure and manufacturing method thereof Download PDF

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Publication number
CN107993994B
CN107993994B CN201711470750.5A CN201711470750A CN107993994B CN 107993994 B CN107993994 B CN 107993994B CN 201711470750 A CN201711470750 A CN 201711470750A CN 107993994 B CN107993994 B CN 107993994B
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chip
mounting surface
cavity
pad
fan
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CN107993994A (en
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请求不公布姓名
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

The application relates to the field of semiconductor packaging, and discloses a semiconductor packaging structure and a manufacturing method thereof. The structure comprises: a parallel gap is formed between the first chip and the second chip which are arranged side by side; the packaging cover is provided with a third mounting surface, a first cavity and a second cavity, wherein the first cavity and the second cavity are recessed from the third mounting surface, the first chip is accommodated in the first cavity, the second chip is accommodated in the second cavity, a first gap is formed between the first cavity and the first chip, and a second gap is formed between the second cavity and the second chip; a heat-conducting medium filled in the first gap and the second gap; the rewiring layer comprises a first fan-in bonding pad, a second fan-in bonding pad and an external bonding pad, wherein the first fan-in bonding pad is connected to a first contact and connected to the corresponding external bonding pad through a first fan-out line, the second fan-in bonding pad is connected to a second contact and connected to the corresponding external bonding pad through a second fan-out line, and the rewiring layer further comprises at least one inner interconnection line which is connected with the first fan-in bonding pad and the second fan-in bonding pad.

Description

Semiconductor packaging structure and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor packaging, and in particular, to a semiconductor packaging structure and a method for manufacturing the same.
Background
Three-dimensional packages (3D) are packages in which two or more dice are interconnected by stacking in a direction perpendicular to the surface of the chip. The System-In-Package (SIP) packaging technology is high-level, and has small space occupation and stable electrical performance. Currently, advanced 3D integration is a system-in-a-package architecture based on wafer-level packaging, which contains a stack of various devices inside and is interconnected in the vertical direction (Z-direction) Via Through-silicon vias (TSVs). In addition, in packaging technology, efforts are made to shorten the signal transmission distance between the packaged chip and the solder balls on the substrate and to reduce the form factor (form factor), while also requiring good heat dissipation from the chip.
Disclosure of Invention
The present disclosure provides a semiconductor package structure and a method for manufacturing the same, which has better heat dissipation effect.
In order to achieve the above object, in one aspect of the present application, there is provided a semiconductor package structure comprising: the first chip is provided with a first mounting surface and a plurality of first joints exposed on the first mounting surface, the second chip is provided with a second mounting surface and a plurality of second joints exposed on the second mounting surface, and a parallel gap is formed between the first chip and the second chip; a package cover having a third mounting surface, a first cavity and a second cavity recessed from the third mounting surface, the third mounting surface being aligned with the first mounting surface and the second mounting surface, the first chip being accommodated in the first cavity, the second chip being accommodated in the second cavity, a first gap being provided between the first cavity and the first chip, and a second gap being provided between the second cavity and the second chip; a heat transfer medium filled in the first gap and the second gap, the heat transfer medium having a filling surface connecting the first mounting surface, the second mounting surface, and the third mounting surface such that the first mounting surface, the second mounting surface, and the third mounting surface are formed on a continuous surface; the rewiring layer is formed on the continuous surface and comprises a first fan-in bonding pad, a second fan-in bonding pad and an external bonding pad, the first fan-in bonding pad is connected to the first connecting point and is connected to the corresponding external bonding pad through a first fan-out line, the second fan-in bonding pad is connected to the second connecting point and is connected to the corresponding external bonding pad through a second fan-out line, and the rewiring layer further comprises at least one inner interconnection line and is connected with the first fan-in bonding pad and the second fan-in bonding pad.
Optionally, the packaging cover further has a channel, which communicates the first cavity and the second cavity, and the heat conducting medium is also filled in the channel.
Optionally, the semiconductor package structure may further include a first solder ball implanted on the external pad.
Optionally, the semiconductor package structure may further include: a carrier substrate having a first surface and a second surface, the carrier substrate comprising an interconnect pad located on the first surface, a terminal pad located on the second surface, and a trace electrically connecting the interconnect pad and the terminal pad, the interconnect pad being bonded to the first solder ball; and a second solder ball implanted on the terminal pad.
Optionally, the packaging cover further has a first opening communicating with the first cavity and a second opening communicating with the second cavity, so as to fill in the heat conducting medium.
Alternatively, the shape of the first opening or the second opening may include any one of an ellipse, a circle, a square, and a prism.
Optionally, any one of the first fan-out line, the second fan-out line, and the internal interconnection line has a line width/line spacing of less than 15 microns.
Alternatively, the material of the encapsulation cover may comprise silicon.
Optionally, the package cover is formed by etching and singulating the silicon wafer.
Optionally, the first gap and the second gap have a width ranging from 10 micrometers to 100 micrometers such that the first chip and the second chip do not directly contact the package cover.
In another aspect of the present application, a method for fabricating a semiconductor package is provided, the method may include: providing a carrier plate, arranging a first chip and a second chip on the carrier plate side by side, wherein the first chip is provided with a first mounting surface and a plurality of first joints exposed on the first mounting surface, the second chip is provided with a second mounting surface and a plurality of second joints exposed on the second mounting surface, a parallel gap is formed between the first chip and the second chip, and the first mounting surface and the second mounting surface are attached to the carrier plate; providing a packaging cover, wherein the packaging cover is provided with a third mounting surface, and a first cavity and a second cavity which are recessed by the third mounting surface; the packaging cover is covered on the first chip and the second chip, the third mounting surface is attached to the carrier plate, the third mounting surface is aligned to the first mounting surface and the second mounting surface, the first chip is accommodated in the first cavity, the second chip is accommodated in the second cavity, a first gap is reserved between the first cavity and the first chip, and a second gap is reserved between the second cavity and the second chip; filling a heat transfer medium in the first gap and the second gap, the heat transfer medium having a filling surface connecting the first mounting surface, the second mounting surface, and the third mounting surface such that the first mounting surface, the second mounting surface, and the third mounting surface are formed on a continuous surface; separating the carrier plate; forming a rewiring layer on the continuous surface, the rewiring layer may include a first fan-in pad, a second fan-in pad, and an external pad, the first fan-in pad being bonded to the first contact and connected to the corresponding external pad via a first fan-out line, the second fan-in pad being bonded to the second contact and connected to the corresponding external pad via a second fan-out line, the rewiring layer may further include at least one internal interconnect line connecting the first fan-in pad and the second fan-in pad; and singulating the package caps to make a plurality of semiconductor package structures, each of which may include the first chip and the second chip.
Optionally, the method may further comprise implanting first solder balls on the external bond pads prior to singulating the package cover.
Optionally, the method may further include providing a carrier substrate having a first surface and a second surface, the carrier substrate including interconnect pads on the first surface, terminal pads on the second surface, and wires electrically connecting the interconnect pads and the terminal pads; bonding the interconnection pad with the first solder ball; and implanting a second solder ball on the terminal pad.
Optionally, the packaging cover further has a channel communicating the first cavity and the second cavity; when the heat-conducting medium is filled in the first gap and the second gap, the heat-conducting medium is also filled in the channel.
Optionally, the material of the encapsulation cover comprises silicon.
Optionally, in the step of covering the package cover, a width of the first gap and the second gap ranges from 10 micrometers to 100 micrometers, such that the first chip and the second chip do not directly contact the package cover.
Through the technical scheme, the heat conducting medium surrounds the periphery of the chip, so that heat generated during the operation of the chip can be effectively and rapidly dissipated.
Additional features and advantages of the present application will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the description serve to explain, but not limit the application. In the drawings:
fig. 1 is a cross-sectional view of a semiconductor package structure according to an embodiment of the present application;
fig. 2 is a cross-sectional view of a semiconductor package structure according to further embodiments of the present application;
fig. 3 is a cross-sectional view of a semiconductor package structure according to another further embodiment of the present application;
fig. 4 is a top view of a semiconductor package structure according to further embodiments of the present application;
FIG. 5 illustrates forming a package cover in a semiconductor package structure according to an embodiment of the present application on a silicon wafer;
fig. 6A to 6H are schematic views showing a structure obtained after each step is performed by a method for manufacturing a semiconductor package structure according to an embodiment of the present application.
Description of the reference numerals
100 semiconductor package 110 first chip
111 first mounting surface 112 first contact
113 first passivation layer 114 side-by-side gap
120 second chip 121 second mounting surface
122 second contact 123 second passivation layer
130 package cover 131 third mounting surface
132 first cavity 133 second cavity
134 first gap 135 second gap
136 first opening 137 second opening
138 channels 140 heat transfer medium
141 fill surface 150 rewiring layer
151 first surface 152 second surface
153 first fan-in pad 154 second fan-in pad
155 external bonding pad 156a first fan-out line
156b second fan-out line 156c inter-connect line
157 first solder ball 160 carrier substrate
161 first surface 162 second surface
163 interconnect pad 164 terminal pad
165 second solder ball of line 166
167 solder mask 200 carrier plate
210 adhesive tape
Detailed Description
The following detailed description of specific embodiments of the present application refers to the accompanying drawings. It should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application.
In the present application, unless otherwise stated, terms such as "upper/above, lower/below, left/left, right/right" are used to refer generally to the upper, lower, left, right as shown with reference to the drawings. "inner and outer" generally refer to the inner and outer relative to the contour of the components themselves.
In this application, if the terms "front side of the chip", "active side of the chip", "first surface of the chip" are used, it may refer to a surface having integrated circuits; in this application, if the terms "back side of the chip", "second surface of the chip" are used, they may refer to the surface opposite to "front side of the chip", "active side of the chip", "first surface of the chip".
In the drawings, the shapes of the illustrations as a result, variations are possible in accordance with manufacturing techniques and/or tolerances. Accordingly, exemplary embodiments of the present application are not limited to the specific shapes shown in the drawings, and may include shape changes caused during manufacturing. Furthermore, the various elements and regions in the figures are only schematically illustrated and thus the present application is not limited to the relative dimensions or distances illustrated in the figures.
Fig. 1 is a cross-sectional view of a semiconductor package 100 according to an embodiment of the present application. Referring to fig. 1, a semiconductor package structure 100 according to an embodiment of the present application may include a first chip 110 and a second chip 120. The first chip 110 and the second chip 120 may be arranged side by side. The first chip 110 may have a first mounting surface 111 and a plurality of first contacts 112 exposed on the first mounting surface 111. For example, the first mounting surface 111 may be an active surface of the first chip 110, and the first contact 112 may be a first chip pad. In addition, an area other than the first chip pad on the first mounting surface 111 may be covered with the first passivation layer 113. The kind of the first passivation layer 113 may include, but is not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers).
The second chip 120 may have a second mounting surface 121 and a plurality of second contacts 122 exposed on the second mounting surface 121. For example, the second mounting surface 121 may be an active surface of the second chip 120, and the second contact 122 may be a second chip pad. In addition, an area other than the second chip pad on the second mounting surface 121 may be covered with the second passivation layer 123. The kind of the second passivation layer 123 may include, but is not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers).
The types of the first chip 110 may include a memory chip and a logic chip. Examples of memory chips may include, but are not limited to, random Access Memory (RAM). Examples of RAM may include Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Examples of logic chips may include, but are not limited to, graphics processing unit (Graphic Processing Unit, GPU) chips, central processing unit (Central Processing Unit, CPU) chips, system On Chip (SOC).
The types of the second chip 120 may include a memory chip and a logic chip. Examples of memory chips may include, but are not limited to, random Access Memory (RAM). Examples of RAM may include Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Examples of logic chips may include, but are not limited to, graphics processing unit (Graphic Processing Unit, GPU) chips, central processing unit (Central Processing Unit, CPU) chips, system On Chip (SOC).
In an embodiment of the present application, the first chip 110 may be, for example, a logic chip, and the second chip 120 may be, for example, a memory chip.
In an embodiment of the present application, a side-by-side gap 114 may be formed between the first chip 110 and the second chip 120.
The semiconductor package 100 may further include a package cover 130. The package cover 130 may have a third mounting surface 131, and a first cavity 132 and a second cavity 133 recessed from the third mounting surface 131. The third mounting surface 131 may be aligned with the first mounting surface 111 and the second mounting surface 121, the first chip 110 may be received in the first cavity 132, and the second chip 120 may be received in the second cavity 133. The first cavity 132 may have a first gap 134 with the first chip 110, and the second cavity 133 may have a second gap 135 with the second chip 120. For example, in one example, the side of the first chip 110 is in contact with the first cavity 132 or not but the gap between is extremely small (can be considered as contact), with only the first gap 134 between the top surface of the first chip 110 and the first cavity 132. In another example, the top surface of the first chip 110 is in contact with the first cavity 132 or not but the gap between is extremely small (can be considered as contact), with only the side surface of the first chip 110 having the first gap 134 between the first cavity 132. In yet another example, a portion (e.g., one or more) of the sides of the first chip 110 is in contact with the first cavity 132 or not but the gap therebetween is extremely small (can be considered as contact), with the remainder of the sides of the first chip 110 and the top surface having the first gap 134 therebetween. In a preferred example, the first chip 110 has a first gap 134 between the side and top surfaces and the first cavity 132. The width of the first gap 134 may range from 10 micrometers to 100 micrometers such that the first chip 110 does not directly contact the package cover 130. This may facilitate filling of the heat transfer medium 140 and continuous formation of a continuous surface.
For example, in one example, the side of the second chip 120 is in contact with the second cavity 133 or not but the gap between is extremely small (can be considered as contact), only the top surface of the second chip 120 has the second gap 135 between the second cavity 133. In another example, the top surface of the second chip 120 is in contact with the second cavity 133 or not but the gap between them is extremely small (can be considered as contact), only the side surface of the second chip 120 has the second gap 135 between it and the second cavity 133. In yet another example, a portion (e.g., one or more) of the sides of the second chip 120 is in contact with the second cavity 133 or not but the gap therebetween is extremely small (can be considered as contact), with a second gap 135 between the top surface and the remaining portion of the sides of the second chip 120. In a preferred example, the second chip 120 has a second gap 135 between the side and top surfaces and the second cavity 133. The width of the second gap 135 may range from 10 micrometers to 100 micrometers so that the second chip 120 does not directly contact the package cover 130. This may facilitate filling of the heat transfer medium 140 and continuous formation of a continuous surface.
The semiconductor package structure 100 may further include a heat conductive medium 140 filled in the first gap 134 and the second gap 135, the heat conductive medium 140 having a filling surface 141 connecting the first mounting surface 111, the second mounting surface 121, and the third mounting surface 131 such that the first mounting surface 111, the second mounting surface 121, and the third mounting surface 131 are formed on a continuous surface. For example, the heat transfer medium 140 may be at least one selected from the group consisting of ultra-high temperature heat transfer glue, silicone heat transfer glue, epoxy resin AB glue, polyurethane glue, and heat transfer silicone grease. The heat transfer medium 140 may not only adhere the first chip 110 and the second chip 120 to the package cover 130, but also may play a role in heat dissipation.
The semiconductor package structure 100 may further include a re-wiring layer 150 formed on the continuous surface, and the re-wiring layer 150 may include a first fan-in pad 153, a second fan-in pad 154, and an external pad 155. The first fan-in pad 153 may be bonded to the first contact 112 and connected to a corresponding external pad 155 via a first fan-out line 156a within the rewiring layer 150. The second fan-in pad 154 is bonded to the second contact 122 and connected to a corresponding external pad 155 via a second fan-out line 156b within the rewiring layer 150. The rewiring layer 150 may further include at least one internal interconnect 156c connecting the first fan-in pad 153 with the second fan-in pad 154. For example, the first fan-in pad 153 and the second fan-in pad 154 may be located on a first surface 151 of the rewiring layer 150, and the external pad 155 may be located on a second surface 152 opposite the first surface 151.
In particular, the re-routing layer 150 may include a dielectric layer and lines (e.g., first fan-out lines 156a, second fan-out lines 156b, inner interconnect lines 156c, etc.) formed in the dielectric layer. The material of the dielectric layer may include a polymer thin film material such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of the dielectric layer may also include other insulating materials. For example, a re-routing technique may be employed to form lines in the dielectric layer and pads (e.g., first fan-in pad 153, second fan-in pad 154, external pad 155, etc.) electrically connected to the lines. RDL technology is a technology known to those skilled in the art and is not described in detail herein. In one embodiment of the present application, the material of the wire may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the traces may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals. In one embodiment of the present application, the wires and pads may use the same material. In another embodiment of the present application, different materials may be used for the wires and pads. In an embodiment of the present application, any one of the first fan-out line 156a, the second fan-out line 156b, and the inner interconnection line 156c has a line width/line pitch of less than 15 micrometers.
The semiconductor package may further include first solder balls 157 implanted on the external bond pads 155. For example, the first solder balls 157 may be implanted to the external bond pads 155 using a ball-implant process.
In one embodiment of the present application, the package cover 130 may further have a first opening 136 communicating with the first cavity 132 and a second opening 137 communicating with the second cavity 133 for filling the heat transfer medium 140. As shown in fig. 1, the first opening 136 and/or the second opening 137 may be located at the top of the enclosure 130, but those skilled in the art will appreciate that the first opening 136 and/or the second opening 137 may also be located at other locations of the enclosure 130. The shape of the first opening 136 and/or the second opening 137 may include any one of an ellipse (elliptic cylinder), a circle (cylinder), a square (rectangular cylinder), and a prism (prismatic cylinder). Those skilled in the art will appreciate that the first opening 136 and/or the second opening 137 may have other shapes not illustrated. Fig. 4 is a top view of a semiconductor package 100 according to further embodiments of the present application. As shown in fig. 4, the shape of the first opening 136 may be elliptical (elliptical cylinder) and the shape of the second opening 137 may be circular (cylindrical), but those skilled in the art will appreciate that the shapes of the first opening 136 and the second opening 137 shown in fig. 4 are exemplary, and that other combinations of shapes are possible for the first opening 136 and the second opening 137. In one example, the size of the first opening 136 may be smaller than the size of the second opening 137. In another example, the size of the first opening 136 may be equal to the size of the second opening 137. In a preferred embodiment of the present application, the size of the first opening 136 may be greater than the size of the second opening 137.
In the embodiment of the present application shown in fig. 1, the first and second openings 136 and 137 may serve as inlets of the first and second cavities 132 and 133, respectively, i.e., the heat transfer medium 140 is injected into the first and second cavities 132 and 133 through the first and second openings 136 and 137, respectively, and may fill the first and second cavities 132 and 133 and preferably the first and second openings 136 and 137.
Fig. 2 is a cross-sectional view of a semiconductor package structure 100 according to further embodiments of the present application. Referring to fig. 2, the semiconductor package structure 100 shown in fig. 2 is substantially the same as the semiconductor package structure 100 shown in fig. 1, except that the package cover 130 in the semiconductor package structure 100 shown in fig. 2 may further have a channel 138 communicating the first cavity 132 and the second cavity 133, and the heat conductive medium 140 is further filled in the channel 138. As shown in fig. 2, in one example, the channel 138 may be formed by a groove in a wall between the first cavity 132 and the second cavity 133. In another example, the channel 138 may be formed by a through hole in a wall between the first cavity 132 and the second cavity 133. In the top view of the semiconductor package 100 according to the embodiment of the present application shown in fig. 4, the first opening 136 may serve as a glue inlet, and the second opening 137 may serve as a glue outlet. In an alternative embodiment of the present application, the first opening 136 may be used as a glue outlet and the second opening 137 may be used as a glue inlet. In embodiments in which the size of the first opening 136 is greater than the size of the second opening 137, the first opening 136 may serve as a glue inlet and the second opening 137 may serve as a glue outlet. The heat transfer medium 140 may be injected from the first opening 136, and the heat transfer medium 140 fills the second cavity 133 through the channel 138 after filling the first cavity 132, and then comes out of the second opening 137, thereby completing the filling of the heat transfer medium 140.
In embodiments of the present application, the material of the encapsulation cover 130 may include, but is not limited to, glass, ceramic, and the like. In a preferred embodiment of the present application, the material of the package cover 130 may include silicon. The package cover 130 of silicon material is used to package the chip, compared to a conventional package chip using a molding compound, such as epoxy molding compound (Epoxy Molding Compound, EMC), because of the lower coefficient of thermal expansion of silicon, thereby making it easier to control warp (warp) in the process.
In an embodiment of the present application, at least one of the first cavity 132, the second cavity 133, the first opening 136, the second opening 137, the channel 138 may be formed on the package cover 130 using an etching technique. In a preferred embodiment of the present application, the package cover 130 may be formed on a silicon wafer. Fig. 5 illustrates forming a package cover 130 in a semiconductor package structure 100 according to an embodiment of the present application on a silicon wafer. As shown in fig. 5, a plurality of first cavities 132 and a plurality of second cavities 133 (and optionally, first openings 136, second openings 137, channels 138) may be etched in a silicon wafer in spaced apart relation. The silicon wafer is then singulated (e.g., diced) to obtain the desired package caps 130. Etching and singulation are conventional techniques, as any technique known in the art, and are not described in detail herein.
Fig. 3 is a cross-sectional view of a semiconductor package structure 100 according to another further embodiment of the present application. Referring to fig. 3, the semiconductor package structure 100 may further include a carrier substrate 160. The carrier substrate 160 may have a first surface 161 and a second surface 162. The carrier substrate 160 may include interconnect pads 163 located on the first surface 161, terminal pads 164 located on the second surface 162, and wires 165 electrically connecting the interconnect pads 163 and the terminal pads 164. The interconnect pad 163 may be bonded with the first solder ball 157.
Carrier substrate 160 may be, but is not limited to, a wire film. In particular, the carrier substrate 160 may include a dielectric layer, a wire 165 formed within the dielectric layer, and an interconnect pad 163 and a terminal pad 164 disposed on the first surface 161 and the second surface 162 of the carrier substrate 160, respectively, and electrically connected to the wire 165. For example, the traces 165 may be formed using a printed circuit board (Printed Circuit Board, PCB) process. In embodiments of the present application, the material of the traces 165 may comprise gold, silver, platinum, aluminum, copper. In a preferred embodiment, the material of the traces 165 may comprise copper.
In an embodiment of the present application, the semiconductor package 100 may further include a second solder ball 166 implanted on the terminal pad 164. For example, the second solder balls 166 may be implanted to the terminal pads 164 using a ball implant process.
In an embodiment of the present application, the second surface 162 (bottom surface) of the carrier substrate 160 may have a Solder Mask (Solder Mask) 167 thereon, the Solder Mask 167 not covering the terminal pads 164 on the bottom surface of the carrier substrate 160. In addition, the surface of the terminal pad 164 may be subjected to a surface polishing process before the second solder ball 166 is implanted on the terminal pad 164.
The semiconductor package structure 100 according to embodiments of the present application may be applied in a wafer level chip scale package (Wafer Level Chip Size Package, WLCSP), particularly in a Fan-out (Fan-out) WLCSP (FOWLCSP).
Embodiments of the present application also provide methods for fabricating semiconductor package structures. Fig. 6A to 6H are schematic views showing a structure obtained after each step is performed by a method for manufacturing a semiconductor package structure according to an embodiment of the present application. Referring to fig. 6A to 6H, a method according to an embodiment of the present application may include the following steps.
Referring to fig. 6A, in step S102, a carrier 200 is provided, and the first chip 110 and the second chip 120 are disposed on the carrier 200 side by side. The first chip 110 has a first mounting surface 111 and a plurality of first contacts 112 exposed on the first mounting surface 111. The second chip 120 has a second mounting surface 121 and a plurality of second contacts 122 exposed on the second mounting surface 121. A parallel gap 114 is formed between the first chip 110 and the second chip 120. The first mounting surface 111 and the second mounting surface 121 may be attached to the carrier plate 200. For example, the first mounting surface 111 may be an active surface of the first chip 110, and the first contact 112 may be a first chip pad. In addition, an area other than the first chip pad on the first mounting surface 111 may be covered with the first passivation layer 113. The kind of the first passivation layer 113 may include, but is not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers).
The second chip 120 may have a second mounting surface 121 and a plurality of second contacts 122 exposed on the second mounting surface 121. For example, the second mounting surface 121 may be an active surface of the second chip 120, and the second contact 122 may be a second chip pad. In addition, an area other than the second chip pad on the second mounting surface 121 may be covered with the second passivation layer 123. The kind of the second passivation layer 123 may include, but is not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubber).
The types of the first chip 110 may include a memory chip and a logic chip. Examples of memory chips may include, but are not limited to, random Access Memory (RAM). Examples of RAM may include Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Examples of logic chips may include, but are not limited to, graphics processing unit (Graphic Processing Unit, GPU) chips, central processing unit (Central Processing Unit, CPU) chips, system On Chip (SOC).
The types of the second chip 120 may include a memory chip and a logic chip. Examples of memory chips may include, but are not limited to, random Access Memory (RAM). Examples of RAM may include Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Examples of logic chips may include, but are not limited to, graphics processing unit (Graphic Processing Unit, GPU) chips, central processing unit (Central Processing Unit, CPU) chips, system On Chip (SOC).
In an embodiment of the present application, the first chip 110 may be, for example, a logic chip, and the second chip 120 may be, for example, a memory chip.
In an embodiment of the present application, a Known qualified chip (KGD) may be selected from the first chip 110, and a KGD may be selected from the second chip 120.
Referring to fig. 6B, in step S104, a package cover 130 is provided, and the package cover 130 may have a third mounting surface 131 and first and second cavities 132 and 133 recessed from the third mounting surface 131.
Referring to fig. 6C, in step S106, the package cover 130 is covered on the first chip 110 and the second chip 120, the third mounting surface 131 is attached to the carrier 200, such that the third mounting surface 131 is aligned with the first mounting surface 111 and the second mounting surface 121, the first chip 110 is accommodated in the first cavity 132, the second chip 120 is accommodated in the second cavity 133, a first gap 134 is provided between the first cavity 132 and the first chip 110, and a second gap 135 is provided between the second cavity 133 and the second chip 120.
For example, in one example, the side of the first chip 110 is in contact with the first cavity 132 or not but the gap therebetween is extremely small (can be considered as contact), with only the first gap 134 between the top surface of the first chip 110 and the first cavity 132. In another example, the top surface of the first chip 110 is in contact with the first cavity 132 or not but the gap therebetween is extremely small (may be considered as contact), with only the side surface of the first chip 110 having the first gap 134 between the first cavity 132. In yet another example, a portion (e.g., one or more) of the sides of the first chip 110 are in contact with the first cavity 132 or are not in contact but the gap therebetween is extremely small (can be considered to be contact), with the remainder of the sides of the first chip 110 and the top surface having the first gap 134 therebetween. In a preferred example, the first chip 110 has a first gap 134 between the side and top surfaces and the first cavity 132. The width of the first gap 134 may range from 10 micrometers to 100 micrometers such that the first chip 110 does not directly contact the package cover 130. This may facilitate filling of the heat transfer medium 140 and continuous formation of a continuous surface.
For example, in one example, the side of the second chip 120 is in contact with the second cavity 133 or not but the gap therebetween is extremely small (can be considered as contact), with only the second gap 135 between the top surface of the second chip 120 and the second cavity 133. In another example, the top surface of the second chip 120 is in contact with the second cavity 133 or not but the gap therebetween is extremely small (can be considered as contact), with only the side surface of the second chip 120 having the second gap 135 between the second cavity 133. In yet another example, a portion (e.g., one or more) of the sides of the second chip 120 is in contact with the second cavity 133 or not but the gap therebetween is extremely small (can be considered as contact), with a second gap 135 between the top surface and the remaining portion of the sides of the second chip 120. In a preferred example, the second chip 120 has a second gap 135 between the side and top surfaces and the second cavity 133. The width of the second gap 135 may range from 10 micrometers to 100 micrometers so that the second chip 120 does not directly contact the package cover 130. This may facilitate filling of the heat transfer medium 140 and continuous formation of a continuous surface.
In one embodiment of the present application, the package cover 130 may further have a first opening 136 communicating with the first cavity 132 and a second opening 137 communicating with the second cavity 133 for filling the heat transfer medium 140. As shown in fig. 6C, the first opening 136 and/or the second opening 137 may be located at the top of the enclosure 130, but those skilled in the art will appreciate that the first opening 136 and/or the second opening 137 may also be located at other locations of the enclosure 130. The shape of the first opening 136 and/or the second opening 137 may include any one of an ellipse (elliptic cylinder), a circle (cylinder), a square (rectangular cylinder), and a prism (prismatic cylinder). Those skilled in the art will appreciate that the first opening 136 and/or the second opening 137 may have other shapes not illustrated. The shape of the first opening 136 may be elliptical (elliptical cylinder) and the shape of the second opening 137 may be circular (cylindrical), but one skilled in the art will appreciate that other combinations of shapes are possible for the first opening 136 and the second opening 137. In one example, the size of the first opening 136 may be smaller than the size of the second opening 137. In another example, the size of the first opening 136 may be equal to the size of the second opening 137. In a preferred embodiment of the present application, the size of the first opening 136 may be greater than the size of the second opening 137.
In further embodiments of the present application, the package cover 130 may further have a channel 138 communicating the first cavity 132 and the second cavity 133, and the heat conductive medium 140 is further filled in the channel 138. In one example, the channel 138 may be formed by a groove in the wall between the first cavity 132 and the second cavity 133. In another example, the channel 138 may be formed by a through hole in a wall between the first cavity 132 and the second cavity 133.
In embodiments of the present application, the material of the encapsulation cover 130 may include, but is not limited to, glass, ceramic, and the like. In a preferred embodiment of the present application, the material of the package cover 130 may include silicon. The package cover 130 of silicon material is used to package the chip, compared to a conventional package chip using a molding compound such as epoxy molding compound (Epoxy Molding Compound, EMC), because of the lower coefficient of thermal expansion of silicon, thereby making it easier to control Warpage (warp) in the process.
In an embodiment of the present application, at least one of the first cavity 132, the second cavity 133, the first opening 136, the second opening 137, the channel 138 may be formed on the package cover 130 using an etching technique. In a preferred embodiment of the present application, the package cover 130 may be formed on a silicon wafer. Thus, providing the package cover 130 in step S104 may include the following steps. The first and second cavities 132 and 133 may be etched on the silicon wafer in spaced apart arrangement. And optionally, any of the first opening 136, the second opening 137, the channel 138 may be etched. The silicon wafer is then singulated (e.g., diced) to obtain the desired package caps 130. Etching and singulation are conventional techniques, as any technique known in the art, and are not described in detail herein.
Referring to fig. 6D, in step S108, the heat transfer medium 140 is filled in the first gap 134 and the second gap 135. The heat conductive medium 140 has a filling surface 141 connecting the first mounting surface 111, the second mounting surface 121, and the third mounting surface 131 such that the first mounting surface 111, the second mounting surface 121, and the third mounting surface 131 are formed on a continuous surface.
In an embodiment in which the package cover 130 does not have the first and second openings 136 and 137, step S108 may occur before step S106, that is, after the first and second chips 110 and 120 are mounted, the heat conductive medium 140 is coated on the surfaces of the first and second chips 110 and 120 so as to cover the first and second chips 110 and 120, and a heat conductive medium 140 layer of a certain thickness is formed. Step S106 is then performed such that the first chip 110 is received in the first cavity 132 and the second chip 120 is received in the second cavity 133, and the layer of heat conductive medium 140 fills the first gap 134 and the second gap 135.
In the embodiment in which the package cover 130 has the first and second openings 136 and 137, the heat transfer medium 140 may be filled in the first and second gaps 134 and 135 through the first and second openings 136 and 137, respectively.
In an embodiment in which the package cover 130 further has the channel 138, one of the first opening 136 and the second opening 137 may be used as a glue inlet, the other one may be used as a glue outlet, the heat-conducting medium 140 may be injected into the first cavity 132 and the second cavity 133 through the glue inlet, and the excess heat-conducting medium 140 may come out from the glue outlet.
The heat transfer medium 140 may be at least one selected from the group consisting of ultra-high temperature heat transfer glue, silicone heat transfer glue, epoxy resin AB glue, polyurethane glue, and heat transfer silicone grease. The heat transfer medium 140 may not only adhere the first chip 110 and the second chip 120 to the package cover 130, but also may play a role in heat dissipation.
Referring to fig. 6E, in step S110, the carrier plate 200 is separated. Specifically, in one embodiment of the present application, an adhesive tape 210, such as a thermal adhesive film, may be attached to the carrier board 200, and in step S102, the first chip 110 and the second chip 120 are placed on the thermal adhesive film. After step S108 is performed, the thermally degummed film may be heated (e.g., by laser irradiation) to lose its tackiness so that the carrier sheet 200 is peeled off.
In alternative embodiments of the present application, other ways of separating the carrier plates may be used. For example, an Ultraviolet (UV) sensitive adhesive may be coated on the glass sheet or the semiconductor carrier, and after step S108, the UV sensitive adhesive is irradiated to lose its adhesion, so that the carrier 200 may be peeled off.
Those skilled in the art will appreciate that other means of separating the carrier 200 that are commonly used in the art are also within the scope of the present application.
After separating the carrier 200, the package obtained after performing step S108 may be flipped.
Referring to fig. 6F, in step S112, a re-wiring layer 150 is formed on the continuous surface. The rewiring layer 150 includes a first fan-in pad 153, a second fan-in pad 154, and an external pad 155. The first fan-in pad 153 is bonded to the first contact and connected to the corresponding external pad 155 via a first fan-out line 156 a. The second fan-in pad 154 is bonded to the second contact and connected to a corresponding external pad 155 via a second fan-out line 156 b. The redistribution layer 150 further includes at least one internal interconnect 156c connecting the first fan-in pad 153 with the second fan-in pad 154.
In particular, the re-routing layer 150 may include a dielectric layer and lines (e.g., first fan-out lines 156a, second fan-out lines 156b, inner interconnect lines 156c, etc.) formed in the dielectric layer. The material of the dielectric layer may include a polymer thin film material such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of the dielectric layer may also include other insulating materials. For example, a re-routing technique may be employed to form lines in the dielectric layer and pads (e.g., first fan-in pad 153, second fan-in pad 154, external pad 155, etc.) electrically connected to the lines. RDL technology is a technology known to those skilled in the art and is not described in detail herein. In one embodiment of the present application, the material of the wire may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the traces may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals. In one embodiment of the present application, the wires and pads may use the same material. In another embodiment of the present application, different materials may be used for the wires and pads. In an embodiment of the present application, any one of the first fan-out line 156a, the second fan-out line 156b, and the inner interconnection line 156c has a line width/line pitch of less than 15 micrometers.
In step S114, first solder balls 157 are implanted on the external pads 155. For example, the first solder balls 157 may be implanted to the external bond pads 155 using a ball-implant process.
Referring to fig. 6G, in step S116, the resulting package is flipped over and the package cover 130 is singulated to make a plurality of semiconductor package structures, each including the first chip 110 and the second chip 120.
In further embodiments of the present application, the method for manufacturing a semiconductor package structure may further include the following steps.
Referring to fig. 6H, in step S118, a carrier substrate 160 is provided, the carrier substrate 160 may have a first surface 161 and a second surface 162, and the carrier substrate 160 includes an interconnect pad 163 on the first surface 161, a terminal pad 164 on the second surface 162, and a wire 165 electrically connecting the interconnect pad 163 and the terminal pad 164.
Carrier substrate 160 may be, but is not limited to, a wire film. In particular, the carrier substrate 160 may include a dielectric layer, a wire 165 formed within the dielectric layer, and an interconnect pad 163 and a terminal pad 164 disposed on the first surface 161 and the second surface 162 of the carrier substrate 160, respectively, and electrically connected to the wire 165. For example, the traces 165 may be formed using a printed circuit board (Printed Circuit Board, PCB) process. In embodiments of the present application, the material of the traces 165 may comprise gold, silver, platinum, aluminum, copper. In a preferred embodiment, the material of the wire may comprise copper.
In an embodiment of the present application, the second surface 162 (bottom surface) of the carrier substrate 160 may have a Solder Mask (Solder Mask) 167 thereon, the Solder Mask 167 not covering the terminal pads 164 on the bottom surface of the carrier substrate 160. In addition, the surface of the terminal pad 164 may be subjected to a surface polishing process before the second solder ball 166 is implanted on the terminal pad 164.
In step S120, the interconnect pad 163 is bonded with the first solder ball 157.
In step S122, the second solder balls 166 are implanted on the terminal pads 164. For example, the second solder balls 166 may be implanted to the terminal pads 164 using a ball implant process.
The method for manufacturing the semiconductor packaging structure according to the embodiment of the application can be applied to a wafer level chip size package (Wafer Level Chip Size Package, WLCSP) process, particularly a Fan-out (Fan-out) WLCSP (FOWLCSP) process.
The semiconductor package structure 100 according to the embodiment of the present application or the semiconductor package structure manufactured according to the method for manufacturing a semiconductor package structure of the embodiment of the present application uses a silicon material instead of an epoxy molding compound (Epoxy Molding Compound, EMC) in a conventional process to mold a chip, which has a lower thermal expansion coefficient and makes it easier to control warp (warp) in a process. In addition, the heat conducting medium surrounds the periphery of the chip, so that heat generated during the operation of the chip can be effectively and rapidly dissipated.
Further, the semiconductor package structure 100 according to the embodiment of the present application or the semiconductor package structure manufactured according to the method for manufacturing a semiconductor package structure of the embodiment of the present application may have a smaller form factor and shorter signal connection, and good heat dissipation properties when applied to a SIP package.
In addition, the steps of the method for manufacturing a semiconductor package described in the above embodiments are only some of the main steps for manufacturing a semiconductor package, and those skilled in the art will understand that some other known steps may be included in the entire semiconductor package process, and these conventional known steps are not described in detail in the present application for conciseness of the specification of the present application, but should also be considered as the scope of the present application.
The preferred embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the present application is not limited to the specific details of the embodiments described above, and various simple modifications may be made to the technical solutions of the present application within the scope of the technical concept of the present application, and all the simple modifications belong to the protection scope of the present application.
It should be further noted that the various features described in the above embodiments may be combined in any suitable manner without a spear shield. In order to avoid unnecessary repetition, the various possible combinations are not described further.
Moreover, any combination of the various embodiments of the present application may be made without departing from the spirit of the present application, which should also be considered as disclosed herein.

Claims (16)

1. A semiconductor package structure, comprising:
the first chip is provided with a first mounting surface and a plurality of first contacts exposed on the first mounting surface, the second chip is provided with a second mounting surface and a plurality of second contacts exposed on the second mounting surface, and a parallel gap is formed between the first chip and the second chip, wherein the first mounting surface is an active surface of the first chip, and the second mounting surface is an active surface of the second chip;
a package cover having a third mounting surface, a first cavity and a second cavity recessed from the third mounting surface, the third mounting surface being aligned with the first mounting surface and the second mounting surface, the first chip being accommodated in the first cavity, the second chip being accommodated in the second cavity, a first gap being provided between the first cavity and the first chip, and a second gap being provided between the second cavity and the second chip;
A heat transfer medium filled in the first gap and the second gap, the heat transfer medium having a filling surface connecting the first mounting surface, the second mounting surface, and the third mounting surface such that the first mounting surface, the second mounting surface, and the third mounting surface are formed on a continuous surface;
the rewiring layer is formed on the continuous surface and comprises a first fan-in bonding pad, a second fan-in bonding pad and an external bonding pad, the first fan-in bonding pad is connected to the first contact and is connected to the corresponding external bonding pad through a first fan-out line, the second fan-in bonding pad is connected to the second contact and is connected to the corresponding external bonding pad through a second fan-out line, and the rewiring layer further comprises at least one inner interconnection line and is connected with the first fan-in bonding pad and the second fan-in bonding pad.
2. The semiconductor package according to claim 1, wherein the package cover further has a passage communicating the first cavity and the second cavity, and the heat conductive medium is filled in the passage.
3. The semiconductor package according to claim 1, further comprising:
The first solder ball is implanted on the external bonding pad.
4. The semiconductor package according to claim 3, further comprising:
a carrier substrate having a first surface and a second surface, the carrier substrate comprising an interconnect pad located on the first surface, a terminal pad located on the second surface, and a trace electrically connecting the interconnect pad and the terminal pad, the interconnect pad being bonded to the first solder ball; and
and the second solder ball is implanted on the terminal pad.
5. The semiconductor package according to claim 1, wherein the package cover further has a first opening communicating with the first cavity and a second opening communicating with the second cavity for filling the heat conductive medium.
6. The semiconductor package according to claim 5, wherein the shape of the first opening or the second opening comprises any one of an ellipse, a circle, a square, and a prism.
7. The semiconductor package of claim 1, wherein any of the first fan-out line, the second fan-out line, and the inner interconnect line has a line width/line spacing of less than 15 microns.
8. The semiconductor package according to claim 1, wherein the material of the package cover comprises silicon.
9. The semiconductor package according to claim 8, wherein the package cover is formed by etching and singulating a silicon wafer.
10. The semiconductor package according to any one of claims 1 to 9, wherein the first and second gaps have a width ranging from 10 micrometers to 100 micrometers such that the first and second chips do not directly contact the package cover.
11. A method for fabricating a semiconductor package, the method comprising:
providing a carrier plate, arranging a first chip and a second chip on the carrier plate side by side, wherein the first chip is provided with a first mounting surface and a plurality of first contacts exposed on the first mounting surface, the second chip is provided with a second mounting surface and a plurality of second contacts exposed on the second mounting surface, a parallel gap is formed between the first chip and the second chip, and the first mounting surface and the second mounting surface are attached to the carrier plate;
providing a packaging cover, wherein the packaging cover is provided with a third mounting surface, and a first cavity and a second cavity which are recessed by the third mounting surface;
The packaging cover is covered on the first chip and the second chip, the third mounting surface is attached to the carrier plate, the third mounting surface is aligned to the first mounting surface and the second mounting surface, the first chip is accommodated in the first cavity, the second chip is accommodated in the second cavity, a first gap is reserved between the first cavity and the first chip, and a second gap is reserved between the second cavity and the second chip;
filling a heat transfer medium in the first gap and the second gap, the heat transfer medium having a filling surface connecting the first mounting surface, the second mounting surface, and the third mounting surface such that the first mounting surface, the second mounting surface, and the third mounting surface are formed on a continuous surface;
separating the carrier plate;
forming a rewiring layer on the continuous surface, the rewiring layer comprising a first fan-in pad, a second fan-in pad and an external pad, the first fan-in pad being bonded to the first contact and connected to the corresponding external pad via a first fan-out line, the second fan-in pad being bonded to the second contact and connected to the corresponding external pad via a second fan-out line, the rewiring layer further comprising at least one internal interconnect line connecting the first fan-in pad and the second fan-in pad; and
Singulating the package caps to produce a plurality of semiconductor package structures, each semiconductor package structure including the first chip and the second chip.
12. The method as recited in claim 11, further comprising:
first solder balls are implanted on the external bonding pads before singulation of the package cover.
13. The method as recited in claim 12, further comprising:
providing a bearing substrate with a first surface and a second surface, wherein the bearing substrate comprises an interconnection pad positioned on the first surface, a terminal pad positioned on the second surface and a circuit electrically connecting the interconnection pad and the terminal pad;
bonding the interconnection pad with the first solder ball; and
and implanting second solder balls on the terminal pads.
14. The method of claim 11, wherein the enclosure further has a channel communicating the first cavity and the second cavity; when the heat-conducting medium is filled in the first gap and the second gap, the heat-conducting medium is also filled in the channel.
15. The method of claim 11, wherein the material of the encapsulation comprises silicon.
16. The method of any one of claims 11 to 15, wherein in the step of covering the package cover, the first and second gaps have a width ranging from 10 micrometers to 100 micrometers such that the first and second chips do not directly contact the package cover.
CN201711470750.5A 2017-12-29 2017-12-29 Semiconductor packaging structure and manufacturing method thereof Active CN107993994B (en)

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