CN107104058A - Fan-out-type list die package structure and preparation method thereof - Google Patents
Fan-out-type list die package structure and preparation method thereof Download PDFInfo
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- CN107104058A CN107104058A CN201710475741.9A CN201710475741A CN107104058A CN 107104058 A CN107104058 A CN 107104058A CN 201710475741 A CN201710475741 A CN 201710475741A CN 107104058 A CN107104058 A CN 107104058A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/11019—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H—ELECTRICITY
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract
The present invention provides a kind of fan-out-type list die package structure and preparation method thereof, including provides carrier, and adhesive layer is formed on carrier；Chip structure is formed on adhesive layer；Plastic packaging layer is formed on adhesive layer, wherein, plastic packaging layer coating chip structure；Carrier and adhesive layer is removed to expose chip structure；The first dielectric layer, which is formed, on the plastic packaging layer for exposing chip structure, and photoetching is carried out to the first dielectric layer exposes the first opening of contact pad to be formed；Form re-wiring layer on the first dielectric layer and contact pad, and photoetching is carried out to re-wiring layer and expose the second opening of first dielectric layer to be formed；The second dielectric layer is formed on re-wiring layer and the first dielectric layer；Laser ablation is carried out to the second dielectric layer and exposes the 3rd opening of the re-wiring layer to be formed；Soldered ball projection is formed in the 3rd opening.By fan-out-type list die package structure of the present invention and preparation method thereof, the problem of existing fan-out package technique manufacturing cost is high is solved.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of fan-out-type list die package structure and its system
Preparation Method.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future,
Integrated antenna package will improve the integration density of various electronic components by constantly reducing minimum feature size.At present, first
The method for packing entered includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging,
WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip
Chip), stacked package (Package on Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be current a kind of input/
Output port (I/O) is more, one of the integrated preferable Advanced Packaging method of flexibility.Fan-out-type wafer-level packaging is compared to routine
Wafer-level packaging have the advantages that its is unique：1. I/O spacing is flexible, independent of chip size；2. effective nude film is only used
(die), product yield is improved；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have
There are preferable electrical property and hot property；5. frequency applications；6. easily high-density wiring is realized in re-wiring layer (RDL).
At present, fan-out-type wafer-level packaging method is generally：Carrier is provided, in carrier surface formation adhesive layer；In bonding
Photoetching on layer, electroplate out re-wiring layer (Redistribution Layers, RDL)；Chip is pacified using chip bonding process
It is attached on re-wiring layer；Using Shooting Technique by chip plastic packaging in capsulation material layer in；Remove carrier and adhesive layer；Again
Photoetching, plating form Underbump metallization layer (UBM) on wiring layer；Carry out planting ball backflow on UBM, form soldered ball projection.However,
The continuous aggravation competed with semicon industry, improves product quality and reduction manufacturing cost has become semiconductor manufacturing industry
In the urgent need to address the problem of.
In consideration of it, being necessary that a kind of new fan-out-type list die package structure of design and preparation method thereof is above-mentioned to solve
Technical problem.
The content of the invention
The shortcoming of prior art, is tied it is an object of the invention to provide a kind of encapsulation of fan-out-type list nude film in view of the above
Structure and preparation method thereof, for solving the problem of existing fan-out-type wafer-level packaging technique manufacturing cost is high.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation of fan-out-type list die package structure
Method, the preparation method includes：
1) carrier is provided, an adhesive layer is formed in the upper surface of the carrier；
2) chip structure is formed in the adhesive layer upper surface, the chip structure includes bare chip and positioned at the naked core
The contact pad being electrically connected on piece and with the bare chip；
3) plastic packaging layer, the plastic packaging layer cladding chip structure are formed in the adhesive layer upper surface；
4) carrier and the adhesive layer are removed, to expose the chip structure；
5) plastic packaging layer surface the first dielectric layer of formation of the chip structure is being exposed, and first dielectric layer is being entered
Row photoetching, to form the first opening for exposing the contact pad；
6) re-wiring layer is formed in first dielectric layer surface and contact pad surface, and to the re-wiring layer
Photoetching is carried out, to form the second opening for exposing first dielectric layer；
7) in the re-wiring layer and the first dielectric layer surface the second dielectric layer of formation；
8) laser ablation is carried out in second dielectric layer surface, exposing the 3rd of the re-wiring layer with formation opens
Mouthful；
9) in the 3rd open surfaces formation soldered ball projection.
Preferably, the method for the re-wiring layer is formed in 6) to be included：
6.1) insulating barrier is formed in first dielectric layer surface and contact pad surface, and light is carried out to the insulating barrier
Carve, to expose the contact pad；
6.2) in the surface of insulating layer and contact pad forming metal layer on surface.
Preferably, the method for the re-wiring layer is formed in 6) to be included：
The laminated construction of insulating barrier and metal level is alternatively formed in first dielectric layer and contact pad surface, it is described folded
The top layer of Rotating fields be metal level, and the laminated construction first layer metal layer be electrically connected with the contact pad, phase
Adjacent two metal layers are electrically connected by the metal plug through respective insulation layers, wherein, the alternate number of times is not small
In 2 times.
Preferably, the step of laser ablation is carried out in 8) includes：
8.1) second dielectric layer and re-wiring layer are performed etching using laser etching process, with described second
The first inverted trapezoidal opening is formed in dielectric layer and re-wiring layer；
8.2) bottom of the first inverted trapezoidal opening is performed etching using laser etching process, to be fallen described first
Second inverted trapezoidal opening is formed on trapezoidal bottom, wherein, the following long ladder that fallen more than described second of the first inverted trapezoidal opening
The upper length of side of shape opening.
Preferably, the wavelength of laser is 193~532nm in laser etching process.
Preferably, the difference of the upper length of side of the lower length of side of the first inverted trapezoidal opening and the second inverted trapezoidal opening is 40
~600um.
Preferably, the step of soldered ball projection is formed in 9) includes first forming metal column in the 3rd open surfaces, then
In the metal column and rewiring layer surface formation soldered ball.
The present invention also provides a kind of fan-out-type list die package structure, and the encapsulating structure includes：
Chip structure, the chip structure includes bare chip and carried out on the bare chip and with the bare chip
The contact pad of electrical connection；
The chip structure is surrounded, while the plastic packaging layer on surface where exposing the contact pad；
The first dielectric layer positioned at plastic packaging layer and chip structure upper surface, first dielectric layer passes through the first opening
Expose the contact pad；
Re-wiring layer positioned at first dielectric layer and contact pad upper surface, the re-wiring layer passes through second
Opening exposes first dielectric layer；
The second dielectric layer positioned at the re-wiring layer and the first dielectric layer upper surface, second dielectric layer passes through
Three openings expose the re-wiring layer；And
Positioned at the soldered ball projection of the described 3rd opening.
Preferably, the re-wiring layer includes：
Insulating barrier positioned at first dielectric layer and contact pad upper surface, the insulating barrier is described provided with exposing
The opening of contact pad；And
Metal level positioned at the insulating barrier and contact pad upper surface.
Preferably, the re-wiring layer includes：
The lamination knot constituted positioned at first dielectric layer and contact pad surface, by alternate insulating barrier and metal level
Structure, the top layer of the laminated construction is metal level, and the first layer metal layer of the laminated construction is carried out with the contact pad
Electrical connection, adjacent two layers metal level is electrically connected by the metal plug through respective insulation layers, wherein, described alternate time
Number is not less than 2 times.
Preferably, the 3rd opening includes the first inverted trapezoidal opening, and the with the first inverted trapezoidal opening insertion
Second-speculation's trapezoid-shaped openings, wherein, the following long upper length of side more than the second inverted trapezoidal opening of the first inverted trapezoidal opening.
Preferably, the difference of the upper length of side of the lower length of side of the first inverted trapezoidal opening and the second inverted trapezoidal opening is 40
~600um.
Preferably, the soldered ball projection includes the metal column positioned at the 3rd open bottom, and positioned at the metal column
And the soldered ball on re-wiring layer.
As described above, fan-out-type list die package structure of the present invention and preparation method thereof, has the advantages that：It is logical
Preparation method of the present invention is crossed, while single nude film fan-out package is realized, also by second dielectric layer and again
New route layer carries out laser ablation, to form the 3rd opening being made up of two inverted trapezoidal openings in the re-wiring layer,
To substitute the UBM layer of existing encapsulating structure, and by making soldered ball projection in being open the described 3rd, not only increase soldered ball convex
Cohesive between block and re-wiring layer, also effectively prevent the soldered ball in globule state in ball reflux course is planted and occurs
Move and position skew occur, it is ensured that the quality of encapsulating structure；Avoid simultaneously on the second dielectric layer by coating photoetching
Glue, the processing step system such as light shield mask, exposure imaging are made, litho pattern, the second dielectric layer of etching is formed, forms UBM, removes photoresist
Make UBM process, not only shorten processing time, also reduce production cost.
Brief description of the drawings
Fig. 1~Figure 11 is shown as each making step schematic diagram of encapsulating structure of the present invention, wherein, Fig. 9 and Figure 10 are
Region A making step schematic diagram in Fig. 8.
Component label instructions
1 carrier
2 adhesive layers
3 chip structures
31 bare chips
32 contact pads
4 plastic packagings layer
5 first dielectric layers
6 first openings
7 re-wiring layers
71 insulating barriers
72 metal levels
8 second openings
9 second dielectric layers
10 the 3rd openings
101 first inverted trapezoidal openings
102 second inverted trapezoidal openings
11 soldered ball projections
111 metal columns
112 soldered balls
1)~9) step
6.1)~6.2) step
8.1)~8.2) step
Embodiment
Embodiments of the present invention are illustrated by particular specific embodiment below, those skilled in the art can be by this explanation
Content disclosed by book understands other advantages and effect of the present invention easily.
Fig. 1 is referred to Figure 11.It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., is only used
To coordinate the content disclosed in the specification of carrier 1, so that those skilled in the art is understood with reading, this hair is not limited to
Bright enforceable qualifications, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or size
Adjustment, in the case where not influenceing of the invention effect that can be generated and the purpose that can reach, all should still fall disclosed
Technology contents obtain and can cover in the range of.Meanwhile, in this specification it is cited as " on ", " under ", "left", "right", " in
Between " and " one " etc. term, be merely convenient to understanding for narration, and be not used to limit enforceable scope of the invention, its is relative
Relation is altered or modified, under without essence change technology contents, when being also considered as enforceable category of the invention.
Embodiment one
As shown in Figure 1 to 11, the present embodiment provides a kind of preparation method of fan-out-type list die package structure, the system
Preparation Method includes：
1) carrier 1 is provided, an adhesive layer 2 is formed in the upper surface of the carrier 1；
2) chip structure 3 is formed in the upper surface of adhesive layer 2, the chip structure 3 includes bare chip 31 and positioned at institute
The contact pad 32 stated on bare chip 31 and be electrically connected with the bare chip 31；
3) plastic packaging layer 4, the cladding chip structure 3 of plastic packaging layer 4 are formed in the upper surface of adhesive layer 2；
4) carrier 1 and the adhesive layer 2 are removed, to expose the chip structure 3；
5) the first dielectric layer 5 is formed on 4 surface of plastic packaging layer for exposing the chip structure 3, and to first dielectric
Layer 5 carries out photoetching, to form the first opening 6 for exposing the contact pad 32；
6) re-wiring layer 7 is formed on the surface of the first dielectric layer 5 and the surface of contact pad 32, and to the cloth again
Line layer 7 carries out photoetching, to form the second opening 8 for exposing first dielectric layer 5；
7) the second dielectric layer 9 is formed on the surface of 7 and first dielectric layer of re-wiring layer 5；
8) laser ablation is carried out on the surface of the second dielectric layer 9, the 3rd of the re-wiring layer 7 is exposed to be formed
Opening 10；
9) soldered ball projection 11 is formed on the described 3rd 10 surfaces of opening.
Fig. 1 to Figure 11 is referred to below preparation method described in the present embodiment is described in detail.
As shown in Figure 1 there is provided a carrier 1, an adhesive layer 2 is formed in the upper surface of the carrier 1.
As an example, the material of the carrier 1 includes one in silicon, glass, silica, ceramics, polymer and metal
Kind or two or more composites, its shape can for wafer shape, it is square or it is other arbitrarily needed for shape；The present embodiment passes through
The problems such as carrier 1 is to prevent subsequent preparation process SMIS chip architecture 3 from occurring rupture, warpage, be broken.
As an example, the material of the adhesive layer 2 includes adhesive tape, adhesive glue, epoxy resin (Epoxy), silicon rubber
One kind in (silicone rubber), polyimides (PI), polybenzoxazoles (PBO) or benzocyclobutene (BCB)；Pass through
(ultraviolet) solidifications of UV or heat cure make, for the separating layer as carrier 1 and the chip-packaging structure being subsequently formed.
As shown in Fig. 2 forming chip structure 3 in the upper surface of adhesive layer 2, the chip structure 3 includes bare chip 31
And the contact pad 32 being electrically connected on the bare chip 31 and with the bare chip 31.
As an example, the quantity of the chip structure 3 is more than or equal to 1, i.e., form many in the upper surface of the adhesive layer 2
The chip structure 3 of individual parallel arranged.
As an example, the contact pad 32 is by one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material group
Into.
As shown in figure 3, plastic packaging layer 4 is formed in the upper surface of adhesive layer 2, the cladding chip structure of plastic packaging layer 4
3。
As an example, the material of the plastic packaging layer 4 includes polyimides, silica gel or epoxy resin；Filled out using molding bottom
Fill technique and form the plastic packaging layer 4 in the upper surface of the adhesive layer 2, wherein, the parcel chip structure 3 of plastic packaging layer 4；
The plastic packaging layer 4 is formed in the upper surface of the adhesive layer 2 by using molded underfill technique, capsulation material can be with smooth
And the gap promptly filled up between each chip structure 3, it is prevented effectively from and interface debonding occurs.
As shown in figure 4, the carrier 1 and the adhesive layer 2 are removed, to expose the chip structure 3.
As an example, removing the carrier 1 and the bonding using grinding technics, reduction process, wet corrosion technique etc.
Layer 2.
As shown in figure 5, the first dielectric layer 5 is formed on 4 surface of plastic packaging layer for exposing the chip structure 3, and to described
First dielectric layer 5 carries out photoetching, to form the first opening 6 for exposing the contact pad 32.
As an example, first dielectric layer 5 be low k dielectric, its material be epoxy resin, silica gel, PI, PBO,
One kind in BCB, silica, phosphorosilicate glass and fluorine-containing glass, it is possible to using spin coating, CVD, plasma enhanced CVD etc.
Technique is prepared.
As an example, one layer of photoresist first is coated on the surface of the first dielectric layer 5, and by mask plate to the photoetching
Glue carries out light shield development, forms litho pattern, then first dielectric layer 5 is performed etching by litho pattern, to form the
One opening 6, finally removes photoresist, obtains structure shown in Fig. 5.
As shown in fig. 6, re-wiring layer 7 is formed on the surface of the first dielectric layer 5 and the surface of contact pad 32, and to institute
State re-wiring layer 7 and carry out photoetching, to form the second opening 8 for exposing first dielectric layer 5.
As an example, forming the method for the re-wiring layer 7 includes：
6.1) insulating barrier 71 is formed on the surface of the first dielectric layer 5 and the surface of contact pad 32, and to the insulating barrier
71 carry out photoetching, to expose the contact pad 32；
6.2) in the surface of insulating barrier 71 and the forming metal layer on surface 72 of contact pad 32.
As another example, forming the method for the re-wiring layer 7 includes：
The lamination knot of insulating barrier 71 and metal level 72 is alternatively formed in first dielectric layer 5 and the surface of contact pad 32
Structure, the top layer of the laminated construction is metal level, and the first layer metal layer of the laminated construction is carried out with the contact pad
Electrical connection, adjacent two layers metal level is electrically connected by the metal plug through respective insulation layers, wherein, described alternate time
Number is not less than 2 times
As an example, the material of the insulating barrier 71 is silica or PET (polyethylene terephthalate), pass through
The techniques such as spin coating, chemical vapor deposition method (CVD), plasma enhanced CVD are prepared.
As an example, the metal level 72 and the metal plug by one kind in copper, aluminium, nickel, gold, silver, tin, titanium or
Two or more materials composition, by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering, electroplate or
Chemical plating is prepared.
Preferably, in the present embodiment, using the method formation re-wiring layer 7 described in the first example, wherein, it is described heavy
New route layer 7 includes layer of metal layer 72；It is further preferred that the thickness of the metal level 72 is 10~15um.
As an example, one layer of photoresist first is coated on the surface of metal level 72, and by mask plate to the photoresist
Light shield development is carried out, litho pattern is formed, then the metal level 72 is performed etching by litho pattern, to form the second opening
8, finally remove photoresist, obtain structure shown in Fig. 6.
As shown in fig. 7, forming the second dielectric layer 9 on the surface of 7 and first dielectric layer of re-wiring layer 5.
As an example, second dielectric layer 9 be low k dielectric, its material be epoxy resin, silica gel, PI, PBO,
One kind in BCB, silica, phosphorosilicate glass and fluorine-containing glass, it is possible to using spin coating, CVD, plasma enhanced CVD etc.
Technique is prepared.
As shown in figure 8, carrying out laser ablation on the surface of the second dielectric layer 9, the rewiring is exposed to be formed
3rd opening 10 of layer 7.
As an example, the step of carrying out laser ablation includes：
As shown in figure 9, performed etching using laser etching process to second dielectric layer 9 and re-wiring layer 7, with
The first inverted trapezoidal opening 101 is formed in second dielectric layer 9 and re-wiring layer 7；
As shown in Figure 10, the bottom of the first inverted trapezoidal opening 101 is performed etching using laser etching process, with
Second inverted trapezoidal opening 102 is formed on the bottom of first inverted trapezoidal, wherein, the lower length of side of the first inverted trapezoidal opening 101
More than the upper length of side of the second inverted trapezoidal opening 102.
And 8.2) as an example, 8.1) wavelength of laser is 193~532nm in laser etching process in.
As an example, the upper length of side of the lower length of side of the first inverted trapezoidal opening 101 and the second inverted trapezoidal opening 102
Difference be that 40~600um, i.e. 2L are 40~600um, L is 20~300um.
As an example, the thickness d of residual metallic layer 72 is 5~6um after etching.
It should be noted that the energy size (i.e. etching depth) of laser and metal level 72 in laser etching process twice
Thickness is related, does not have specific requirement to the etching depth of metal level 72 in each laser etching process, as long as ensureing by twice
After laser etching process, the hatch frame being made up of two inverted trapezoidal openings can be formed in metal level 72.By this
Hatch frame substitutes UBM layer, when making 112 projection 11 of soldered ball subsequently in the opening, not only passes through the distinctive knot of the opening
Structure adds the cohesive between the projection 11 of soldered ball 112 and re-wiring layer 7, also effectively prevent and locates in ball reflux course is planted
It is moved in the soldered ball 112 of globule state and position skew occurs, it is ensured that the quality of encapsulating structure；More avoid simultaneously
UBM series of process step is made on second dielectric layer 9, production cost is reduced.
As shown in figure 11, soldered ball projection 11 is formed on the described 3rd 10 surfaces of opening.
As an example, the step of forming soldered ball projection 11 includes first forming metal column on the described 3rd 10 surfaces of opening
111, then form soldered ball 112 in the metal column 111 and the surface of re-wiring layer 7.
As an example, the metal column 111 is by one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material group
Into, pass through physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering, plating or chemical plating in one kind
Prepare.
As an example, the soldered ball 112 is made up of one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material,
Prepared by planting ball reflux technique.
Embodiment two
As shown in figure 11, the present embodiment provides a kind of fan-out-type list die package structure, and the encapsulating structure includes：
Chip structure 3, the chip structure 3 include bare chip 31 and on the bare chip 31 and with the naked core
The contact pad 32 that piece 31 is electrically connected；
The chip structure 3 is surrounded, while exposing the plastic packaging layer 4 on the place surface of contact pad 32；
The first dielectric layer 5 positioned at plastic packaging layer 4 and the upper surface of chip structure 3, first dielectric layer 5 passes through first
Opening 6 exposes the contact pad 32；
Re-wiring layer 7 positioned at first dielectric layer 5 and the upper surface of contact pad 32, the re-wiring layer 7 leads to
Cross the second opening 8 and expose first dielectric layer 5；
The second dielectric layer 9 positioned at the upper surface of 7 and first dielectric layer of re-wiring layer 5, second dielectric layer 9 leads to
Cross the 3rd opening 10 and expose the re-wiring layer 7；And
Positioned at the soldered ball projection 11 of the described 3rd opening 10.
As an example, the quantity of the chip structure 3 is more than or equal to 1, i.e., described plastic packaging layer 4 surrounds multiple parallel simultaneously
The chip structure 3 of arrangement.
As an example, the contact pad 32 is by one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material group
Into.
As an example, the material of the plastic packaging layer 4 includes polyimides, silica gel or epoxy resin.
As an example, first dielectric layer 5 be low k dielectric, its material be epoxy resin, silica gel, PI, PBO,
One kind in BCB, silica, phosphorosilicate glass and fluorine-containing glass.
As an example, the re-wiring layer 7 includes：
Insulating barrier 71 positioned at first dielectric layer 5 and the upper surface of contact pad 32, the insulating barrier 71 is provided with sudden and violent
Expose the opening of the contact pad 32；And
Metal level 72 positioned at the insulating barrier 71 and the upper surface of contact pad 32.
As another example, the re-wiring layer 7 includes：
Constituted positioned at first dielectric layer 5 and the surface of contact pad 32, by alternate insulating barrier 71 and metal level 72
Laminated construction, the top layer of the laminated construction is metal level, and the first layer metal layer and the Contact welding of the laminated construction
Disk is electrically connected, and adjacent two layers metal level is electrically connected by the metal plug through respective insulation layers, wherein, it is described to hand over
The number of times replaced is not less than 2 times.
As an example, the material of the insulating barrier 71 is silica or PET (polyethylene terephthalate).
As an example, the metal level 72 and the metal plug by one kind in copper, aluminium, nickel, gold, silver, tin, titanium or
Two or more material compositions.
Preferably, in the present embodiment, the structure of the re-wiring layer 7 such as the first example, i.e., described re-wiring layer 7
Including layer of metal layer 72；The thickness of the metal level 72 is 10~15um；It is further preferred that in the present embodiment, it is described
The thickness of metal level 72 is 12um.
As an example, second dielectric layer 9 be low k dielectric, its material be epoxy resin, silica gel, PI, PBO,
One kind in BCB, silica, phosphorosilicate glass and fluorine-containing glass.
As an example, it is described 3rd opening 10 include the first inverted trapezoidal opening 101, and with the first inverted trapezoidal opening
Second inverted trapezoidal opening 102 of 101 insertions, wherein, the following long ladder that fallen more than described second of the first inverted trapezoidal opening 101
The upper length of side of shape opening 102.
As an example, the upper length of side of the lower length of side of the first inverted trapezoidal opening 101 and the second inverted trapezoidal opening 102
Difference be that 40~600um, i.e. 2L are 40~600um, L is 20~300um.
As an example, the thickness d of residual metallic layer 72 is 5~6um after etching.
It should be noted that UBM layer is substituted by the hatch frame, when the making projection of soldered ball 112 subsequently in the opening
When 11, the cohesive between the projection 11 of soldered ball 112 and re-wiring layer 7 is not only added by the distinctive structure of the opening, also
The soldered ball 112 in globule state in ball reflux course is planted is effectively prevent to be moved and position skew occur, it is ensured that
The quality of encapsulating structure；The processing step that UBM is made on the second dielectric layer 9 is more avoided simultaneously, reduces production cost.
As an example, the soldered ball projection 11 includes the metal column 111 for being located at the described 3rd 10 bottoms of opening, and positioned at institute
State the soldered ball 112 on metal column 111 and re-wiring layer 7.
As an example, the metal column 111 is by one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material group
Into.
As an example, the soldered ball 112 is made up of one or both of copper, aluminium, nickel, gold, silver, tin, titanium above material.
In summary, fan-out-type list die package structure of the invention and preparation method thereof, has the advantages that：It is logical
Preparation method of the present invention is crossed, while single nude film fan-out package is realized, also by second dielectric layer 9 and again
New route layer 7 carries out laser ablation, to form the 3rd opening being made up of two inverted trapezoidal openings in the re-wiring layer 7
10, to substitute the UBM layer of existing encapsulating structure, and by making the projection 11 of soldered ball 112 in the described 3rd opening 10, not only increase
The cohesive between the projection 11 of soldered ball 112 and re-wiring layer 7 is added, also effectively prevent and ball is in ball reflux course is planted
The soldered ball 112 of drop-wise state is moved and position skew occurs, it is ensured that the quality of encapsulating structure；Avoid and be situated between second simultaneously
By coating photoresist, making light shield mask, exposure imaging, formation litho pattern, the second dielectric layer 9 of etching, formation in electric layer 9
UBM, the processing step such as remove photoresist make UBM process, not only shorten processing time, also reduce production cost.So, this hair
It is bright effectively to overcome various shortcoming of the prior art and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (13)
1. a kind of preparation method of fan-out-type list die package structure, it is characterised in that the preparation method includes：
1) carrier is provided, an adhesive layer is formed in the upper surface of the carrier；
2) chip structure is formed in the adhesive layer upper surface, the chip structure includes bare chip and positioned at the bare chip
Contact pad that is upper and being electrically connected with the bare chip；
3) plastic packaging layer, the plastic packaging layer cladding chip structure are formed in the adhesive layer upper surface；
4) carrier and the adhesive layer are removed, to expose the chip structure；
5) plastic packaging layer surface the first dielectric layer of formation of the chip structure is being exposed, and light is carried out to first dielectric layer
Carve, to form the first opening for exposing the contact pad；
6) re-wiring layer is formed in first dielectric layer surface and contact pad surface, and the re-wiring layer is carried out
Photoetching, to form the second opening for exposing first dielectric layer；
7) in the re-wiring layer and the first dielectric layer surface the second dielectric layer of formation；
8) laser ablation is carried out in second dielectric layer surface, to form the 3rd opening for exposing the re-wiring layer；
9) in the 3rd open surfaces formation soldered ball projection.
2. the preparation method of fan-out-type list die package structure according to claim 1, it is characterised in that institute is formed in 6)
Stating the method for re-wiring layer includes：
6.1) insulating barrier is formed in first dielectric layer surface and contact pad surface, and photoetching is carried out to the insulating barrier,
To expose the contact pad；
6.2) in the surface of insulating layer and contact pad forming metal layer on surface.
3. the preparation method of fan-out-type list die package structure according to claim 1, it is characterised in that institute is formed in 6)
Stating the method for re-wiring layer includes：
The laminated construction of insulating barrier and metal level, the lamination knot are alternatively formed in first dielectric layer and contact pad surface
The top layer of structure be metal level, and the laminated construction first layer metal layer be electrically connected with the contact pad, adjacent two
Layer metal level is electrically connected by the metal plug through respective insulation layers, wherein, the alternate number of times is not less than 2
It is secondary.
4. the preparation method of fan-out-type list die package structure according to claim 1, it is characterised in that swashed in 8)
The step of photoengraving, includes：
8.1) second dielectric layer and re-wiring layer are performed etching using laser etching process, with second dielectric
The first inverted trapezoidal opening is formed in layer and re-wiring layer；
8.2) bottom of the first inverted trapezoidal opening is performed etching using laser etching process, with first inverted trapezoidal
Bottom form the second inverted trapezoidal opening, wherein, the following length of the first inverted trapezoidal opening is opened more than second inverted trapezoidal
The upper length of side of mouth.
5. the preparation method of fan-out-type list die package structure according to claim 4, it is characterised in that laser ablation work
The wavelength of laser is 193~532nm in skill.
6. the preparation method of fan-out-type list die package structure according to claim 4, it is characterised in that described first falls
The difference of the upper length of side of the lower length of side of trapezoid-shaped openings and the second inverted trapezoidal opening is 40~600um.
7. the preparation method of fan-out-type list die package structure according to claim 1, it is characterised in that weldering is formed in 9)
The step of ball projection, is included first in the 3rd open surfaces formation metal column, then in the metal column and re-wiring layer table
Face forms soldered ball.
8. a kind of fan-out-type list die package structure, it is characterised in that the encapsulating structure includes：
Chip structure, the chip structure includes bare chip and is electrically connected on the bare chip and with the bare chip
The contact pad connect；
The chip structure is surrounded, while the plastic packaging layer on surface where exposing the contact pad；
The first dielectric layer positioned at plastic packaging layer and chip structure upper surface, first dielectric layer is exposed by the first opening
Go out the contact pad；
Re-wiring layer positioned at first dielectric layer and contact pad upper surface, the re-wiring layer passes through the second opening
Expose first dielectric layer；
The second dielectric layer positioned at the re-wiring layer and the first dielectric layer upper surface, second dielectric layer is opened by the 3rd
Mouth exposes the re-wiring layer；And
Positioned at the soldered ball projection of the described 3rd opening.
9. fan-out-type list die package structure according to claim 8, it is characterised in that the re-wiring layer includes：
Insulating barrier positioned at first dielectric layer and contact pad upper surface, the insulating barrier, which is provided with, exposes the contact
The opening of pad；And
Metal level positioned at the insulating barrier and contact pad upper surface.
10. fan-out-type list die package structure according to claim 8, it is characterised in that the re-wiring layer includes：
The laminated construction constituted positioned at first dielectric layer and contact pad surface, by alternate insulating barrier and metal level, institute
The top layer of laminated construction is stated for metal level, and the first layer metal layer of the laminated construction is electrically connected with the contact pad
Connect, adjacent two layers metal level is electrically connected by the metal plug through respective insulation layers, wherein, the alternate number of times is
Not less than 2 times.
11. fan-out-type list die package structure according to claim 8, it is characterised in that the 3rd opening includes the
One inverted trapezoidal opening, and the second inverted trapezoidal opening with the first inverted trapezoidal opening insertion, wherein, first inverted trapezoidal is opened
The following long upper length of side more than the second inverted trapezoidal opening of mouth.
12. fan-out-type list die package structure according to claim 11, it is characterised in that the first inverted trapezoidal opening
The lower length of side and the second inverted trapezoidal opening the upper length of side difference be 40~600um.
13. fan-out-type list die package structure according to claim 8, it is characterised in that the soldered ball projection includes position
In the metal column of the 3rd open bottom, and the soldered ball on the metal column and re-wiring layer.
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| CN201710475741.9A CN107104058A (en) | 2017-06-21 | 2017-06-21 | Fan-out-type list die package structure and preparation method thereof |
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| CN201710475741.9A CN107104058A (en) | 2017-06-21 | 2017-06-21 | Fan-out-type list die package structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Applicant after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Applicant before: SJ Semiconductor (Jiangyin) Corp. |
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Application publication date: 20170829 |