CN111180382A - Wafer-level device integration method and structure - Google Patents
Wafer-level device integration method and structure Download PDFInfo
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- CN111180382A CN111180382A CN201811347414.6A CN201811347414A CN111180382A CN 111180382 A CN111180382 A CN 111180382A CN 201811347414 A CN201811347414 A CN 201811347414A CN 111180382 A CN111180382 A CN 111180382A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The invention provides a wafer level device integration method and an integration structure, wherein the method comprises the following steps: bonding a plurality of elements to be integrated on the bearing part at intervals to form a plastic package layer covering the bearing part and the elements to be integrated, removing the bearing part, bonding one surface of the plastic package layer far away from the elements to be integrated with the first substrate to form a first wiring layer covering the first substrate and connected with the elements to be integrated, bonding the first substrate with the second substrate, forming a plurality of first via holes and a plurality of second via holes on a second substrate, the first via holes exposing the device structure, the second via holes exposing the first wiring layer, forming a second wiring layer, the second wiring layer being connected to the device structure and the first wiring layer through the first via holes and the second via holes, respectively, so that the element to be integrated and the device structure are interconnected in a direction perpendicular to the second substrate, 3D integration is achieved, therefore, the area of the formed integrated structure can be greatly reduced, the manufacturing cost is reduced, and the performance of the integrated structure is optimized.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a wafer level device integration method and an integration structure.
Background
SiP (System in Package) is a System or subsystem that combines a plurality of active components and passive components with different functions, micro-electromechanical systems (MEMS), optical components, and other components into a single unit to provide a multi-functional System or subsystem, allowing heterogeneous IC (integrated circuit) integration, which is the best for Package integration. Compared with SoC (System on Chip ), the SiP integration is relatively simple, the design period and the market period are shorter, the cost is lower, and a more complex system can be realized.
Compared with the conventional SiP, the WLP (wafer level package) directly completes the packaging process on the wafer, has the advantages of greatly reducing the area of the packaging structure, reducing the manufacturing cost, optimizing the electrical performance, performing batch manufacturing and the like, and can obviously reduce the workload and the requirement of equipment.
With the higher integration of electronic devices, the market also demands microelectronic products with small volume, high density and thin package, and the requirements for the electrical properties of the microelectronic products are also continuously increased. Therefore, it is an urgent need to provide a wafer level device integration method and an integrated structure to reduce the area of the integrated structure, optimize the performance of the integrated structure, and reduce the manufacturing cost.
Disclosure of Invention
The invention aims to provide a wafer level device integration method and an integration structure, which can greatly reduce the area of the formed integration structure, reduce the manufacturing cost and optimize the performance of the integration structure.
In order to achieve the above object, the present invention provides a wafer level device integration method, comprising the following steps:
temporarily bonding a plurality of elements to be integrated on the bearing part at intervals;
forming a plastic packaging layer, wherein the plastic packaging layer covers the bearing part and the element to be integrated;
removing the bearing part, and bonding one surface of the plastic packaging layer, which is far away from the element to be integrated, with the first substrate;
forming a first wiring layer on the plastic packaging layer and connecting the first wiring layer with the element to be integrated;
bonding the surface of the first substrate, on which the first wiring layer is formed, with the surface of the second substrate, on which the plurality of device structures are formed;
forming a plurality of first through holes and a plurality of second through holes on the second substrate, wherein the first through holes expose the device structure, and the second through holes expose the first wiring layer; and the number of the first and second groups,
and forming a second wiring layer, wherein the second wiring layer is connected with the device structure through the first through hole and is connected with the first wiring layer through the second through hole so as to interconnect the element to be integrated and the device structure in a direction vertical to the first substrate.
Optionally, the method further includes:
forming a passivation layer covering the second wiring layer and the second substrate;
forming a plurality of passivation layer openings in the passivation layer, the passivation layer openings exposing the second wiring layer; and the number of the first and second groups,
and removing the first substrate.
Optionally, after the plastic package layer is formed, the bearing part is removed, and then the plastic package layer is bonded with the first substrate; alternatively, the first and second electrodes may be,
after the plastic packaging layer is formed, the plastic packaging layer is bonded with the first substrate, and then the bearing part is removed.
Optionally, the to-be-integrated element has a front surface and a back surface, and the front surface of the to-be-integrated element is fixed on the bearing part.
Optionally, the plurality of components to be integrated are fixed on the bearing part at intervals by a glue layer.
Optionally, the glue layer comprises an adhesive sheet film or a dry film.
Optionally, the plastic package layer is formed by a hot-press injection molding process.
Optionally, before bonding the molding compound layer and the first substrate, the method further includes: and forming a first bonding layer on the plastic packaging layer or the bonding surface of the first substrate.
Optionally, the step of forming a first wiring layer on the to-be-integrated element includes:
forming an insulating layer, wherein the insulating layer covers the element to be integrated and the plastic packaging layer;
forming a plurality of insulating layer openings in the insulating layer, the insulating layer openings exposing the components to be integrated; and
and filling a conductive material in the insulating layer opening to form a first wiring layer, wherein the first wiring layer is connected with the element to be integrated through the insulating layer opening.
Optionally, before bonding the first substrate and the second substrate, the method further includes: and forming a second bonding layer on the bonding surface of the first substrate or the second substrate.
Optionally, the step of forming a plurality of first through holes and a plurality of second through holes on the second substrate includes:
forming a patterned mask layer on the second substrate;
etching the second substrate by taking the patterned mask layer as a mask to form a plurality of first through holes exposing the device structure and a plurality of third through holes exposing the second bonding layer;
and etching the exposed second bonding layer until the first wiring layer is exposed so as to form a second through hole in the third through hole.
Optionally, the second substrate is etched by a reactive ion etching process, and the etching gas includes CF4、CF3And Ar, wherein CF4The flow rate of (1) is 5sccm to 15sccm, CF3The flow rate of the gas is 40sccm to 70sccm, the flow rate of Ar is 100sccm to 150sccm, the pressure of the chamber is 140mTorr to 160mTorr, the radio frequency power is 300w to 500w, and the etching time is 50s to 200 s;
etching the second bonding layer by reactive ion etching process, wherein the etching gas comprises O2And Ar, wherein O2The flow rate of the gas is 50sccm to 200sccm, the flow rate of Ar is 60sccm to 90sccm, the pressure of the chamber is 15mTorr to 35mTorr, and the etching time is 400s to 800 s.
Optionally, after bonding the first substrate and the second substrate, before forming the first through hole and the second through hole, the method further includes: and thinning one side of the second substrate, which is far away from the first substrate.
Optionally, a first pad is formed on the to-be-integrated element, and the first pad is used for being connected with the first wiring layer; a second pad is formed on the device structure, the second pad for connection with the second wiring layer.
Correspondingly, the invention also provides a wafer level device integration structure formed by the method, which comprises the following steps:
a plastic packaging layer;
the components to be integrated are fixed in the plastic packaging layer at intervals, and the surface of the components to be integrated is exposed out of the plastic packaging layer;
the first wiring layer is positioned on the element to be integrated and is connected with the element to be integrated;
the second substrate is positioned on the plastic packaging layer and the first wiring layer, a device structure is formed in the second substrate, and the device structure is positioned on one surface, close to the first wiring layer, in the second substrate; and the number of the first and second groups,
and the second wiring layer is connected with the device structure through a first through hole formed in the second substrate and is connected with the first wiring layer through a second through hole formed in the second substrate, so that the element to be integrated and the device structure are interconnected in a direction perpendicular to the second substrate.
Optionally, the method further includes: and the passivation layer is positioned on the second substrate and the second wiring layer and is provided with a passivation layer opening for exposing part of the second wiring layer.
Optionally, the method further includes: the first wiring layer is located on the insulating layer opening and connected with the element to be integrated.
Optionally, the method further includes: a second bonding layer between the insulating layer and the second substrate.
Compared with the prior art, in the wafer-level device integration method and the wafer-level device integration structure provided by the invention, a plurality of elements to be integrated are temporarily bonded on a bearing part at intervals to form a plastic package layer, the plastic package layer covers the bearing part and the elements to be integrated, then the bearing part is removed, one surface of the plastic package layer, which is far away from the elements to be integrated, is bonded with a first substrate, then a first wiring layer is formed, the first wiring layer covers the first substrate and is connected with the elements to be integrated, the first substrate with the first wiring layer formed thereon is bonded with a second substrate with a device structure formed thereon, and then a plurality of first through holes and second through holes are formed on the second substrate, wherein the first through holes expose the device structure, and the second through holes expose the first wiring layer; and forming a second wiring layer connected with the device structure through the first via hole and connected with the first wiring layer through a second via hole so as to interconnect the element to be integrated and the device structure in a direction perpendicular to the second substrate. The invention realizes the connection of the element to be integrated and the device structure in the direction vertical to the second substrate, and realizes 3D integration, thereby greatly reducing the area of the formed integrated structure, reducing the manufacturing cost and optimizing the performance of the integrated structure.
Furthermore, the invention combines the wafer level package and the system level package, thereby realizing the integration of a plurality of elements to be integrated and a plurality of device structures, realizing the package manufacture on the substrate, and combining the advantages of the wafer level package and the system level package, thereby further reducing the area of the formed integrated structure, reducing the manufacturing cost and optimizing the performance of the integrated structure.
Drawings
Fig. 1 is a flowchart of a device integration method according to an embodiment of the present invention.
Fig. 2 to 11 are schematic structural diagrams of steps of a device integration method according to an embodiment of the present invention.
Detailed Description
The inventor has found that the system-in-package has the advantages of being relatively simple, shorter in design period and market period, lower in cost, capable of realizing a more complex system and the like, the wafer-level package has the advantages of greatly reducing the area of a package structure, reducing manufacturing cost, optimizing electrical performance, manufacturing in batches and the like, and if the wafer-level package and the system-in-package are integrated, the advantages of the wafer-level package and the system-in-package can be combined. Furthermore, the invention temporarily bonds a plurality of elements to be integrated on a bearing part at intervals to form a plastic package layer, the plastic package layer covers the bearing part and the elements to be integrated, then removes the bearing part, bonds one surface of the plastic package layer, which is far away from the elements to be integrated, with a first substrate, then forms a first wiring layer, the first wiring layer covers the first substrate and is connected with the elements to be integrated, bonds one surface of the first substrate, which is provided with the first wiring layer, with one surface of a second substrate, which is provided with a plurality of device structures, and forms a plurality of first through holes and second through holes on the second substrate, wherein the first through holes expose the device structures, and the second through holes expose the first wiring layer; and forming a second wiring layer connected with the device structure through the first via hole and connected with the first wiring layer through the second via hole to interconnect the element to be integrated and the device structure in a direction perpendicular to the second substrate. The invention realizes the connection of the element to be integrated and the device structure in the direction vertical to the second substrate, and realizes 3D integration, thereby greatly reducing the area of the formed integrated structure, reducing the manufacturing cost and optimizing the performance of the integrated structure.
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.
Fig. 1 is a flowchart illustrating a wafer level device integration method according to an embodiment of the invention. As shown in fig. 1, an embodiment of the present invention provides a device integration method, including the following steps:
step S100: temporarily bonding a plurality of elements to be integrated on the bearing part at intervals;
step S200: forming a plastic packaging layer, wherein the plastic packaging layer covers the bearing part and the element to be integrated;
step S300: removing the bearing part, and bonding one surface of the plastic packaging layer, which is far away from the element to be integrated, with the first substrate;
step S400: forming a first wiring layer on the plastic packaging layer and connecting the first wiring layer with the element to be integrated;
step S500: bonding the surface of the first substrate, on which the first wiring layer is formed, with the surface of the second substrate, on which the device structure is formed;
step S600: forming a plurality of first through holes and a plurality of second through holes on the second substrate, wherein the first through holes expose the device structure, and the second through holes expose the first wiring layer;
step S700: and forming a second wiring layer, wherein the second wiring layer is connected with the device structure through the first through hole and is connected with the first wiring layer through the second through hole so as to interconnect the element to be integrated and the device structure in a direction vertical to the second substrate.
Fig. 2 to 11 are schematic structural diagrams of steps of a wafer level device integration method according to an embodiment of the invention, and the device integration method according to the invention will be described in detail below with reference to fig. 2 to 11.
In step S100, a carrier 10 is provided, and a plurality of to-be-integrated devices 20 are temporarily bonded to the carrier 10 at intervals, so as to form the structure shown in fig. 2.
The bearing part 10 is a plate-shaped structure, and the bearing part 10 is preferably a glass substrate, so that better hardness and flatness can be provided, and the failure rate of the integrated device can be reduced. In addition, since the bearing part 10 is removed in the subsequent steps, the bearing part made of glass is easy to peel off and has strong corrosion resistance, and the physical or chemical properties of the bearing part are not changed due to the subsequent contact with the cementing layer, so that the bearing part can be repeatedly used. Of course, the carrier 10 may also be a sapphire substrate, a silicon substrate, or other substrates known to those skilled in the art, which is not limited in the present invention. The shape of the carrying part 10 may be circular, rectangular, triangular or other shapes, and the invention does not limit the shape of the carrying part 10.
The bearing part 10 is formed with a glue layer 11, and the glue layer 11 is used for adhering and fixing the component 20 to be integrated on the bearing part 10. The glue layer 11 may be an organic material, and may be coated on the bearing portion 10 by spin coating, spraying, rolling, printing, vacuum lamination, or pressure lamination. The adhesive layer 11 is a temporary adhesive layer, and may be a thermoplastic or thermosetting organic material, or an inorganic material containing Cu, Ni, Cr, Co, or the like, and may be removed by heating, mechanical, chemical, laser, freezing, or the like.
These elements 20 to be integrated may be all chips, all passive devices, or a combination of chips and passive devices, which is selected according to the actual situation. The passive devices include but are not limited to capacitors, inductors, resistors, etc., and the chips may also be chips with different functions. The component 20 to be integrated includes a front surface and a back surface disposed corresponding to the front surface, the front surface of the component 20 to be integrated may be formed with a first pad 20 'for electrically connecting with an external circuit, when the component 20 to be integrated is fixed on the carrier 10, the front surface of the component 20 to be integrated faces a direction close to the carrier 10 (i.e., the first pad 20' is in contact with the carrier 10), and the back surface faces a direction away from the carrier 10.
The plurality of components 20 to be integrated may be distributed on the carrier 10 in an array, and the spacing distances between the components 20 to be integrated are the same. Of course, the distribution of the components 20 to be integrated can also be adjusted according to actual needs in specific implementation.
In step S200, please refer to fig. 2 again, a molding compound layer 30 is formed on the carrier portion 20, and the molding compound layer 30 covers the carrier portion 10 and the to-be-integrated component 20.
Specifically, the carrier 10 with the component 20 to be integrated fixed thereon is subjected to plastic molding and curing, so as to form the plastic molding layer 30. In a preferred embodiment of the invention, plastic packaging is performed by adopting a hot-press injection molding process. The molding compound layer 30 covers the carrier 10 (specifically, the glue layer 11 on the carrier 10) and the component 20 to be integrated at the same time. Further, the area of the molding layer 30 may be the same as the area of the load-bearing part 10, so as to cover the entire load-bearing part 10; the molding layer 30 may also have an area smaller than that of the carrying portion 10, so as to cover a part of the surface of the carrying portion 10, as shown in fig. 2, and the edge region of the carrying portion 10 is exposed.
The molding compound layer 30 includes thermosetting resin, which can soften or flow during the molding process, has plasticity, can be formed into a certain shape, and simultaneously undergoes a chemical reaction to be cross-linked and cured, the molding compound layer 30 may include at least one of thermosetting resin such as phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, polyimide, etc., wherein, the epoxy resin is preferably used as the molding compound layer, wherein the epoxy resin may be epoxy resin with or without filler, and various additives (for example, curing agent, modifier, release agent, thermal colorant, flame retardant, etc.), for example, phenolic resin is used as the curing agent, and solid particles (for example, silicon micropowder) are used as the filler.
In step S300, please refer to fig. 3 and fig. 4, the carrier 10 is removed, and one surface of the molding compound layer 30 away from the component 20 to be integrated is bonded to the first substrate 40.
First, as shown in fig. 3, the injection-molded components 20 to be integrated remain, the components 20 to be integrated are fixed in the molding layer 30, and the molding layer 30 exposes the front surface of the components 20 to be integrated and exposes the first liner 20'. In a preferred embodiment of the present invention, the bearing part 10 can be removed by peeling, and the glue layer 11 is also removed. An appropriate removing method is selected according to the bonding method used, for example, when the material of the bonding layer 11 is an adhesive sheet film or a dry film, the bonding layer 11 may be denatured by high temperature or ultraviolet irradiation to lose its adhesiveness, so as to peel the carrier part 10.
Next, referring to fig. 4, a surface of the molding compound layer 30 away from the to-be-integrated component 20 is bonded to a first substrate 40 to expose the to-be-integrated component 20.
Specifically, a first substrate 40 is provided, the first substrate 40 is a monolithic wafer substrate, and the material of the first substrate 40 may be a silicon substrate, or may be a germanium, silicon germanium, gallium arsenide substrate or a silicon-on-insulator substrate. The first substrate may be selected as desired by those skilled in the art, and thus the type of the first substrate should not limit the scope of the present invention. The first substrate 40 in this embodiment is preferably a silicon substrate. The first substrate 40 may have a shape conforming to the carrier 10 so as to bond with the molding layer 30 formed on the carrier 10. The first substrate 40 is mainly used for supporting the molding layer 30 and the component 20 to be integrated, and no device structure needs to be formed thereon, and finally the first substrate 40 is removed.
Bonding of the molding layer 30 and the first substrate 40 may be achieved by any suitable method. In one example, the molding layer 30 and the first substrate 40 are bonded together by a fusion bonding process, preferably a low temperature fusion bonding process is used to avoid the failure of the device caused by the bonding process with too high temperature, wherein the temperature of the low temperature fusion bonding process may be lower than 400 ℃, for example, the temperature of the low temperature fusion bonding process is between 100 ℃ and 250 ℃, so that the molding layer 30 and/or the first substrate 40 are fused and bonded together.
In one example, the molding layer 30 and the first substrate 40 may also be bonded together by forming a bonding layer, such as: before bonding, a first bonding layer 41 is firstly formed on a side of the plastic package layer 30 away from the component to be integrated 20, that is, on a bonding surface of the plastic package layer 30, or a first bonding layer 41 is formed on a bonding surface of the first substrate 40, and then the bonding surface of the plastic package layer 30 and the bonding surface of the first substrate 40 are bonded together. The first bonding layer 41 includes, but is not limited to, an oxide layer, such as a silicon oxide layer. In the present embodiment, a silicon oxide layer is formed on the bonding surface of the first substrate 40 by thermally oxidizing the first substrate 40. In other embodiments, the silicon oxide layer may also be formed using a deposition process, or other processes known to those skilled in the art.
In one example, the molding layer 30 and the first substrate 40 may be bonded together by an adhesion process, such as bonding the molding layer and the first substrate together by an adhesive layer, which may be an organic film, which may include various organic film layers, such as a sticker film, a dry film, a photoresist, or the like. The thickness of the adhesive layer is set as required, and the number of the adhesive layers is not limited to one, and may be two or more. The two surfaces of the adhesive layer have adhesiveness, one surface is adhered to the surface of the molding layer 30, and the other surface is adhered to the surface of the first substrate 40, so as to fix the molding layer 30 on the first substrate 40, and realize the physical connection between the molding layer 30 and the first substrate 40.
In this embodiment, the bonding is a temporary bonding, that is, the plastic package layer 30 and the first substrate 40 are separated in a subsequent process step.
It can be understood that, in this step, the bearing portion 10 may be removed, and then the surface of the molding compound layer 30 away from the component 20 to be integrated is bonded to the first substrate 40, or the surface of the molding compound layer 30 away from the component 20 to be integrated is bonded to the first substrate 40, and then the bearing portion 10 is removed.
In step S400, please refer to fig. 5, a first wiring layer 50 is formed on the molding layer 30, and the first wiring layer 50 is connected to the to-be-integrated component 20.
Specifically, first, an insulating layer 51 is formed on the molding compound layer 30 and the to-be-integrated element 20, the insulating layer 51 covers the to-be-integrated element 20 and the molding compound layer 30, and the material of the insulating layer 51 includes, but is not limited to, silicon oxide or silicon nitride. Next, the insulating layer 51 is etched, typically, a photoresist layer (not shown) is formed on the insulating layer 51, the photoresist layer is exposed and developed to form a patterned photoresist layer, and then the insulating layer 51 is etched by using the patterned photoresist layer as a mask to form an insulating layer opening exposing the to-be-integrated component 20, and preferably, the insulating layer opening exposes the first pad 20' on the front surface of the to-be-integrated component 20. Then, a conductive material layer is deposited on the insulating layer 51, the conductive material layer covers the insulating layer 51 and fills the insulating layer opening, and then the conductive material layer is etched until a part of the insulating layer 51 is exposed, so as to form a first wiring layer 50. The first wiring layer 50 fills the insulating layer opening and covers a portion of the insulating layer 51. And finally, removing the patterned photoresist layer. The first wiring layer 50 is connected to the element to be integrated 20 through the first pad 20'.
In step S500, please refer to fig. 6, the first substrate 40 formed with the first wiring layer 50 is bonded to the second substrate 60 formed with the device structure 61.
Specifically, in this step, first, a second substrate 60 is provided, and a plurality of device structures 61 are formed on the second substrate 60. The device structure 61 on the second substrate 60 is a device structure manufactured by providing a bare wafer and then designing according to a corresponding layout by using an integrated circuit manufacturing technology, that is, the second substrate 60 is a wafer on which device manufacturing is completed. For example, devices such as NMOS and/or PMOS devices, as well as interconnect layers formed by dielectric layers and metal layers and pads located above the interconnect layers, may be formed on a semiconductor wafer by deposition, etching, doping, etc., so as to fabricate at least one device structure in the semiconductor wafer.
Illustratively, the second substrate 60 may be at least one of the semiconductor materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like. The device structure 61 may be any semiconductor device structure, which may include active devices such as a memory, a logic circuit, a power device, a bipolar device, a single MOS transistor, a Micro Electro Mechanical System (MEMS), etc., or even optoelectronic devices such as a light emitting diode, etc., or passive devices such as a resistor, a capacitor, etc.
A second pad 61' is formed on each of the device structures 61 for connection to an external circuit. Next, a second bonding layer 52 is formed on the bonding surface of the first substrate 40, that is, on the insulating layer 51 and the first wiring layer 50, the second bonding layer 52 covers the insulating layer 51 and the first wiring layer 50, or the second bonding layer 52 is formed on the bonding surface of the second substrate 60, that is, on the side of the second substrate 60 on which the device structure 61 is formed, and then the first substrate 40 and the second substrate 60 are bonded. It should be noted that, this bonding is a permanent bonding, and after the insulating layer 51, the first wiring layer 50 and the second substrate 60 are bonded, they are not separated in the subsequent process steps.
In step S600, referring to fig. 7 and 8, a plurality of first vias 62 and a plurality of second vias 64 are formed on the second substrate 60, wherein the first vias 62 expose the device structures 61, and the second vias 64 expose the first wiring layer 50.
Preferably, referring to fig. 7, a side of the second substrate 60 away from the first substrate 40 is thinned, so that the thickness of the second substrate 60 is thinned, and difficulty of a subsequent etching process is reduced. The side of the second substrate 60 away from the first substrate 40 can be thinned to a desired thickness of the device by coarse grinding and fine grinding. Preferably, when the second substrate 60 is thinned, the thinning rate is reduced, for example, the thinning rate is reduced by half, when the predetermined distance is away from the device structure 61, and the predetermined distance is, for example, 5 μm. This is because, at the interface where the thickness of the second substrate is discontinuous, the rate drops to effectively reduce the micro-gaps, cracks and debris at the edge of the silicon wafer. And after the second substrate 60 is thinned to a preset thickness, wet etching can be carried out on the thinned second substrate 60, the stress of the thinned surface can be effectively released in the wet etching process, and the roughness of the surface of the second substrate 60 can be effectively improved.
Next, referring to fig. 8, the thinned surface of the second substrate 60 is etched to form a plurality of first through holes 62 and a plurality of second through holes 64. The first via 62 and the second via 64 may be formed using any suitable method, and in one example, a patterned mask layer (not shown) including, but not limited to, a photoresist layer may be first formed on the thinned surface of the second substrate 60, for example, by spin-coating a photoresist mask material on the thinned surface of the second substrate 60 to form a photoresist layer, and then patterning the photoresist layer using a photolithography process to form a patterned photoresist layer in which the location and critical dimensions of the via to be formed are defined. Then, using the patterned photoresist layer as a mask, a portion of the second substrate 60 is etched to form a plurality of first vias 62 exposing the device structure 61 and a plurality of third vias 63 exposing the second bonding layer 52. In this embodiment, the first via 62 exposes the second pad 61 'on the device structure 61, that is, the second pad 61' and the second bonding layer 52 serve as an etching stop layer. Then, the second bonding layer 52 exposed therein is continuously etched until the first wiring layer 50 is exposed, and the first wiring layer 50 serves as an etching stop layer, so as to form the second via hole 64 in the third via hole 63, wherein the second via hole exposes the first wiring layer 50. The etching process in this implementation may be a wet etching process or a dry etching process, wherein a dry etching process is preferably used, and the dry etching includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching or laser cutting, followed by removal of the patterned photoresist layer, for example using ashing.
Illustratively, the second substrate 60 is etched using a reactive ion etching process, wherein the etching gas comprises CF4、CF3And Ar, CF4The flow rate of (1) is 5sccm to 15sccm, CF3The flow rate of the gas is 40sccm to 70sccm, the flow rate of Ar is 100sccm to 150sccm, the pressure of the chamber is 140mTorr to 160mTorr, the radio frequency power is 300w to 500w, and the etching time is 50s to 200 s. With this etching method, it is possible to achieve a good etching selectivity between the second substrate 60 and the second pad 61' and the second bonding layer 52, and to provide a via with a good profile.
Illustratively, in this embodiment, the second bonding layer 52 is etched using a reactive ion etching process, and the etching gas includes O2And Ar, wherein O2The flow rate of the gas is 50sccm to 200sccm, the flow rate of Ar is 60sccm to 90sccm, the pressure of the chamber is 15mTorr to 35mTorr, and the etching time is 400s to 800 s. With this etching method, it is possible to achieve a good etching selection ratio between the second bonding layer 52 and the first wiring layer 50 and the second pad 61', and to make a via hole have a good profile.
In step S700, please refer to fig. 9, a second wiring layer 70 is formed, where the second wiring layer 70 is connected to the device structure 61 through the first via 62, and connected to the first wiring layer 50 through the second via 64, so as to interconnect the to-be-integrated component 20 and the device structure 61 in a direction perpendicular to the second substrate 60.
Specifically, a conductive material is deposited on the second substrate 60, the conductive material fills the first through hole 62 and the second through hole 64 and covers the second substrate 60, then the conductive material is etched to form second wiring layers 70, and each second wiring layer 70 fills the first through hole 62 and the second through hole 64 and partially covers the second substrate 60. A portion of the second wiring layer 70 is connected to the device structure 61 through the first via hole 62, and another portion of the second wiring layer 70 is connected to the first wiring layer 50 through the second via hole 64, and is finally connected to the to-be-integrated device 20. By the interconnection between the different second wiring layers 70, the interconnection of the element to be integrated 20 and the device structure 61 in the direction perpendicular to the second substrate 60 can be achieved.
After forming the second wiring layer 70, a passivation layer 80 may be formed on the second substrate 60, the passivation layer 80 covers the second wiring layer 70 and the second substrate 60, and then the passivation layer 80 is etched to form a plurality of passivation layer openings 80 ', the passivation layer openings 80' expose the second wiring layer 70, so as to form the structure shown in fig. 10.
Finally, please refer to fig. 11, the first substrate 40 is removed. Preferably, the first substrate 40 may be removed by a lift-off method, and the first bonding layer 41 is also removed.
In this embodiment, after the first substrate 40 and the second substrate 60 are bonded, a plurality of through holes 62 are formed on the second substrate 60, wherein a part of the through holes 62 expose the device structures 61, and another part of the through holes 62 expose the first wiring layer 50, and then a second wiring layer 70 is formed in the through holes 62, so that at least one of the chips 20 to be integrated is electrically connected to at least one of the device structures 61. In other embodiments, after bonding the first substrate 40 and the second substrate 60, plugs may be formed directly on the second substrate 60, wherein the plugs corresponding to the to-be-integrated components 20 are electrically connected to the to-be-integrated components 20, and the plugs corresponding to the device structures 61 are electrically connected to the device structures 61, so that the to-be-integrated components 20 and the device structures 61 are interconnected through two types of plugs. The present invention is not limited to the method and structure for implementing the interconnection.
In the wafer-level device integration method provided by the embodiment of the present invention, a plurality of to-be-integrated components 20 are temporarily bonded to a carrier 10 at intervals, a molding compound layer 30 is formed on the carrier 10, the molding compound layer 30 covers the carrier 10 and the to-be-integrated components 20, then the carrier 10 is removed, one surface of the molding compound layer 30 away from the to-be-integrated components 20 is bonded to a first substrate 40, a first wiring layer 50 is formed on the to-be-integrated components 20, the first wiring layer 50 is connected to the to-be-integrated components 20, the first substrate 40 on which first wirings 50 are formed is bonded to a second substrate 60 on which device structures 61 are formed, then a plurality of first through holes 62 and a plurality of second through holes 64 are formed on the second substrate 60, wherein the first through holes 62 expose the device structures 61, and the second through holes 64 expose the first wiring layer 50, and forming a second wiring layer 70 in the first through hole 62 and the second through hole 64, wherein the connection between the element 20 to be integrated and the device structure 61 in the direction perpendicular to the second substrate 60 can be realized through the second wiring layer 70, so that 3D integration is realized, the area of the formed integrated structure can be greatly reduced, the manufacturing cost is reduced, and the performance of the integrated structure is optimized.
Furthermore, the invention combines the wafer level packaging with the traditional system integration method, not only completes the integration of various elements to be integrated and the integration of the elements to be integrated and a plurality of device structures, but also realizes the packaging manufacture on the substrate, and combines the advantages of the wafer level packaging and the system level packaging, thereby further reducing the area of the formed integrated structure, reducing the manufacturing cost and optimizing the performance of the integrated structure.
Accordingly, the present invention further provides a wafer level device integration structure manufactured by the above device integration method, referring to fig. 11, the device integration structure includes:
a plastic sealing layer 30;
the components 20 to be integrated are fixed in the plastic package layer 30 at intervals, and the surface of the components 20 to be integrated is exposed out of the plastic package layer 30;
a first wiring layer 50 located on the element to be integrated 20 and connected to the element to be integrated 20;
a second substrate 60 located on the plastic package layer 30 and the first wiring layer 50, wherein a device structure 61 is formed in the second substrate 60, and the device structure 61 is located on a surface of the second substrate 60 close to the first wiring layer 50; and the number of the first and second groups,
a second wiring layer 70 connected to the device structure 61 through a first via hole 62 formed in the second substrate 60 and connected to the first wiring layer 50 through a second via hole 64 formed in the second substrate 60, so as to interconnect the element to be integrated 20 and the device structure 61 in a direction perpendicular to the second substrate 60.
Further, the device integration structure further includes a passivation layer 80, where the passivation layer 80 is located on the second substrate 60 and the second wiring layer 70 and has a passivation layer opening 81 exposing a portion of the second wiring layer 70, so as to facilitate connection of the second wiring layer 70 with an external circuit.
Further, the device integration structure further includes an insulating layer 52, the insulating layer 52 is located above the molding compound layer 30 and the to-be-integrated element 20, and has an insulating layer opening exposing the to-be-integrated element 20, and the first wiring layer 50 is connected to the to-be-integrated element 20 through the insulating layer opening.
Further, the device integrated structure further includes a second bonding layer 52, and the second bonding layer 52 is located between the insulating layer 52 and the second substrate 60.
In summary, in the wafer-level device integration method and the wafer-level device integration structure provided by the present invention, a plurality of devices to be integrated are temporarily bonded to a carrier at intervals to form a plastic package layer, the plastic package layer covers the carrier and the devices to be integrated, the carrier is removed, one surface of the plastic package layer away from the devices to be integrated is bonded to a first substrate, a first wiring layer is formed, the first wiring layer covers the first substrate and is connected to the devices to be integrated, the first substrate with the first wiring layer formed thereon is bonded to a second substrate with the device structure formed thereon, and a plurality of first through holes and a plurality of second through holes are formed on the second substrate, wherein the first through holes expose the device structure, and the second through holes expose the first wiring layer; and forming a second wiring layer connected with the device structure through the first via hole and connected with the first wiring layer through the second via hole so as to interconnect the element to be integrated and the device structure in a direction perpendicular to the second substrate. The invention realizes the connection of the element to be integrated and the device structure in the direction vertical to the second substrate, and realizes 3D integration, thereby greatly reducing the area of the formed integrated structure, reducing the manufacturing cost and optimizing the performance of the integrated structure.
Furthermore, the invention combines the wafer level package and the system level package, thereby realizing the integration of a plurality of elements to be integrated and a plurality of device structures, realizing the package manufacture on the substrate, and combining the advantages of the wafer level package and the system level package, thereby further reducing the area of the formed integrated structure, reducing the manufacturing cost and optimizing the performance of the integrated structure.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (18)
1. A wafer level device integration method is characterized by comprising the following steps:
temporarily bonding a plurality of elements to be integrated on the bearing part at intervals;
forming a plastic packaging layer, wherein the plastic packaging layer covers the bearing part and the element to be integrated;
removing the bearing part, and bonding one surface of the plastic packaging layer, which is far away from the element to be integrated, with the first substrate;
forming a first wiring layer on the plastic packaging layer and connecting the first wiring layer with the element to be integrated;
bonding the surface of the first substrate, on which the first wiring layer is formed, with the surface of the second substrate, on which the plurality of device structures are formed;
forming a plurality of first through holes and a plurality of second through holes on the second substrate, wherein the first through holes expose the device structure, and the second through holes expose the first wiring layer; and the number of the first and second groups,
and forming a second wiring layer, wherein the second wiring layer is connected with the device structure through the first through hole and is connected with the first wiring layer through the second through hole so as to interconnect the element to be integrated and the device structure in a direction vertical to the second substrate.
2. The device integration method of claim 1, further comprising:
forming a passivation layer covering the second wiring layer and the second substrate;
forming a plurality of passivation layer openings in the passivation layer, the passivation layer openings exposing the second wiring layer; and the number of the first and second groups,
and removing the first substrate.
3. The device integration method of claim 2, wherein after the molding compound layer is formed, the carrier is removed and then the molding compound layer is bonded to the first substrate; alternatively, the first and second electrodes may be,
after the plastic packaging layer is formed, the plastic packaging layer is bonded with the first substrate, and then the bearing part is removed.
4. The device integration method according to claim 1, wherein the component to be integrated has a front surface and a back surface, and the front surface of the component to be integrated is fixed on the carrier.
5. The device integration method according to claim 4, wherein a plurality of the components to be integrated are fixed on the bearing part at intervals by a glue layer.
6. The device integration method of claim 5, wherein the glue layer comprises an adhesive sheet film or a dry film.
7. The device integration method of claim 1, wherein the molding layer is formed using a hot-press injection molding process.
8. The device integration method of claim 1, further comprising, prior to bonding the molding layer to the first substrate:
and forming a first bonding layer on the plastic packaging layer or the bonding surface of the first substrate.
9. The device integration method according to claim 1, wherein the step of forming a first wiring layer on the element to be integrated includes:
forming an insulating layer, wherein the insulating layer covers the element to be integrated and the plastic packaging layer;
forming a plurality of insulating layer openings in the insulating layer, the insulating layer openings exposing the components to be integrated; and the number of the first and second groups,
and filling a conductive material in the insulating layer opening to form the first wiring layer, wherein the first wiring layer is connected with the element to be integrated through the insulating layer opening.
10. The device integration method of claim 1, further comprising, prior to bonding the first substrate to the second substrate:
and forming a second bonding layer on the bonding surface of the first substrate or the second substrate.
11. The device integration method of claim 10, wherein the step of forming a plurality of first vias and a plurality of second vias on the second substrate comprises:
forming a patterned mask layer on the second substrate;
etching the second substrate by taking the patterned mask layer as a mask to form a plurality of first through holes exposing the device structure and a plurality of third through holes exposing the second bonding layer;
and etching the exposed second bonding layer until the first wiring layer is exposed so as to form a second through hole in the third through hole.
12. The device integration method of claim 11, wherein the second substrate is etched using a reactive ion etching process, and an etching gas comprises CF4、CF3And Ar, wherein CF4The flow rate of (1) is 5sccm to 15sccm, CF3The flow rate of the gas is 40sccm to 70sccm, the flow rate of Ar is 100sccm to 150sccm, the pressure of the chamber is 140mTorr to 160mTorr, the radio frequency power is 300w to 500w, and the etching time is 50s to 200 s;
etching the second bonding layer by reactive ion etching process, wherein the etching gas comprises O2And Ar, wherein O2The flow rate of the gas is 50sccm to 200sccm, the flow rate of Ar is 60sccm to 90sccm, the pressure of the chamber is 15mTorr to 35mTorr, and the etching time is 400s to 800 s.
13. The device integration method of claim 1, after bonding the first substrate and the second substrate, and before forming the first via and the second via, further comprising:
and thinning one side of the second substrate, which is far away from the first substrate.
14. The device integration method according to claim 1, wherein a first pad for connecting with the first wiring layer is formed on the element to be integrated; a second pad is formed on the device structure, the second pad for connection with the second wiring layer.
15. A wafer level device integration structure fabricated by the device integration method of any one of claims 1 to 14, the device integration structure comprising:
a plastic packaging layer;
the components to be integrated are fixed in the plastic packaging layer at intervals, and the surface of the components to be integrated is exposed out of the plastic packaging layer;
the first wiring layer is positioned on the element to be integrated and is connected with the element to be integrated;
the second substrate is positioned on the plastic packaging layer and the first wiring layer, a device structure is formed in the second substrate, and the device structure is positioned on one surface, close to the first wiring layer, in the second substrate; and the number of the first and second groups,
and the second wiring layer is connected with the device structure through a first through hole formed in the second substrate and is connected with the first wiring layer through a second through hole formed in the second substrate, so that the element to be integrated and the device structure are interconnected in a direction perpendicular to the second substrate.
16. The device integration structure of claim 15, further comprising:
and the passivation layer is positioned on the second substrate and the second wiring layer and is provided with a passivation layer opening for exposing part of the second wiring layer.
17. The device integration structure of claim 16, further comprising:
the first wiring layer is connected with the element to be integrated through the insulating layer opening.
18. The device integration structure of claim 17, further comprising:
a second bonding layer between the insulating layer and the second substrate.
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