CN103383927A - Semiconductor encapsulation and forming method thereof - Google Patents

Semiconductor encapsulation and forming method thereof Download PDF

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Publication number
CN103383927A
CN103383927A CN2013101595306A CN201310159530A CN103383927A CN 103383927 A CN103383927 A CN 103383927A CN 2013101595306 A CN2013101595306 A CN 2013101595306A CN 201310159530 A CN201310159530 A CN 201310159530A CN 103383927 A CN103383927 A CN 103383927A
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China
Prior art keywords
layer
semiconductor chip
resilient coating
semiconductor
semiconductor packages
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CN2013101595306A
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Chinese (zh)
Inventor
朴辰遇
李锡贤
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020120046997A external-priority patent/KR20130123682A/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN103383927A publication Critical patent/CN103383927A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a semiconductor encapsulation and a forming method thereof. The semiconductor encapsulation comprises a buffer layer comprising at least one side wall covering a semiconductor chip. The buffer layer is covered by a molding layer. According to the invention, the reliability of the semiconductor encapsulation is improved.

Description

Semiconductor packages and forming method thereof
Technical field
Inventive concept relates to semiconductor packages and forming method thereof.
Background technology
Traditionally, the electronics industry expectation has the less and lighter semiconductor packages of low manufacturing cost.In addition, many kinds of semiconductor packages have been developed to use in various application.For example, can by at the upper mounting semiconductor chip of printed circuit board (PCB) (PCB), carry out molding process, ball grid array (BGA) encapsulation is formed on the bottom that then soldered ball joined to PCB.The BGA encapsulation needs molding process and PCB usually, makes the thickness that is difficult to reduce the BGA encapsulation.
Wafer-class encapsulation (WLP) has been proposed, for the treatment of the above-mentioned shortcoming of BGA encapsulation.In the WLP encapsulation, redistributing layer can be formed on the bottom of semiconductor chip.Can not need molding process and PCB in the WLP encapsulation.Therefore, the WLP encapsulation can utilize simple process to form, and has the thickness that reduces.Yet, because the size of WLP encapsulation is very little, so can there be other problem in the WLP encapsulation.
Summary of the invention
In some embodiments, semiconductor packages comprises the first semiconductor chip, and this first semiconductor chip comprises reciprocal first surface and second surface.The first semiconductor chip has the first conductive pattern and covers first surface and have opening to expose the first passivation layer of the first conductive pattern.This semiconductor packages also comprises: resilient coating, top surface and the sidewall of covering the first semiconductor chip; Moulding layer covers resilient coating; With the first redistributing layer, be arranged on the basal surface of the first passivation layer.The first redistributing layer is electrically connected to the first conductive pattern.
In some embodiments, the first redistributing layer can directly contact with the first passivation layer.
In some embodiments, semiconductor packages comprises: semiconductor chip, comprise reciprocal first surface and second surface, and semiconductor chip has conductive pattern and passivation layer, and passivation layer covers first surface and has the opening that exposes conductive pattern; Resilient coating covers the whole sidewall of semiconductor chip basically; Moulding layer covers resilient coating; And redistributing layer, being arranged on the basal surface of passivation layer, redistributing layer is electrically connected to conductive pattern.
In some embodiments, semiconductor packages comprises: semiconductor chip has pad; Passivation layer is formed on semiconductor chip, and passivation layer has the opening that exposes pad; Resilient coating covers semiconductor chip; Moulding layer covers resilient coating; And redistributing layer, be electrically connected to pad, wherein redistributing layer directly contacts with passivation layer.
In some embodiments, the formation method of semiconductor packages comprises: first semiconductor chip that will comprise the first conductive pattern is placed on carrier; Form the top surface of covering the first semiconductor chip and the resilient coating of sidewall; Form moulding layer on resilient coating; The first semiconductor chip is separated with carrier; And form the first redistributing layer be electrically connected to the first conductive pattern on the basal surface of the first semiconductor chip.
In some embodiments, the formation method of semiconductor packages comprises: place a plurality of semiconductor chips on carrier, each semiconductor chip comprises having opening with the passivation layer of exposed pad; With a plurality of semiconductor chips of buffer coated, make all sidewalls basically of a plurality of semiconductor chips be cushioned layer covering; Formation is positioned at the moulding layer on resilient coating; And the redistributing layer that forms the pad be electrically connected in a plurality of semiconductor chips corresponding one.
Description of drawings
Consider accompanying drawing and detailed description subsequently, it is more obvious that inventive concept will become.
Fig. 1 is the sectional view that illustrates according to the semiconductor packages of the first embodiment of inventive concept;
Fig. 2 and Fig. 3 are the zoomed-in views of the part " A " of Fig. 1;
Fig. 4 to Figure 11 is the sectional view of formation method that the semiconductor packages of Fig. 1 is shown;
Figure 12 is the sectional view of modified example that the semiconductor packages of Fig. 1 is shown;
Figure 13 is the sectional view that illustrates according to the semiconductor packages of the second embodiment of inventive concept;
Figure 14 to Figure 19 is the sectional view of formation method that the semiconductor packages of Figure 13 is shown;
Figure 20 is the sectional view that illustrates according to the semiconductor packages of the 3rd embodiment of inventive concept;
Figure 21 to Figure 25 is the sectional view of formation method that the semiconductor packages of Figure 20 is shown;
Figure 26 and Figure 27 are the sectional views of modified example that the semiconductor packages of Figure 20 is shown;
Figure 28 is the sectional view that illustrates according to the semiconductor packages of the 4th embodiment of inventive concept;
Figure 29 illustrates the schematic diagram that comprises according to the package module example of the semiconductor packages of inventive concept embodiment;
Figure 30 illustrates the schematic block diagram that comprises according to the electronic installation example of the semiconductor packages of inventive concept embodiment; And
Figure 31 illustrates the schematic block diagram that comprises according to the storage system example of the semiconductor packages of inventive concept embodiment.
Embodiment
Referring now to accompanying drawing, the present invention's design, the example embodiment of inventive concept shown in the drawings are described more fully.Will be in the following example embodiment of describing in more detail by the reference accompanying drawing, the advantage of inventive concept and feature and the method for these advantages and feature that realizes will become obvious.Yet, should be noted that inventive concept is not limited to following example embodiment, but can realize with various forms.Therefore, provide example embodiment only be used for open inventive concept and allow those skilled in the art understand the kind of inventive concept.In the accompanying drawings, the concrete example that provides at this is provided the embodiment of inventive concept, and for clear and exaggerated.
Term only is used for describing specific embodiment and is not intended to the restriction invention as used herein.As used herein, singulative also is intended to comprise plural form, unless the other meaning clearly indicated in context.As used herein, term " and/or " comprise in associated listed items one or more arbitrarily and all combinations.Should be understood that, when element was called as " being connected to " or " being couple to " another element, it can directly connect or be couple to another element or can have intermediary element.
Similarly, will be appreciated that when the element such as layer, zone or substrate be called as another element " on " time, it can be directly on another element or can have intermediary element.On the contrary, term " directly " means and does not have intermediary element.Can further understand and " comprise " and/or illustrate " comprising " existence of described feature, integral body, step, operation, element and/or component when term when this uses, do not exist or add one or more other features, integral body, step, operation, element, component and/or its group but do not get rid of.
In addition, be described in embodiment in detailed description with sectional view as the desirable exemplary views of inventive concept.Therefore, the shape of exemplary views can change according to manufacturing technology and/or admissible error.Therefore, inventive concept embodiment is not limited to the concrete shape shown in exemplary views, but can comprise other shapes issuable according to manufacturing process.In accompanying drawing, illustrative zone has general performance, and is provided to show the concrete shape of element.Therefore, should not be construed the scope of restriction inventive concept.
Although be appreciated that term first, second, and third grade can be used for this and describe various elements, these elements are not limited by these terms should.These terms only are used for distinguishing an element and other elements.Therefore, the first element in some embodiments can be called as the second element in other embodiments, and without departing the teaching of the invention.The complementary homologue that comprises them in the exemplary embodiment aspect the inventive concept of this explanation and explanation.In specification, identical reference number or identical reference marker refers to identical element in the whole text.
In addition, be shown in reference to cross-sectional illustration and/or plane graph and described one exemplary embodiment here, this diagram is desirable exemplary illustration.Therefore, can expect the variation of the illustrated shape that causes due to for example manufacturing technology and/or tolerance.Therefore, one exemplary embodiment should not be construed as the region shape shown in being limited to here, but comprises departing from due to the shape that is for example caused by manufacturing.For example, the etching region that is illustrated as rectangle will have sphering or crooked feature usually.Therefore, the zone shown in figure be in essence schematically and their shape be not intended to illustrate device the zone true shape and be not intended to limit the scope of one exemplary embodiment.
[the first execution mode]
Fig. 1 is the sectional view that illustrates according to the semiconductor packages of the first embodiment of inventive concept.Fig. 2 and Fig. 3 are the zoomed-in views of the part " A " of Fig. 1.
With reference to figure 1,2 and 3, comprise semiconductor chip 10 according to the semiconductor packages 100 of the first embodiment.Semiconductor chip 10 comprises reciprocal first surface 10a and second surface 10b.For example, first surface 10a can be the basal surface of semiconductor chip 10, and second surface 10b can be the top surface of semiconductor chip 10.Semiconductor chip 10 can be included in the conductive pad (or pad) 12 that first surface 10a exposes.Semiconductor chip 10 can be in various storage chips and various logic chip.The first passivation layer 14 can cover the first surface 10a of semiconductor chip 10.For example, the first passivation layer 14 can be the bilayer of silicon-nitride layer 14a and polyimide layer 14b for example.The first passivation layer 14 also can be formed by other suitable materials, such as Si oxide-nitride layer.Resilient coating 16 can cover sidewall and the top surface 10b of semiconductor chip 10.Moulding layer 18 can cover resilient coating 16.The basal surface of resilient coating 16 can be arranged on and the essentially identical level of the basal surface of the first passivation layer 14, as shown in Figure 2.Alternatively, the basal surface of resilient coating 16 can be arranged on the level higher than the basal surface of the first passivation layer 14, as shown in Figure 3.In one embodiment, resilient coating 16 can be arranged between the top surface 10b and moulding layer 18 of semiconductor chip 10.
Redistribution pattern 24 can be arranged on below the first passivation layer 14.Redistribution pattern 24 passes the first passivation layer 14 to be electrically connected to conductive pad 12.Redistribution pattern 24 extends with the basal surface near resilient coating 16.
Between redistribution pattern 24 and the first passivation layer 14, between redistribution pattern 24 and resilient coating 16 and between redistribution pattern 24 and conductive pad 12, inculating crystal layer pattern 20 can be set.Illustration redistribution pattern 24 and inculating crystal layer pattern 20 can be formed by the metal such as copper, nickel and/or tin.
In some embodiments, inculating crystal layer pattern 20 and redistribution pattern 24 can jointly form redistributing layer 25.In the case, redistributing layer 25 can be the bilayer that comprises seed metal and coating metal.In another embodiment, redistributing layer 25 can form individual layer.
In one embodiment, redistributing layer 25 can contact with the basal surface of resilient coating 16 (for example, directly contact).In another embodiment, redistributing layer 25 also can contact with the first passivation layer 14 (for example, directly contact).
The second passivation layer 26 can cover redistribution pattern 24 partly, can expose the zone of joint (electric coupling) outside terminal (such as soldered ball 28) of redistribution pattern 24.The second passivation layer 26 can contact with the basal surface of resilient coating 16.For example, the second passivation layer 26 can be formed such as polyimide layer by polymeric layer.Soldered ball 28 joins the basal surface of redistribution pattern 24 to.
In some embodiments, the second passivation layer 26 can cover basal surface, resilient coating 16 and a part of redistributing layer 25 of the first passivation layer 14.
In some embodiments, the second passivation layer 26 can comprise the material identical with resilient coating 16 with the first passivation layer 14.
Can be so-called fan-out wafer-class encapsulation (FO-WLP) according to the semiconductor packages of the first embodiment.In fan-out-type encapsulation, at least some in external contact pad and/or conductor rail laterally are positioned at outside the profile of semiconductor chip or intersect at least the profile of semiconductor chip, and this conductor rail is electrically connected to the external contact pad with semiconductor chip.Therefore, in the fan-out-type encapsulation, the peripheral outer part of the encapsulation of semiconductor chip can be used for joining this packaged battery to external device (ED).Should outer part effectively enlarge the relevant contact area of the floor space with semiconductor chip that encapsulates around the encapsulation of semiconductor chip.
Moulding layer 18 can comprise organic material, such as, epoxy-based polymerization thing layer and filler particles.Silica or alumina can be used as filler particles.In some embodiments, moulding layer 18 can have approximately 85% to the about filer content of 92% scope.Moulding layer 18 can have suitable thermal coefficient of expansion and suitable coefficient of elasticity, to suppress the warpage of whole semiconductor packages 100.The suitable thermal coefficient of expansion that be used for to suppress the moulding layer 18 of warpage can be at about 7ppm/ ° of C to the about scope of 20ppm/ ° of C.Particularly, the suitable thermal coefficient of expansion of moulding layer 18 can be about 7ppm/ ° of C.The coefficient of elasticity that be used for to suppress the moulding layer 18 of warpage can be at about 20GPa to the about scope of 25GPa.On the other hand, the thermal coefficient of expansion of semiconductor chip 10 can be at about 3ppm/ ° of C to the about scope of 4ppm/ ° of C.Resilient coating 16 can have the physical property that is different from moulding layer 18.Inter alia, this physical property can be dielectric constant, adhesion strength, flexible, thermal coefficient of expansion and coefficient of elasticity.In one embodiment, resilient coating 16 can be formed by dielectric material, and this dielectric material is different from the material that forms moulding layer 18.
Resilient coating 16 can alleviate by the caused stress of difference between the physical property of semiconductor chip 10 and moulding layer 18.In order to alleviate stress, resilient coating 16 can have suitable thermal coefficient of expansion and suitable coefficient of elasticity.The thermal coefficient of expansion of resilient coating 16 can be at about 50ppm/ ° of C to the about scope of 150ppm/ ° of C.Particularly, the thermal coefficient of expansion of resilient coating 16 can be at about 50ppm/ ° of C to the about scope of 100ppm/ ° of C.The coefficient of elasticity of resilient coating 16 can be at about 1GPa to the about scope of 4GPa.In addition, resilient coating 16 can have photonasty.Photosensitive resin layer can be used as resilient coating 16.Particularly, the polyimide-based polymeric layer of sensitization, for example, the polyimides of sensitization (PSPI) can be used as resilient coating 16.Resilient coating 16 can comprise the material identical with the first passivation layer 14.Alternatively, resilient coating 16 can be formed by non-photopolymer material, such as non-light-sensitive polyimide.
The if there is no resilient coating 16 of inventive concept is because the variety of issue relevant with the reliability of semiconductor packages may occur the difference between the physical property of semiconductor chip 10 and moulding layer 18.For example, due to the difference between the physical property of semiconductor chip 10 and moulding layer 18, stress may occur between moulding layer 18 and semiconductor chip 10.Stress may concentrate on the sidewall of semiconductor chip 10.Therefore, the interval between the sidewall of semiconductor chip 10 and moulding layer 18 can be widened, and perhaps semiconductor packages can warpage.In addition, the warpage by semiconductor packages can worsen plate level reliability, makes at the soldered ball place that joins base board (board substrate) to and may engage the crack.Yet according to some execution modes of inventive concept, resilient coating 16 is arranged between at least one sidewall of moulding layer 18 and semiconductor chip 10, to alleviate by the caused stress of difference between the physical property of semiconductor chip 10 and moulding layer 18.Therefore, can solve by the caused problem of this stress.
According to an execution mode, moulding layer 18 can be for example by resilient coating 16 and spaced apart with the first passivation layer 14.In another embodiment, the second passivation layer 26 can be for example by resilient coating 16 and spaced apart with moulding layer 18.
In some embodiments, the sidewall 16a of resilient coating 16 and the sidewall 18a of moulding layer 18 vertically aim at basically each other, as shown in Figure 1.As a result, the sidewall 18a of the sidewall 16a of resilient coating and moulding layer 18 forms the exterior side wall of encapsulation 100.
Fig. 4 to Figure 11 is the sectional view of formation method that the semiconductor packages of Fig. 1 is shown.
With reference to figure 4, semiconductor chip 10 joins carrier 1 to, and adhesive layer 3 betwixt.Carrier 1 can be by such as at least a formation the in the various materials of glass, plastics and metal.Adhesive layer 3 can be two-sided tape or adhesive.If adhesive layer 3 is two-sided tapes, adhesive layer 3 can join carrier 1 to by vacuum laminating technology.If adhesive layer 3 is adhesives, adhesive layer 3 can be formed on carrier 1 by ink-jetting process, typography and/or coating processes.Each semiconductor chip 10 comprises reciprocal first surface 10a and second surface 10b and conductive pad 12.The first passivation layer 14 covers first surface 10a.The first passivation layer 14 can have the opening 13 that exposes a part of conductive pad 12.The first passivation layer 14 can contact with adhesive layer 3.
With reference to figure 5, resilient coating 16 can form to engage thereon to be had on the carrier 1 of semiconductor chip 10.Resilient coating 16 covers semiconductor chip 10 and adhesive layer 3.Resilient coating 16 can be formed on semiconductor chip 10 and adhesive layer 3 by coating processes.For example, resilient coating 16 can be formed by polyimide-based polymeric layer.Resilient coating 16 can form under atmospheric pressure.
With reference to figure 6, moulding layer 18 is formed on resilient coating 16.In order to form moulding layer 18, carrier 1 can be inserted in the moulding layer mold framework, and then moulding layer solution can be injected into the moulding layer mold framework from the top.In order to reduce the formation in the space in moulding layer 18, can the moulding layer mold framework with the regional opposite zone of moulding layer solution by its injection on vacuum or decompression are provided.
At this moment, in the situation that there is no resilient coating 16, can be with stress induced to the top surface of semiconductor chip 10 by injection molding layer solution.In addition, moulding layer solution may be invaded the zone below the basal surface 10a of semiconductor chip 10.Therefore, conductive pad 12 may be contaminated, and conductive pad 12 may be molded layer and cover, perhaps may cause whole semiconductor chip be molded layer 18 around the immersion problem.In addition, during forming the technique of moulding layer 18, the mobile meeting by moulding layer solution makes semiconductor chip distortion or rotation.Yet, according to some execution modes of inventive concept, form moulding layer 18 after forming resilient coating 16.Therefore, moulding layer 18 is not invaded the basal surface 10a of semiconductor chip 10.In addition, can reduce or prevent immersion problem and/or Rotation.
In addition, owing to carrying out the technique that forms resilient coating 16 under atmospheric pressure, so can basically reduce immersion problem and/or Rotation.Therefore, semiconductor chip 10 being pressed dearly or is fixed to may be not necessarily in adhesive layer 3.Thereby, the difference in height between the basal surface of the basal surface of resilient coating 16 and the first passivation layer 14 can not occur, perhaps this difference in height may be relatively little.Therefore, follow-up redistribution pattern can be formed directly on the basal surface of resilient coating 16 and the first passivation layer 14.Therefore, can not need extra insulating barrier to form technique and etch process.At length, in the prior art, before forming redistributing layer on passivation layer, typically be formed on moulding layer and have the semiconductor chip top of passivation layer such as the insulating barrier of PSPI.Yet, in some execution modes of the application, can skip over such additional process steps and redistributing layer and can be formed directly on passivation layer, this can reduce significantly manufacturing cost and simplify whole assembly technology.
With reference to figure 7, carrier 1 separates with semiconductor chip 10.If adhesive layer 3 is two-sided tapes, be used for for example providing approximately the heat of 170 ° of C or higher temperature can be supplied to two-sided tape.Therefore, two-sided tape may lose adhesion strength, makes it to separate with carrier 1.Alternatively, if carrier 1 is formed by glass, ultraviolet ray can irradiation to the dorsal part of carrier 1 so that two-sided tape can hardening to lose adhesion strength.Therefore, adhesive layer 3 can separate with carrier 1.In other embodiments, adhesive layer 3 can dissolve to be removed with chemicals.Therefore, the basal surface of the first passivation layer 14 and resilient coating 16 is exposed.With reference to figure 8, the semiconductor chip 10 that separates with carrier 1 is reversed, and makes first surface 10a face up.
Then, inculating crystal layer pattern 20 can be formed on the top surface of the first passivation layer 14 of semiconductor chip 10 and resilient coating 16.Inculating crystal layer pattern 20 can form by depositing operation.
In some embodiments, inculating crystal layer pattern 20 can use the soft lithographic technique of selecting from the group that is comprised of stencil printing technique (stencil printing process), silk-screen printing technique, ink-jet printing process, imprint process, offset printing (offset printing process) technique to form.
Inculating crystal layer pattern 20 can contact with conductive pad 12.Inculating crystal layer pattern 20 can be formed by the metal such as copper, nickel and/or tin.The photoresist pattern 22 that limits the shape of redistribution pattern can be formed on inculating crystal layer 20.Photoresist pattern 22 can use photoetching process to form.Redistribution pattern 24 for example is formed on the expose portion that is not covered by photoresist pattern 22 of inculating crystal layer 20 by shikishima plating process.With reference to figure 9, photoresist pattern 22 can be removed to be exposed to the following inculating crystal layer 20 of photoresist pattern 22.Then, the expose portion that is not covered by redistribution pattern 24 of inculating crystal layer 20 utilizes redistribution pattern 24 to be removed as etching mask, thereby exposes the first passivation layer 14 and resilient coating 16.
With reference to Figure 10, the second passivation layer 26 forms redistribution pattern 24 and resilient coating 16 and first passivation layer 14 between redistribution pattern 24 of cover part.The second passivation layer 26 can be formed by polyimide-based material.Soldered ball 28 joins the expose portion that is not covered by the second passivation layer 26 of redistribution pattern 24 to.
With reference to Figure 11, can carry out cutting technique to cut the second passivation layer 26, resilient coating 16 and moulding layer 18.Therefore, elemental semiconductor encapsulation 100 is separated from one another.Thereby, semiconductor packages 100 that can shop drawings 1.
Figure 12 is the sectional view of modified example that the semiconductor packages of Fig. 1 is shown.
With reference to Figure 12, in the semiconductor packages 101 according to this modified example, resilient coating 16 can basically cover the whole sidewall of semiconductor chip 10 and can not cover the top surface 10b of semiconductor chip 10.Therefore, the top surface 10b of semiconductor chip 10 can contact with moulding layer 18.Other elements of semiconductor packages 101 can be identical with the respective element of the semiconductor packages 100 of Fig. 1.
To the formation method of the semiconductor packages 101 of Figure 12 be described.After resilient coating 16 formed the sidewall and top surface 10b that covers semiconductor chip 10, the resilient coating 16 on top surface 10b can be removed to expose the top surface 10b of semiconductor chip 10.The resilient coating 106 of removal on top surface 10b can be carried out by selectivity exposure technology and developing process.Alternatively, the resilient coating 106 of removing on top surface 10b can be carried out such as etch process by flatening process.Follow-up technique can be as with reference to figure 6 to 11 described execution.
[the second execution mode]
Figure 13 is sectional view, and the semiconductor packages according to inventive concept the second execution mode is shown.The fan-out wafer level packaging structure that has a plurality of semiconductor chips that comprise sequential cascade according to the semiconductor packages 102 of present embodiment.
With reference to Figure 13, comprise the first semiconductor chip 10 and be layered in the second semiconductor chip 40 on the first semiconductor chip 10 according to the semiconductor packages 102 of present embodiment.The second adhesive layer 30 can be arranged between the first semiconductor chip 10 and the second semiconductor chip 40.The first semiconductor chip 10 and the second semiconductor chip 40 can attach each other and fix by the second adhesive layer 30.The second adhesive layer 30 can be two-sided tape or adhesive.The first conductive pad 12 can expose in the bottom surface of the first semiconductor chip 10.The first conductive pad 12 can be covered by the first passivation layer 14.The second conductive pad 42 can expose in the bottom surface of the second semiconductor chip 40.The second conductive pad 42 can be covered by the second passivation layer 44.The first passivation layer 14 can be formed by the material identical with the second passivation layer 44.The second conductive pad 42 can not overlapping the first semiconductor chip 10.The width of the second semiconductor chip 40 can be greater than the width of the first semiconductor chip 10.In one embodiment, resilient coating 16 can cover basal surface and at least one sidewall of the second semiconductor chip 40.In another embodiment, resilient coating 16 can cover sidewall, top surface, the basal surface of a part and the sidewall of the first semiconductor chip 10 of the second semiconductor chip 40.Moulding layer 18 can be arranged on resilient coating 16.
The first redistribution pattern 24a can be arranged on the basal surface of the first passivation layer 14 and pass the first passivation layer 14 to be electrically connected to the first conductive pattern 12.The second redistribution pattern 24b can be arranged on the basal surface of resilient coating 16 and pass resilient coating 16 to be electrically connected to the second conductive pad 42.Resilient coating 16 and first passivation layer 14 of the redistribution pattern 24a of the 3rd passivation layer 26 cover parts and 24b and part.The first inculating crystal layer 20a is arranged between the first redistribution pattern 24a and the first passivation layer 14 and between the first redistribution pattern 24a and the first conductive pad 12.The first inculating crystal layer 20a and the first redistribution pattern 24a also can jointly be called the first redistributing layer 23.The second inculating crystal layer 20b is arranged between the second redistribution pattern 24b and resilient coating 16 and between the second redistribution pattern 24b and the second conductive pad 42.The second inculating crystal layer 20b and the second redistribution pattern 24b can jointly be called the second redistributing layer 27.As in the first embodiment, the first inculating crystal layer 20a and the second inculating crystal layer 20b can use the soft lithographic technique of selecting from the group that is comprised of stencil printing technique, silk-screen printing technique, ink-jet printing process, imprint process, offset printing process to form.In addition, although not shown, the first redistributing layer 23 and the second redistributing layer 27 can alternatively form individual layer, rather than double-deck.
The first soldered ball 28a can join to not by the first redistribution pattern 24a of the exposure of the 3rd passivation layer 26 coverings, and the second soldered ball 28b can join to not by the second redistribution pattern 24b of the exposure of the 3rd passivation layer 26 coverings.
Other elements of semiconductor packages 102 can be identical with the respective element of semiconductor packages in the first execution mode/and similar.
In the present embodiment, the number of stacked semiconductor chip can be two.Yet inventive concept is not limited to this.In other embodiments, the number of stacked semiconductor chip can be three or more.
Figure 14 to Figure 19 is the sectional view of formation method that the semiconductor packages of Figure 13 is shown.
With reference to Figure 14, the first adhesive layer 3 is formed on carrier 1.The first semiconductor chip 10 can be attached on the first adhesive layer 3.The second adhesive layer 30 can be formed on the top surface of the first semiconductor chip 10, and then the second semiconductor chip 40 is attached on the second adhesive layer 30.The first conductive pad 12 is arranged on the bottom surface of the first semiconductor chip 10 and is covered by the first passivation layer 14.The second conductive pad 42 can be arranged on the bottom surface of the second semiconductor chip 40 and be covered by the second passivation layer 44.When the second semiconductor chip 40 was attached on the second adhesive layer 30, therefore not overlapping the first semiconductor chip 10 of the second conductive pad 42 also was exposed.
With reference to Figure 15, resilient coating 16 is formed on the second semiconductor chip 40.Resilient coating 16 covers sidewall, top surface, the basal surface of a part and the sidewall of the first semiconductor chip 10 of the second semiconductor chip 40.As described in the first execution mode, resilient coating 16 can form by the photosensitive resin solution that applies photosensitive resin solution for example and this coating of hardening.Alternatively, according to the application's one side, non-photosensitive resin solution can be used to form resilient coating 16.In this case, the photoresist layer can be formed on the non-photosensitive resin top of sclerosis, is used for the non-photosensitive resin that patterning should harden.Other execution modes that can be applied to discuss in the application in this respect of the application.After forming resilient coating 16, moulding layer 18 is formed on resilient coating 16.
With reference to Figure 16, carrier 1 separates with the first semiconductor chip 10.If the first adhesive layer 3 is two-sided tapes, be used for for example providing approximately the heat of 170 ° of C or higher temperature can be fed to two-sided tape.Therefore, two-sided tape can lose adhesion strength, makes the first adhesive layer 3 to separate with carrier 1.At this moment, the hardening temperature of the first adhesive layer 3 and the second adhesive layer 30 can differ from one another.As a result, when the first adhesive layer 3 separated with carrier 1, the second adhesive layer 30 can not separate with the second semiconductor chip 40 with the first semiconductor chip 10.
In other embodiments, if carrier 1 is formed by glass, ultraviolet ray can irradiation to the dorsal part of carrier 1 so that two-sided tape can hardening to lose adhesion strength.Therefore, the first adhesive layer 3 can separate with carrier 1.
In other embodiments, the first adhesive layer 3 can dissolve to be removed with chemicals.As a result, the basal surface of the first passivation layer 14 and resilient coating 16 is exposed.The adhesion strength that can keep at this moment, the second adhesive layer 30.The first semiconductor chip 10 and the second semiconductor chip 40 that separate with carrier 1 can be reversed.Then the mask pattern 50 that has an opening 52 is formed on the top surface of the first and second semiconductor chips 10 of upset and the first passivation layer 14 of 40 and resilient coating 16.Mask pattern 50 can be formed by the material that has etching selectivity about resilient coating 16.For example, mask pattern 50 can be formed by at least one in spin-coating hardmask (SOH) layer, amorphous carbon layer (ACL), silicon-nitride layer, silicon oxide layer, silicon oxynitride layer, metal oxide layer and photoresist.Opening 52 can be overlapping vertically with the second conductive pad 42.
With reference to Figure 17 and Figure 18, resilient coating 16 uses mask pattern 50 etched to expose the second conductive pad 42 of a part as etching mask.Then, mask pattern 50 can be etched to expose the top surface of resilient coating 16 and the first passivation layer 14.Therefore, opening 52 can extend to resilient coating 16, makes opening 52 also can be formed in resilient coating 16.
With reference to Figure 19, as described with reference to figure 8 and Fig. 9, can be conformally formed the inculating crystal layer (not shown), photoresist pattern (not shown) can be formed on inculating crystal layer, then optionally forms redistribution pattern 24a and 24b by the shikishima plating process that utilizes the inculating crystal layer that selectivity exposes.Then, photoresist pattern (not shown) and the inculating crystal layer (not shown) below the photoresist pattern can be removed to form inculating crystal layer pattern 20a and 20b.The 3rd passivation layer 26 forms redistribution pattern 24a and 24b and resilient coating 16 and first passivation layer 14 between redistribution pattern 24a and 24b of cover part.The 3rd passivation layer 26 can be formed by polyimide-based material.Soldered ball 28a and 28b can be arranged on not by on the redistribution pattern 24a and 24b of the exposure of the 3rd passivation layer 26 coverings.
Subsequently, can carry out cutting technique to cut the 3rd passivation layer 26, resilient coating 16 and moulding layer 18, make elemental semiconductor encapsulation 102 separated from one another.Therefore, can make the semiconductor packages 102 of Figure 13.
[the 3rd execution mode]
Figure 20 is sectional view, and the semiconductor packages according to inventive concept the 3rd execution mode is shown.Have according to the semiconductor packages 105 of the 3rd execution mode the laminate packaging structure that comprises stacked fan-out wafer-class encapsulation.
With reference to Figure 20, comprise the first semiconductor packages 103 and be arranged on the second semiconductor packages 104 on the first semiconductor packages 103 according to the semiconductor packages 105 of the 3rd execution mode.
The first semiconductor packages 103 comprises the first semiconductor chip 10.The first conductive pad 12 is arranged on the bottom surface of the first semiconductor chip 10 and is covered by the first passivation layer 14.The first resilient coating 16 can cover sidewall and/or the top surface of the first semiconductor chip 10.The first redistribution pattern 24 can be close to the basal surface setting of basal surface and first resilient coating 16 of the first passivation layer 14.The first redistribution pattern 24 is electrically connected to the first conductive pad 12.The first inculating crystal layer pattern 20 can be arranged between the first redistribution pattern 24 and the first conductive pad 12, between the first redistribution pattern 24 and the first passivation layer 14 and between the first redistribution pattern 24 and the first resilient coating 16.As in the first embodiment, the first redistribution pattern 24 and the first inculating crystal layer pattern 20 can jointly form the first redistributing layer 25.In addition, the first redistributing layer 25 can form individual layer.
The second passivation layer 26 can the cover part the first redistribution pattern 24, the first resilient coating 16 and first passivation layer 14 of part.The first soldered ball 28 joins the expose portion that is not covered by the second passivation layer 26 of the first redistribution pattern 24 to.The first moulding layer 18 is arranged on the first resilient coating 16.
Through hole 64 passes the first moulding layer 18 and resilient coating 16 successively to be electrically connected to the first redistribution pattern 24.Run through inculating crystal layer pattern 66 can be arranged between through hole 64 and the first moulding layer 18, between through hole 64 and the first resilient coating 16 and between through hole 64 and the first inculating crystal layer pattern 20.The second redistribution pattern 70 is arranged on the top surface of moulding layer 18.The second redistribution pattern 70 is electrically connected to through hole 64.
The second inculating crystal layer pattern 68 can be arranged between the second redistribution pattern 70 and moulding layer 18 and between the second redistribution pattern 70 and through hole 64.
The 3rd passivation layer 72 can cover a part of the second redistribution pattern 70 and moulding layer 18.The 3rd passivation layer 72 can have the opening 75 of the second redistribution pattern 70 that exposes a part.
The second semiconductor packages 104 comprises the second semiconductor chip 80.The second conductive pad 82 is arranged on the bottom surface of the second semiconductor chip 80 and is covered by the 4th passivation layer 84.The second resilient coating 86 covers sidewall and the top surface of the second semiconductor chip 80.In another embodiment, the second resilient coating 86 can only cover the sidewall (not shown) of the second semiconductor chip 80.The second moulding layer 88 covers the second resilient coating 86.The basal surface of the 3rd redistribution pattern 94 contiguous the 4th passivation layers 84 and the basal surface setting of the second resilient coating 86.The 3rd redistribution pattern 94 is electrically connected to the second conductive pad 82.
The 3rd inculating crystal layer pattern 90 can be arranged between the 3rd redistribution pattern 94 and the second conductive pad 82, between the 3rd redistribution pattern 94 and the 4th passivation layer 84 and between the 3rd redistribution pattern 94 and the second resilient coating 86.
The 5th passivation layer 96 can the cover part the 3rd redistribution pattern 94 and the second resilient coating 86 and the 4th passivation layer 84 of part.The 3rd redistribution pattern 94 of the 5th passivation layer 96 expose portions.
The second soldered ball 98 can be arranged between the 3rd redistribution pattern 94 and the second redistribution pattern 70 and with the 3rd redistribution pattern 94 and the second redistribution pattern 70 electrical interconnections.
The first passivation layer 14 of Figure 20 and the 4th passivation layer 84 can be corresponding to the first passivation layers 14 of the first execution mode of Fig. 1.For example, the first passivation layer 14 of Figure 20 and the 4th passivation layer 84 can be formed by the material identical with the first passivation layer 14 of the first execution mode of Fig. 1.Second, third of Figure 20 and the 5th passivation layer 26,72 and 96 can and be formed by the material identical with this second passivation layer 26 corresponding to the second passivation layer 26 of the first execution mode of Fig. 1.The first to the 3rd redistribution pattern 24,70 and 94, inculating crystal layer pattern 20,66,68 and 90, and through hole 64 can form by metal, such as copper, nickel and/or tin.
The first resilient coating 16 and the second resilient coating 86 can be corresponding to the resilient coatings 16 of the first execution mode of Fig. 1.The first moulding layer 18 and the second moulding layer 88 can be corresponding to the moulding layers 18 of the first execution mode of Fig. 1.
The first semiconductor chip 10 and the second semiconductor chip 80 can be of the same type, and perhaps the first semiconductor chip 10 can be the type different from the second semiconductor chip 80.In some embodiments, the type of the first semiconductor chip 10 and the second semiconductor chip 80 can differ from one another.For example, the first semiconductor chip 10 can be logic chip, and the second semiconductor chip 80 can be storage chip.Other elements of semiconductor packages 105 can be identical with the respective element of the semiconductor packages of the first execution mode/and similar.
Figure 21 to Figure 25 is sectional view, and the method according to the semiconductor packages of formation Figure 20 of some execution modes is shown.The second semiconductor packages 104 can have the essentially identical element of semiconductor packages 100 with Fig. 1.Therefore, the formation method of the second semiconductor packages 104 can be basic identical with the formation method of semiconductor packages 100.Yet the shape of the first semiconductor packages 103 can be different from the shape of the semiconductor packages 100 of Fig. 1.Therefore, the formation method of the first semiconductor packages 103 will be described in detail.
With reference to Figure 21, as described with reference to the Fig. 4 to Fig. 9 in the first execution mode, the first resilient coating 16 can form sidewall and/or the top surface that covers the first semiconductor chip 10.The first moulding layer 18 is formed on the first resilient coating 16.The first inculating crystal layer pattern 20, the first redistribution pattern 24 and the second passivation layer 26 are formed on the basal surface of the first passivation layer 14 and the first resilient coating 16.
With reference to Figure 22, the first moulding layer 18 and the first resilient coating 16 can be removed to form the through hole (through-hole) 62 of the first inculating crystal layer pattern 20 that exposes part partly.The technique that forms through hole 62 can be utilized for example etch process or laser.
With reference to Figure 23, according to some execution modes, run through inculating crystal layer and can be conformally formed on the first moulding layer 18 that has formed therein through hole 62, then can carry out shikishima plating process to form the plating layer of filling through hole 62.Can run through inculating crystal layer pattern 66 and through hole (through-via) 64 to form in through hole 62 at execution flatening process on plating layer.At this moment, can expose the top surface of the first moulding layer 18.
With reference to Figure 24, the second inculating crystal layer pattern 68, the second redistribution pattern 70 and the 3rd passivation layer 72 are formed on the top surface of the first moulding layer 18 by the method for describing with reference to figure 8 to 10 according to some execution modes.The first soldered ball 28 can join the first redistribution pattern 24 that is not covered to be exposed by the second passivation layer 26 to.
With reference to Figure 25, carry out cutting technique so that the first independent semiconductor packages 103 is separated from one another.After cutting the first semiconductor packages 103, the second semiconductor packages 104 can be arranged on the first semiconductor packages 103.
The second semiconductor packages 104 can form by the method identical with the semiconductor packages 100 of the first execution mode.The second semiconductor packages 104 comprises the second semiconductor chip 80.The second conductive pad 82 can be arranged on the bottom surface of the second semiconductor chip 80 and can be covered by the 4th passivation layer 84.The top surface of the second semiconductor chip 80 and/or sidewall can be covered by the second resilient coating 86.The second moulding layer 88 can be formed on the second resilient coating 86.The basal surface of the 3rd redistribution pattern 94 contiguous the 4th passivation layers 84 and the basal surface setting of the second resilient coating 86.The 3rd redistribution pattern 94 is electrically connected to the second conductive pad 82.The 3rd inculating crystal layer pattern 90 can be arranged between the 3rd redistribution pattern 94 and the second conductive pad 82, between the 3rd redistribution pattern 94 and the 4th passivation layer 84 and between the 3rd redistribution pattern 94 and the second resilient coating 86.The 3rd redistribution pattern 94 of the 5th passivation layer 96 cover parts and the second resilient coating 86 and the 4th passivation layer 84 of part.The second soldered ball 98 is attached on the expose portion that is not covered by the 5th passivation layer 96 of the 3rd redistribution pattern 94.
Return with reference to Figure 20, when the second semiconductor packages 104 was arranged on the first semiconductor packages 103, the second soldered ball 98 can contact with the second redistribution pattern 70.Then, the second soldered ball is melted and is attached to the second redistribution pattern 70.Therefore, can form semiconductor packages 105.Other elements of semiconductor packages 105 can be same or similar with the respective element of the semiconductor packages of the first execution mode.
Figure 26 and Figure 27 are sectional views, and the modified example of the semiconductor packages of Figure 20 is shown.
With reference to Figure 26, according to this modified example, the semiconductor packages 103a of semiconductor packages 106 does not comprise the second inculating crystal layer pattern 68, the second redistribution pattern 70 and the 3rd passivation layer 72 of Figure 20.In semiconductor packages 106, the second soldered ball 98 can directly contact with through hole 64, and can expose the top surface of the first moulding layer 18.Other elements of semiconductor packages 106 with describe with reference to Figure 20 identical.
With reference to Figure 27, in the first semiconductor packages 103b according to the semiconductor packages 107 of this modified example, through hole 64a and the second redistribution pattern 64b can be connected to each other, and there is no betwixt the border.In other words, through hole 64a and the second redistribution pattern 64b can form single integral body.In addition, run through inculating crystal layer pattern 66a and the second inculating crystal layer pattern 66b can be connected to each other, there is no betwixt the border.In other words, run through inculating crystal layer pattern 66a and the second inculating crystal layer pattern 66b also can form single integral body.The width of the through hole 62 in this modified example can be less than the width of illustrated through hole 62 in Figure 22.Other elements of semiconductor packages 107 can with reference Figure 20 describe basic identical.
Aspects more of the present invention of using in one embodiment also can realize in another embodiment.For example, running through inculating crystal layer pattern 66a can utilize soft lithography to form.In addition, run through inculating crystal layer pattern 66a and the second redistribution pattern 64b can jointly form redistributing layer.This redistributing layer also can form individual layer.
Formation method according to the first semiconductor packages 103b of Figure 27, the width of through hole 62 can form narrowlyer, can form inculating crystal layer, then can carry out shikishima plating process and etch process and run through inculating crystal layer pattern 66a, the second inculating crystal layer pattern 66b, through hole 64a and the second redistribution pattern 64b to form simultaneously.At this moment, do not carry out the flatening process of describing with reference to Figure 23.Then, can carry out the subsequent technique with reference to Figure 24 and Figure 25 description, to form semiconductor packages 107.
[the 4th execution mode]
Figure 28 is sectional view, and the semiconductor packages according to inventive concept the 4th execution mode is shown.
With reference to Figure 28, in the semiconductor packages 108 according to present embodiment, the second semiconductor chip 40 is arranged on the first semiconductor chip 10.Each of the first semiconductor chip 10 and the second semiconductor chip 40 can comprise each the through hole 11 that passes the first semiconductor chip 10 and the second semiconductor chip 40.The second semiconductor chip 40 can be arranged on the first semiconductor chip 10 via the first outside terminal (such as the first soldered ball 13) that is arranged between the first semiconductor chip 10 and the second semiconductor chip 20 by for example flip-chiop bonding method.The first soldered ball 13 is electrically connected to through hole 11.The first passivation layer 14 can be arranged on the basal surface of the first semiconductor chip 10.Resilient coating 16 covers top surface and the sidewall of the first semiconductor chip 10 and the second semiconductor chip 40.Moulding layer 18 is arranged on resilient coating 16.Inculating crystal layer pattern 20, redistribution pattern 24 and the second passivation layer 26 are arranged on the basal surface of the first passivation layer 14 and resilient coating 16.The second soldered ball 28 is arranged on the basal surface of redistribution pattern 24.
In Figure 28, through hole 11 can directly contact with the first soldered ball 13.Yet inventive concept is not limited to this.The redistribution pattern of describing with reference to Figure 20 can be separately positioned on the basal surface of the top surface of the first semiconductor chip 10 and the second semiconductor chip 40 extraly.In this case, the first soldered ball 13 can contact with extra redistribution pattern.
Other elements of semiconductor packages 108 and other techniques are identical with corresponding technique with the respective element of describing in the first to the 3rd execution mode/and similar.
Above-mentioned semiconductor packaging can be applied to various types of semiconductor device and comprise the package module of this semiconductor device.
Figure 29 is schematic diagram, and the example according to the package module that comprises semiconductor packages of some execution modes of inventive concept is shown.With reference to Figure 29, package module 1200 can comprise semiconductor device 1220 and with the QFP(quad flat package) semiconductor integrated circuit chip 1230 of packaged type encapsulation.Be arranged on substrate 1210 according to the semiconductor device 1220 and 1230 with the semiconductor packaging assembling of some execution modes of inventive concept, make to form package module 1200.Package module 1200 can be by being arranged on substrate 1210 the external connection terminals 1240 at a lateral edges place be connected to external electronic device.
Can adopt semiconductor packaging as above to form electronic system as shown in figure 30.Figure 30 is schematic block diagram, and the example of the electronic system that comprises semiconductor packages that some execution modes according to inventive concept form is shown.
With reference to Figure 30, electronic system 1300 can comprise controller 1310, I/O (I/O) unit 1320 and memory device 1330.Controller 1310, I/O unit 1320 and memory device 1330 can be bonded to each other by data/address bus 1350.Data/address bus 1350 can be corresponding to the path of the signal of telecommunication by its transmission.For example, controller 1310 can comprise at least one in microprocessor, digital signal processor, microcontroller or other logical device.Other logical device can have to microprocessor, digital signal processor and microcontroller in any one similar function.Controller 1310 and/or memory device 1330 can be assemblied in according at least one in the semiconductor packages of some execution modes of inventive concept.I/O unit 1320 can comprise keypad, keyboard and/or display unit.Memory device 1330 can storage data and/or the order carried out by controller 1310.Memory device 1330 can comprise volatile memory device and/or nonvolatile semiconductor memory member.In some embodiments, memory device 1310 can form flash memory.Flash memory can be implemented as solid-state disk (SSD).In this case, electronic system 1300 can stably store mass data into flash memory system.Electronic system 1300 can also comprise the interface 1340 that electric transfer of data is arrived communication network or receive electric data from communication network.Interface 1340 can be by wireless or cable operated.For example, interface 1340 can comprise for the antenna of radio communication or be used for the transceiver of cable communication.Although not shown in accompanying drawing, application chip group and/or camera images processor (CIS) can be further provided in electronic system 1300.
Electronic system 1300 can be embodied as mobile system, PC, industrial computer or carry out the logic system of difference in functionality.For example, mobile system can be in PDA(Personal Digital Assistant), portable computer, network basis, radio telephone, mobile phone, laptop computer, digital music system and information sending/receiving system one.When electronic system 1300 was carried out radio communication, electronic system 1300 can be used for communication interface standard, such as 3 generation communication systems (for example, CDMA, GSM, NADC, E-TDMA, WCDMA, CDMA2000).
Semiconductor packaging as above can for example use in as shown in figure 31 storage system.Figure 31 is schematic block diagram, and the example according to the storage system of the employing semiconductor packages of some execution modes of inventive concept is shown.
With reference to Figure 31, storage system 1400 can comprise nonvolatile semiconductor memory member 1410 and storage control 1420.Nonvolatile semiconductor memory member 1410 and storage control 1420 can storage datas or are read the data of storage.Nonvolatile semiconductor memory member 1410 can comprise at least one in the nonvolatile semiconductor memory member of the semiconductor packaging of using more with good grounds execution modes.Storage control 1420 can be controlled nonvolatile semiconductor memory member 1410, in order to read data and/or the storage data of storage in response to the read/write requests of main frame.
According to some execution modes of inventive concept, semiconductor packages can comprise at least one sidewall of being arranged on semiconductor chip and the resilient coating between moulding layer.Resilient coating can have the performance different from moulding layer and semiconductor chip, for example, and physical property.During the method that forms semiconductor packages, due to the difference between the performance of semiconductor chip and moulding layer, can cause stress between moulding layer and semiconductor chip.Therefore, the interval between moulding layer and semiconductor chip may be widened or semiconductor packages possibility warpage.In addition, the warpage by semiconductor packages can worsen plate level reliability, makes the crack to occur to engage at the soldered ball place that joins base board to.Yet according to the execution mode of inventive concept, resilient coating can alleviate by the caused stress of the difference between the physical property of semiconductor chip and moulding layer.Therefore, can solve by the caused problem of this stress.As a result, the reliability of semiconductor packages may be improved by resilient coating.
According to other execution modes of inventive concept, semiconductor packages does not comprise printed circuit board (PCB), makes the gross thickness that can reduce semiconductor packages.
According to other execution modes of inventive concept, extend to the sidewall that covers semiconductor chip due to resilient coating, redistribution pattern also can be formed on the basal surface of resilient coating and soldered ball can be attached on redistribution pattern below resilient coating.Therefore, be easy to engage the soldered ball that is suitable for international standard.In addition, semiconductor packages can be easy to process and test.
In addition, in the formation method according to the semiconductor packages of some execution modes of inventive concept, form resilient coating with at least one sidewall that covers semiconductor chip after, form moulding layer.Do not form resilient coating if moulding layer is formed directly on semiconductor chip, during the technique that forms moulding layer, moulding layer can be invaded by strong pressure the basal surface of semiconductor chip.Therefore, conductive pad may be contaminated, and conductive pad may be molded layer and cover, and perhaps may cause so-called immersion problem, thus whole semiconductor chip be molded layer around.In addition, during the technique that forms moulding layer, may make semiconductor chip distortion or rotation by flowing of moulding layer solution.Yet, according to some execution modes of inventive concept, form moulding layer after forming resilient coating.Therefore, moulding layer is not invaded the basal surface of the passivation layer of the basal surface of semiconductor chip or the basal surface that intrusion covers semiconductor chip.In addition, can reduce or prevent immersion problem and/or Rotation.As a result, can improve the reliability of semiconductor packages.
On the other hand, in the formation method of fan-out wafer-class encapsulation, can after being fixed on carrier by for example adhesive layer, semiconductor chip form moulding layer.Yet, for immersion and/or the Rotation that reduces semiconductor chip, can be pressed against in adhesive layer after desired depth in part of semiconductor chip, carry out the technique that forms moulding layer.Therefore, between the basal surface of the basal surface of moulding layer and semiconductor chip (or cover the basal surface of semiconductor chip passivation layer), difference in height may occur in the fan-out wafer-class encapsulation of completing.Due to this difference in height, so may be difficult to directly form redistribution pattern in encapsulation.Therefore, can need moulding layer and the extra insulating barrier on the basal surface of semiconductor chip, for reducing difference in height.Insulating barrier can cover conductive pad, makes the extra Patternized technique that also can need to comprise etch process and photoetching process, is used for manifesting the conductive pad that is covered by insulating barrier.Therefore, the formation technique of encapsulation can be complicated and can increase process costs.Yet, according to some execution modes of inventive concept, can complete the resilient coating that covers semiconductor chip under atmospheric pressure, make can not occur to soak and/or Rotation.Therefore, can reduce or prevent difference in height between the basal surface of resilient coating and semiconductor chip (or cover the basal surface of semiconductor chip passivation layer).As a result, can be easily and directly form redistribution pattern, make and can simplify technique and can reduce manufacturing cost.
In this specification, " execution mode " or " execution mode " mean that specific features, structure or the characteristic described in conjunction with this execution mode are included at least one execution mode of the present invention.Therefore, the phrase " in one embodiment " that occurs in the different places of whole specification or " in execution mode " differ to establish a capital and refer to identical execution mode.In addition, concrete feature, structure or characteristic can be combined in one or more execution modes in any suitable manner.
Various operations will be described as helping most understanding the step of a plurality of separation that mode of the present invention carries out.Yet the order of describing step does not mean that operation is that order or order execution in step of dependence must be the order that step is presented.
Although the reference example execution mode has been described inventive concept, to those skilled in the art clearly, can carry out various changes and distortion and not break away from the spirit and scope of inventive concept.Therefore, be to be understood that above-mentioned execution mode is not restriction, but illustrative.Therefore, the scope of inventive concept will be determined by the widest admissible explanation of claim and their equivalent, and will can not limited or limit by foregoing description.
The application requires the priority of the patent application No.10-2012-0046997 of submission from May 3rd, 2012 to Koran Office, and its full content is combined in this by reference.

Claims (46)

1. semiconductor packages comprises:
The first semiconductor chip comprises reciprocal first surface and second surface, and described the first semiconductor chip has the first conductive pattern and the first passivation layer, and this first passivation layer covers described first surface and has the opening that exposes described the first conductive pattern;
Resilient coating covers top surface and the sidewall of described the first semiconductor chip;
Moulding layer covers described resilient coating; And
The first redistributing layer is arranged on the basal surface of described the first passivation layer, and described the first redistributing layer is electrically connected to described the first conductive pattern.
2. semiconductor packages as claimed in claim 1, wherein said the first redistributing layer directly contacts with described the first passivation layer.
3. semiconductor packages as claimed in claim 2, also comprise the outside terminal that is conductively coupled to described the first redistributing layer.
4. semiconductor packages as claimed in claim 1, the sidewall of wherein said resilient coating is vertically aimed at basically each other with the sidewall of described moulding layer.
5. semiconductor packages as claimed in claim 1, wherein said moulding layer and described the first passivation layer are spaced apart.
6. semiconductor packages as claimed in claim 5, wherein said moulding layer is spaced apart by described resilient coating and described the first passivation layer.
7. semiconductor packages as claimed in claim 1, the sidewall of wherein said resilient coating and the sidewall of described moulding layer form the exterior side wall of described encapsulation.
8. semiconductor packages as claimed in claim 1, wherein said resilient coating comprise the dielectric material different from the material that forms described moulding layer.
9. semiconductor packages as claimed in claim 1, wherein said resilient coating comprises the material identical with described the first passivation layer.
10. semiconductor packages as claimed in claim 1, wherein said resilient coating has the thermal coefficient of expansion 50ppm/ ° C to 100ppm/ ° of C scope.
11. semiconductor packages as claimed in claim 10, the thermal coefficient of expansion of wherein said moulding layer is 7ppm/ ° C to 20ppm/ ° of C scope.
12. semiconductor packages as claimed in claim 1, wherein said resilient coating has the coefficient of elasticity in 1GPA to 4GPA scope.
13. semiconductor packages as claimed in claim 12, the coefficient of elasticity of wherein said moulding layer is in the scope of 20Gpa to 25GPa.
14. semiconductor packages as claimed in claim 1, wherein said resilient coating is formed by non-photopolymer material.
15. semiconductor packages as claimed in claim 14, wherein said non-photosensitive material is non-light-sensitive polyimide.
16. semiconductor packages as claimed in claim 1, the basal surface of wherein said resilient coating are arranged on the level place of the described basal surface that is equal to or higher than described the first passivation layer.
17. semiconductor packages as claimed in claim 1, wherein said resilient coating are arranged between the described second surface and described moulding layer of described the first semiconductor chip.
18. semiconductor packages as claimed in claim 1, the basal surface of the described resilient coating of part contact of wherein said the first redistributing layer.
19. semiconductor packages as claimed in claim 18 also comprises:
The second passivation layer covers described basal surface and the described basal surface of described resilient coating and the part of described the first redistributing layer of described the first passivation layer,
20. semiconductor packages as claimed in claim 18, wherein said the second passivation layer comprise the material identical with described resilient coating with described the first passivation layer.
21. semiconductor packages as claimed in claim 19, wherein said the second passivation layer is spaced apart by described resilient coating and described moulding layer.
22. semiconductor packages as claimed in claim 1 also comprises:
The second semiconductor chip is layered on described the first semiconductor chip and by described moulding layer and covers,
Wherein said the second semiconductor chip comprises the second conductive pattern; And
Wherein said resilient coating covers a part of basal surface and at least one sidewall of described the second semiconductor chip.
23. semiconductor packages as claimed in claim 22, wherein said resilient coating cover whole sidewalls of described the second semiconductor chip basically.
24. semiconductor packages as claimed in claim 22, not overlapping described the first semiconductor chip of wherein said the second conductive pattern,
Described semiconductor packages also comprises:
The second redistributing layer is arranged on the part of basal surface of described resilient coating, and described the second redistributing layer passes described resilient coating to be electrically connected to described the second conductive pattern.
25. semiconductor packages as claimed in claim 22, wherein said the first conductive pattern are the first through holes that passes described the first semiconductor chip; And
Wherein said the second conductive pattern is the second through hole that passes described the second semiconductor chip,
Described semiconductor packages also comprises: outside terminal is arranged between described the first through hole and described the second through hole so that described the first semiconductor chip and described the second semiconductor chip are electrically connected to each other.
26. semiconductor chip as claimed in claim 1 also comprises:
Through hole passes described moulding layer and described resilient coating to be electrically connected to described the first redistributing layer.
27. semiconductor packages as claimed in claim 26 also comprises:
The semiconductor-on-insulator encapsulation is arranged on described moulding layer and is electrically connected to described through hole.
28. semiconductor packages as claimed in claim 26 also comprises:
The second redistributing layer is arranged on described moulding layer and is electrically connected to described through hole.
29. semiconductor packages as claimed in claim 28, wherein said through hole and described the second redistributing layer form single integral body.
30. a semiconductor packages comprises:
Semiconductor chip comprises reciprocal first surface and second surface, and described semiconductor chip has conductive pattern and passivation layer, and described passivation layer covers described first surface and has the opening that exposes described conductive pattern;
Resilient coating covers the whole sidewall of described semiconductor chip basically;
Moulding layer covers described resilient coating; And
Redistributing layer is arranged on the basal surface of described passivation layer, and described redistributing layer is electrically connected to described conductive pattern.
31. semiconductor packages as claimed in claim 30, the top surface of wherein said semiconductor chip contacts with described moulding layer.
32. semiconductor packages as claimed in claim 30, wherein said redistributing layer directly contacts with described passivation layer.
33. a semiconductor packages comprises:
Semiconductor chip has pad;
Passivation layer is formed on described semiconductor chip, and described passivation layer has the opening that exposes described pad;
Resilient coating covers described semiconductor chip;
Moulding layer covers described resilient coating; And
Redistributing layer is electrically connected to described pad,
Wherein said redistributing layer directly contacts with described passivation layer.
34. semiconductor packages as claimed in claim 1, wherein said redistributing layer is formed directly on the basal surface of described resilient coating.
35. the formation method of a semiconductor packages, the method comprises:
First semiconductor chip that will comprise the first conductive pattern is placed on carrier;
Form the top surface of described the first semiconductor chip of covering and the resilient coating of sidewall;
Form moulding layer on described resilient coating;
Described the first semiconductor chip is separated with described carrier; And
Form the first redistributing layer that is electrically connected to described the first conductive pattern on the basal surface of described the first semiconductor chip.
36. method as claimed in claim 35 wherein forms described resilient coating and comprises:
The described resilient coating of coating on described the first semiconductor chip.
37. method as claimed in claim 36 also comprises:
The a part described resilient coating of removal on described the first semiconductor chip is to expose the top surface of described the first semiconductor chip.
38. method as claimed in claim 35 also comprises:
Before forming described resilient coating, place the second semiconductor chip that comprises the second conductive pattern, not overlapping described the first semiconductor chip of this second conductive pattern on described the first semiconductor chip; And
Before forming described the first redistributing layer, the described resilient coating of patterning exposes the hole of described the second conductive pattern with formation,
Wherein said the first redistributing layer is filled described hole.
39. method as claimed in claim 35 also comprises:
Before the described resilient coating of formation, the second semiconductor chip is installed on described the first semiconductor chip,
Wherein said resilient coating extends at least one sidewall that covers described the second semiconductor chip.
40. method as claimed in claim 35 also comprises:
The described moulding layer of patterning and described resilient coating expose the hole of described the first redistributing layer with formation; And
Form through hole in described hole.
41. method as claimed in claim 40 also comprises:
Form the second redistributing layer that is electrically connected to described through hole on described moulding layer.
42. method as claimed in claim 40 also comprises:
Installation is electrically connected to the semiconductor-on-insulator encapsulation of described through hole.
43. method as claimed in claim 35 also comprises:
The a part described resilient coating of removal on described the first semiconductor chip is to expose the top surface of described the first semiconductor chip.
44. the formation method of a semiconductor packages comprises:
Place a plurality of semiconductor chips on carrier, each semiconductor chip comprises having opening with the passivation layer of exposed pad;
With the described a plurality of semiconductor chips of buffer coated, make all sidewalls basically of described a plurality of semiconductor chips be covered by described resilient coating;
Formation is positioned at the moulding layer on described resilient coating; And
Formation is electrically connected in described a plurality of semiconductor chip the redistributing layer of the pad of corresponding.
45. method as claimed in claim 44, wherein said redistributing layer directly contacts with described resilient coating with described passivation layer.
46. method as claimed in claim 44 wherein applies described a plurality of semiconductor chip and comprises the dorsal part that applies described a plurality of semiconductor chips and the described sidewall of described a plurality of semiconductor chips.
CN2013101595306A 2012-05-03 2013-05-03 Semiconductor encapsulation and forming method thereof Pending CN103383927A (en)

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KR1020120046997A KR20130123682A (en) 2012-05-03 2012-05-03 Semiconductor pacakge and method of forming the package
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US13/651,453 US20130295725A1 (en) 2012-05-03 2012-10-14 Semiconductor package and method of forming the same

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