KR102190390B1 - Semiconductor package and method of fabricating the same - Google Patents

Semiconductor package and method of fabricating the same Download PDF

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Publication number
KR102190390B1
KR102190390B1 KR1020130134937A KR20130134937A KR102190390B1 KR 102190390 B1 KR102190390 B1 KR 102190390B1 KR 1020130134937 A KR1020130134937 A KR 1020130134937A KR 20130134937 A KR20130134937 A KR 20130134937A KR 102190390 B1 KR102190390 B1 KR 102190390B1
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South Korea
Prior art keywords
substrate
semiconductor package
semiconductor
semiconductor chip
conductive pattern
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KR1020130134937A
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Korean (ko)
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KR20150053128A (en
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박진우
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삼성전자주식회사
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Priority to KR1020130134937A priority Critical patent/KR102190390B1/en
Priority to US14/463,854 priority patent/US9224710B2/en
Publication of KR20150053128A publication Critical patent/KR20150053128A/en
Application granted granted Critical
Publication of KR102190390B1 publication Critical patent/KR102190390B1/en

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    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

본 발명은 반도체 패키지를 제공한다. 이 반도체 패키지에서는, 하부 패키지와 상부 패키지가 와이어에 의해 전기적으로 연결된다. 와이어는 솔더볼에 비하여 두께가 매우 가늘기 때문에 하부 패키지와 상부 패키지 간에 더 많은 채널 수 및/또는 입출력 패드를 적용할 수 있다. The present invention provides a semiconductor package. In this semiconductor package, the lower package and the upper package are electrically connected by wires. Since the wire is very thin compared to the solder ball, a larger number of channels and/or input/output pads can be applied between the lower package and the upper package.

Figure R1020130134937
Figure R1020130134937

Description

반도체 패키지 및 이의 제조 방법{Semiconductor package and method of fabricating the same}Semiconductor package and method of fabricating the same {Semiconductor package and method of fabricating the same}

본 발명은 반도체 패키지 및 이의 제조 방법에 관한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same.

전자 산업의 발달로 전자 부품의 고기능화, 고속화 및 소형화 요구가 증대되고 있다. 이러한 추세에 대응하여 현재 반도체 실장 기술은 하나의 패키지 기판에 여러 반도체 칩들을 적층하여 실장하거나 패키지 위에 패키지를 적층하는 방법이 대두되고 있다. 이중에 특히 패키지 위에 패키지를 적층하는 반도체 패키지를 패키지 온 패키지(Package on package, PoP) 장치라고도 한다. 모바일에 장착되는 패키지 온 패키지 장치는 고대역폭(high bandwidth)의 주파수를 수용하기 위하여 다채널과 많은 입출력 패드의 특성이 요구된다. 따라서 패키지 온 패키지 장치에서, 하부 패키지와 상부 패키지 간에 더 많은 채널 수 및/또는 입출력 패드를 적용하기 위하여 연구가 진행되고 있다. With the development of the electronic industry, the demand for high functionality, high speed and miniaturization of electronic components is increasing. In response to this trend, in the current semiconductor mounting technology, a method of stacking and mounting multiple semiconductor chips on a single package substrate or stacking a package on a package is emerging. Among them, a semiconductor package in which packages are stacked on a package is also referred to as a package on package (PoP) device. A package-on-package device mounted on a mobile device requires characteristics of multiple channels and many input/output pads in order to accommodate frequencies of high bandwidth. Therefore, in a package-on-package device, research is being conducted to apply a larger number of channels and/or input/output pads between the lower package and the upper package.

본 발명이 해결하고자 하는 과제는 하부 패키지와 상부 패키지 간에 더 많은 채널 수 및/또는 입출력 패드를 적용할 수 있는 반도체 패키지를 제공하는데 있다. The problem to be solved by the present invention is to provide a semiconductor package in which a larger number of channels and/or input/output pads can be applied between a lower package and an upper package.

본 발명이 해결하고자 하는 다른 과제는 상기 반도체 패키지의 제조 방법을 제공하는데 있다. Another problem to be solved by the present invention is to provide a method of manufacturing the semiconductor package.

상기 과제를 달성하기 위한 본 발명의 일 예에 따른 반도체 패키지는, 제 1 기판; 상기 제 1 기판 상에 실장된 제 1 반도체 칩; 상기 제 1 반도체 칩 상에 배치되는 제 2 기판; 상기 제 2 기판 상에 배치되는 적어도 하나의 제 2 반도체 칩; 및 상기 제 2 기판과 상기 제 1 기판을 전기적으로 연결하되 적어도 상기 제 1 기판과 접하는 와이어들을 포함한다.A semiconductor package according to an embodiment of the present invention for achieving the above object includes: a first substrate; A first semiconductor chip mounted on the first substrate; A second substrate disposed on the first semiconductor chip; At least one second semiconductor chip disposed on the second substrate; And wires electrically connecting the second substrate and the first substrate and contacting at least the first substrate.

상기 제 2 기판은 상기 제 1 기판보다 넓은 폭을 가질 수 있다. The second substrate may have a wider width than the first substrate.

적어도 상기 제 2 기판의 일 가장자리는 제 1 기판의 측면 옆으로 돌출될 수 있다. At least one edge of the second substrate may protrude toward a side of the first substrate.

상기 반도체 패키지는, 적어도 상기 제 1 반도체 칩의 측면과 상기 제 1 기판을 덮는 몰드막을 더 포함할 수 있다.The semiconductor package may further include a mold layer covering at least a side surface of the first semiconductor chip and the first substrate.

상기 반도체 패키지는, 상기 제 1 반도체 칩과 상기 제 2 기판 사이에 개재되어 이들을 접착시키는 접착막을 더 포함할 수 있다.The semiconductor package may further include an adhesive film interposed between the first semiconductor chip and the second substrate to bond them.

상기 반도체 패키지는, 상기 제 2 기판 상에 배치되어 상기 제 2 기판과 전기적으로 연결되며 상기 제 2 반도체 칩이 실장되는 제 3 기판을 더 포함할 수 있다. The semiconductor package may further include a third substrate disposed on the second substrate, electrically connected to the second substrate, and on which the second semiconductor chip is mounted.

상기 반도체 패키지는 상기 2 기판과 상기 제 3 기판 사이에 개재되어 이들을 전기적으로 연결시키는 솔더볼들을 더 포함할 수 있다.The semiconductor package may further include solder balls interposed between the second substrate and the third substrate to electrically connect them.

상기 반도체 패키지는, 상기 와이어들을 덮는 보호 부재를 더 포함할 수 있다. 상기 보호부재는 몰드막, 접착성 수지 또는 홀더를 포함할 수 있다.The semiconductor package may further include a protection member covering the wires. The protective member may include a mold film, an adhesive resin, or a holder.

일 예에 있어서, 상기 제 1 반도체 칩은 로직 칩이며, 상기 제 2 반도체 칩은 메모리 칩일 수 있다. In one example, the first semiconductor chip may be a logic chip, and the second semiconductor chip may be a memory chip.

상기 제 1 기판의 가장자리는 단차진 구조를 가질 수 있다. 이때, 상기 제 1 기판은 높이가 다른 제 1 기판 도전 패턴과 제 2 기판 도전 패턴을 포함하고, 상기 제 2 기판은 서로 이격된 제 3 기판 도전 패턴과 제 4 기판 도전 패턴을 포함하고, 상기 와이어들은 상기 제 1 기판 도전 패턴과 상기 제 3 기판 도전 패턴을 연결하는 제 1 와이어와 상기 제 2 기판 도전 패턴과 상기 제 4 기판 도전 패턴을 연결하는 제 2 와이어를 포함할 수 있다.The edge of the first substrate may have a stepped structure. In this case, the first substrate includes a first substrate conductive pattern and a second substrate conductive pattern having different heights, the second substrate includes a third substrate conductive pattern and a fourth substrate conductive pattern spaced apart from each other, and the wire They may include a first wire connecting the first substrate conductive pattern and the third substrate conductive pattern, and a second wire connecting the second substrate conductive pattern and the fourth substrate conductive pattern.

상기 반도체 패키지는, 상기 제 2 기판 상에 배치되어 상기 제 2 기판과 전기적으로 연결되며 상기 제 2 반도체 칩이 실장되는 제 3 기판을 더 포함하되, 상기 와이어들은 상기 제 1 기판, 상기 제 2 기판 및 상기 제 3 기판을 연속적으로 연결할 수 있다.The semiconductor package further includes a third substrate disposed on the second substrate, electrically connected to the second substrate, and mounting the second semiconductor chip, wherein the wires are the first substrate and the second substrate And the third substrate may be connected continuously.

상기 반도체 패키지는, 상기 제 1 기판 하부에 부착되는 솔더볼들을 더 포함할 수 있다. The semiconductor package may further include solder balls attached to a lower portion of the first substrate.

본 발명의 일 예에 따른 반도체 패키지는, 차례로 적층된 제 1 서브 반도체 패키지와 제 2 서브 반도체 패키지; 및 상기 제 1 서브 반도체 패키지와 상기 제 2 서브 반도체 패키지를 전기적으로 연결시키는 와이어들을 포함한다. A semiconductor package according to an embodiment of the present invention includes: a first sub-semiconductor package and a second sub-semiconductor package sequentially stacked; And wires electrically connecting the first sub semiconductor package and the second sub semiconductor package.

상기 제 2 서브 반도체 패키지의 적어도 일 단부는 상기 제 1 서브 반도체 패키의 측면 보다 옆으로 돌출될 수 있다. At least one end of the second sub-semiconductor package may protrude laterally than a side surface of the first sub-semiconductor package.

상기 제 2 서브 반도체 패키지는 상기 제 1 서브 반도체 패키지 보다 넓은 폭을 가질 수 있다. The second sub-semiconductor package may have a wider width than the first sub-semiconductor package.

일 예에서, 상기 반도체 패키지는, 상기 제 1 서브 반도체 패키지와 상기 제 2 서브 반도체 패키지 사이에 개재되는 인터포저 기판을 더 포함하되, 상기 와이어들은 상기 인터포저 기판과 상기 제 1 서브 반도체 패키지를 전기적으로 연결시킬 수 있다. In one example, the semiconductor package further includes an interposer substrate interposed between the first sub-semiconductor package and the second sub-semiconductor package, wherein the wires electrically connect the interposer substrate and the first sub-semiconductor package. Can be connected by

다른 예에서, 상기 제 1 서브 반도체 패키지는 제 1 기판을 포함하고, 상기 제 2 서브 반도체 패키지는 제 2 기판을 포함하고, 상기 제 1 서브 반도체 패키지와 상기 제 2 서브 반도체 패키지는 접착막에 의해 접착되고, 상기 와이어들은 상기 제 1 기판과 상기 제 2 기판을 연결시킬 수 있다.In another example, the first sub-semiconductor package includes a first substrate, the second sub-semiconductor package includes a second substrate, and the first sub-semiconductor package and the second sub-semiconductor package are formed by an adhesive layer. Bonded, the wires may connect the first substrate and the second substrate.

또 다른 예에서, 상기 제 1 서브 반도체 패키지는 제 1 기판을 포함하고, 상기 제 1 기판의 가장자리는 단차진 구조를 가질 수 있다. In another example, the first sub-semiconductor package may include a first substrate, and an edge of the first substrate may have a stepped structure.

본 발명의 일 예에 따른 반도체 패키지에서는, 하부 패키지와 상부 패키지가 와이어에 의해 전기적으로 연결된다. 와이어는 솔더볼에 비하여 두께가 매우 가늘기 때문에 하부 패키지와 상부 패키지 간에 더 많은 채널 수 및/또는 입출력 패드를 적용할 수 있다. In the semiconductor package according to an embodiment of the present invention, the lower package and the upper package are electrically connected by wires. Since the wire is very thin compared to the solder ball, a larger number of channels and/or input/output pads can be applied between the lower package and the upper package.

상기 반도체 패키지에서, 제 1 서브 반도체 패키지가 제 2 서브 반도체 패키지 상에 부착되고 상기 제 1 서브 반도체 패키지의 제 1 기판과 상기 제 2 서브 반도체 패키지의 제 2 기판이 와이어들에 의해 전기적으로 연결될 수 잇다. 이로써 상기 서브 반도체 패키지들 간의 전기적 경로가 모두 와이어들에 의해 진행되어 입출력 패드 수를 더욱 증대시킬 수 있다. In the semiconductor package, a first sub-semiconductor package may be attached to a second sub-semiconductor package, and a first substrate of the first sub-semiconductor package and a second substrate of the second sub-semiconductor package may be electrically connected by wires. connect. Accordingly, electrical paths between the sub-semiconductor packages are all carried out by wires, thereby further increasing the number of input/output pads.

일 예에 따른 반도체 패키지에서 제 1 기판의 가장자리는 단차진 구조를 가질 수 있으며, 이로 인해 와이어들이 쳐져서 서로 맞닿을 위험을 줄일 수 있다. 이로써 입출력 수를 두배 이상으로 늘릴 수 있다.In the semiconductor package according to an example, the edge of the first substrate may have a stepped structure, and thus, the risk of the wires hitting each other may be reduced. This allows the number of inputs and outputs to be doubled or more.

또한 서브 반도체 패키지들 간의 연결을 솔더볼을 이용하지 않으므로 레이저를 이용하여 몰드막에 구멍을 뚫을 필요가 없어 공정을 단순화시킬 수 있다. In addition, since solder balls are not used for connection between the sub-semiconductor packages, there is no need to drill holes in the mold film using a laser, thereby simplifying the process.

도 1은 본 발명의 일 예에 따른 반도체 패키지의 레이아웃이다.
도 2는 도 1을 I-I'선으로 자른 단면도이다.
도 3 내지 도 10은 도 2의 단면을 가지는 반도체 패키지의 제조 과정을 순차적으로 나타내는 단면도들이다.
도 11은 본 발명의 다른 예에 따른 반도체 패키지의 단면도이다.
도 12 내지 도 14는 도 11의 단면을 가지는 반도체 패키지의 제조 과정을 나타내는 단면도들이다.
도 15 내지 도 22는 본 발명의 또 다른 예들에 따른 반도체 패키지의 단면도들이다.
도 23은 본 발명의 기술이 적용된 반도체 패키지를 포함하는 패키지 모듈의 예를 보여주는 도면이다.
도 24는 본 발명의 기술이 적용된 반도체 패키지를 포함하는 전자 장치의 예를 보여주는 블럭도이다.
도 25는 본 발명의 기술이 적용된 반도체 패키지를 포함하는 메모리 시스템의 예를 보여주는 블럭도이다.1 is a layout of a semiconductor package according to an example of the present invention.
2 is a cross-sectional view of FIG. 1 taken along line I-I'.
3 to 10 are cross-sectional views sequentially illustrating a manufacturing process of the semiconductor package having the cross-section of FIG. 2.
11 is a cross-sectional view of a semiconductor package according to another example of the present invention.
12 to 14 are cross-sectional views illustrating a manufacturing process of the semiconductor package having the cross-section of FIG. 11.
15 to 22 are cross-sectional views of semiconductor packages according to still other examples of the present invention.
23 is a diagram showing an example of a package module including a semiconductor package to which the technology of the present invention is applied.
24 is a block diagram showing an example of an electronic device including a semiconductor package to which the technology of the present invention is applied.
25 is a block diagram showing an example of a memory system including a semiconductor package to which the technology of the present invention is applied.

본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms different from each other, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have it, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same components throughout the specification.

소자(elements) 또는 층이 다른 소자 또는 층의 "위(on)" 또는 "상(on)"으로 지칭되는 것은 다른 소자 또는 층의 바로 위뿐만 아니라 중간에 다른 층 또는 다른 소자를 개재한 경우를 모두 포함한다. 반면, 소자가 "직접 위(directly on)" 또는 "바로 위"로 지칭되는 것은 중간에 다른 소자 또는 층을 개재하지 않은 것을 나타낸다. "및/또는"은 언급된 아이템들의 각각 및 하나 이상의 모든 조합을 포함한다.When an element or layer is referred to as “on” or “on” of another element or layer, it is possible to interpose another layer or other element in the middle as well as directly above the other element or layer. All inclusive. On the other hand, when a device is referred to as "directly on" or "directly on", it indicates that no other device or layer is interposed therebetween. "And/or" includes each and every combination of one or more of the recited items.

공간적으로 상대적인 용어인 "아래(below)", "아래(beneath)", "하부(lower)", "위(above)", "상부(upper)" 등은 도면에 도시되어 있는 바와 같이 하나의 소자 또는 구성 요소들과 다른 소자 또는 구성 요소들과의 상관관계를 용이하게 기술하기 위해 사용될 수 있다. 공간적으로 상대적인 용어는 도면에 도시되어 있는 방향에 더하여 사용시 또는 동작 시 소자의 서로 다른 방향을 포함하는 용어로 이해되어야 한다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다. Spatially relative terms "below", "beneath", "lower", "above", "upper", etc., as shown in the figure It may be used to easily describe the correlation between the device or components and other devices or components. Spatially relative terms should be understood as terms including different directions of the device during use or operation in addition to the directions shown in the drawings. The same reference numerals refer to the same components throughout the specification.

비록 제1, 제2 등이 다양한 소자, 구성요소 및/또는 섹션들을 서술하기 위해서 사용되나, 이들 소자, 구성요소 및/또는 섹션들은 이들 용어에 의해 제한되지 않음은 물론이다. 이들 용어들은 단지 하나의 소자, 구성요소 또는 섹션들을 다른 소자, 구성요소 또는 섹션들과 구별하기 위하여 사용하는 것이다. 따라서, 이하에서 언급되는 제1 소자, 제1 구성요소 또는 제1 섹션은 본 발명의 기술적 사상 내에서 제2 소자, 제2 구성요소 또는 제2 섹션일 수도 있음은 물론이다.Although the first, second, etc. are used to describe various elements, components and/or sections, of course, these elements, components and/or sections are not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, it goes without saying that the first element, the first element, or the first section mentioned below may be a second element, a second element, or a second section within the technical scope of the present invention.

본 명세서에서 기술하는 실시예들은 본 발명의 이상적인 개략도인 평면도 및 단면도를 참고하여 설명될 것이다. 따라서, 제조 기술 및/또는 허용 오차 등에 의해 예시도의 형태가 변형될 수 있다. 따라서, 본 발명의 실시예들은 도시된 특정 형태로 제한되는 것이 아니라 제조 공정에 따라 생성되는 형태의 변화도 포함하는 것이다. 따라서, 도면에서 예시된 영역들은 개략적인 속성을 가지며, 도면에서 예시된 영역들의 모양은 소자의 영역의 특정 형태를 예시하기 위한 것이고, 발명의 범주를 제한하기 위한 것은 아니다. Embodiments described in the present specification will be described with reference to a plan view and a cross-sectional view, which are ideal schematic diagrams of the present invention. Therefore, the shape of the exemplary diagram may be modified by manufacturing technology and/or tolerance. Accordingly, embodiments of the present invention are not limited to the specific form shown, but also include a change in form generated according to the manufacturing process. Accordingly, regions illustrated in the drawings have schematic properties, and the shapes of regions illustrated in the drawings are intended to illustrate a specific shape of the region of the device, and are not intended to limit the scope of the invention.

이하, 본 발명을 보다 구체적으로 설명하기 위하여 본 발명에 따른 실시예들을 첨부 도면을 참조하면서 보다 상세하게 설명하고자 한다.Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings in order to describe the present invention in more detail.

도 1은 본 발명의 일 예에 따른 반도체 패키지의 레이아웃이다. 도 2는 도 1을 I-I'선으로 자른 단면도이다.1 is a layout of a semiconductor package according to an example of the present invention. 2 is a cross-sectional view of FIG. 1 taken along line I-I'.

도 1 및 도 2를 참조하면, 본 예에 따른 반도체 패키지(200)에서는 제 1 기판(1) 상에 제 1 반도체 칩(10)이 제 1 솔더볼들(5)에 의해 플립 칩 본딩 방식으로 실장된다. 상기 제 1 기판(1)은 인쇄회로기판일 수 있다. 상기 제 1 기판(1)은 상하부면들에 제 11 내지 제 13 기판 도전 패턴들(3a, 3b, 3c)이 배치될 수 있고 상기 제 1 기판(1)의 내부에는 상기 제 11 내지 제 13 기판 도전 패턴들(3a, 3b, 3c)을 전기적으로 연결되는 관통 비아나 내부 배선들(미도시)이 배치될 수 있다. 상기 제 11 내지 제 13 기판 도전 패턴들(3a, 3b, 3c)은 상기 제 1 기판(1)의 하부면에 배치되는 제 11 기판 도전 패턴들(3a)과 제 12 기판 도전 패턴들(3b) 그리고 상기 제 1 기판(1)의 상부면에 배치되는 제 13 기판 도전 패턴들(3c)을 포함한다. 상기 제 13 기판 도전 패턴들(3c)에는 상기 제 1 솔더볼들(5)이 부착된다. 상기 제 11 기판 도전 패턴들(3a)에는 외부로부터 전기적 신호가 인가되는 제 2 솔더볼들(16)이 부착된다. 상기 제 1 반도체 칩(10)의 측면과 상기 제 1 기판(1)의 상부면은 제 1 몰드막(12)으로 덮인다. 상기 제 1 몰드막(12)은 상기 제 1 반도체 칩(10)과 상기 제 1 기판(1) 사이의 공간을 채울 수 있다. 상기 제 1 반도체 칩(10)은 예를 들면 로직 칩일 수 있다. 상기 제 1 기판(1), 상기 제 1 반도체 칩(10) 및 상기 제 1 몰드막(12) 등은 제 1 서브 반도체 패키지(101)를 구성할 수 있다. Referring to FIGS. 1 and 2, in the semiconductor package 200 according to the present example, the first semiconductor chip 10 is mounted on the first substrate 1 by flip chip bonding by first solder balls 5. do. The first substrate 1 may be a printed circuit board. The first substrate 1 may have eleventh to thirteenth substrate conductive patterns 3a, 3b, and 3c disposed on upper and lower surfaces, and the 11th to 13th substrates inside the first substrate 1 Through vias or internal wirings (not shown) electrically connecting the conductive patterns 3a, 3b, and 3c may be disposed. The eleventh to thirteenth substrate conductive patterns 3a, 3b, 3c are eleventh substrate conductive patterns 3a and twelfth substrate conductive patterns 3b disposed on the lower surface of the first substrate 1 And, it includes thirteenth substrate conductive patterns 3c disposed on the upper surface of the first substrate 1. The first solder balls 5 are attached to the thirteenth substrate conductive patterns 3c. Second solder balls 16 to which an electrical signal is applied from the outside are attached to the eleventh substrate conductive patterns 3a. A side surface of the first semiconductor chip 10 and an upper surface of the first substrate 1 are covered with a first mold layer 12. The first mold layer 12 may fill a space between the first semiconductor chip 10 and the first substrate 1. The first semiconductor chip 10 may be, for example, a logic chip. The first substrate 1, the first semiconductor chip 10, and the first mold layer 12 may constitute a first sub-semiconductor package 101.

계속해서 상기 제 1 반도체 칩(10) 상에는 제 2 기판(20)이 배치된다. 상기 제 2 기판(20)은 인터포저 기판일 수 있다. 상기 제 2 기판(20)은 하부면에 배치되는 제 21 기판 도전 패턴들(22)과 상부면에 배치되는 제 22 기판 도전 패턴들(24)을 포함한다. 상기 제 21 및 제 2 기판 도전 패턴들(22, 24)은 상기 제 2 기판(20) 내부에 배치되는 관통 비아와 내부 배선들(미도시)을 통해 전기적으로 연결될 수 있다. 상기 제 2 기판(20)의 하부면에는 상기 제 1 서브 반도체 패키지(101)가 제 1 접착막(14)에 의하여 접착될 수 있다. Subsequently, a second substrate 20 is disposed on the first semiconductor chip 10. The second substrate 20 may be an interposer substrate. The second substrate 20 includes 21st substrate conductive patterns 22 disposed on a lower surface and 22nd substrate conductive patterns 24 disposed on an upper surface. The 21st and second substrate conductive patterns 22 and 24 may be electrically connected through a through via disposed inside the second substrate 20 and internal wirings (not shown). The first sub-semiconductor package 101 may be adhered to the lower surface of the second substrate 20 by a first adhesive layer 14.

상기 제 2 기판(20) 상에는 제 3 기판(30)이 배치된다. 상기 제 3 기판(30)은 인쇄회로기판일 수 있다. 상기 제 3 기판(30)은 하부면에 배치되는 제 31 기판 도전 패턴들(32)과 상부면에 배치되는 제 32 기판 도전 패턴들(34)을 포함한다. 상기 제 3 기판(30)과 상기 제 2 기판(20)은 전기적으로 연결된다. 즉, 상기 제 22 기판 도전 패턴(24)과 상기 제 31 기판 도전 패턴(32)은 이들 사이에 개재되는 제 3 솔더볼들(38)에 의해 전기적으로 연결된다. 상기 제 3 기판(30)에는 제 2 반도체 칩들(40a, 40b)이 적층되어 배치될 수 있다. 상기 제 2 반도체 칩들(40a, 40b)은 서로 동일한 종류이며, 예를 들면 메모리 칩일수 있다. 상기 제 2 반도체 칩들(40a, 40b)은 상기 제 3 기판(30) 상에 제 2 접착막(44)에 의하여 부착될 수 있다. 상기 제 2 반도체 칩들(40a, 40b)은 양 단부들에 칩 도전 패턴들(42)을 포함할 수 있다. 상기 칩 도전 패턴들(42)과 상기 제 32 기판 도전 패턴들(34)은 제 1 와이어들(46)로 연결된다. 상기 제 2 반도체 칩들(40a, 40b)과 상기 제 3 기판(30)은 제 2 몰드막(48)으로 덮일 수 있다. 상기 제 3 기판(30), 상기 제 2 반도체 칩들(40a, 40b) 및 상기 제 2 몰드막(48) 등은 제 2 서브 반도체 패키지(102)를 구성할 수 있다. A third substrate 30 is disposed on the second substrate 20. The third substrate 30 may be a printed circuit board. The third substrate 30 includes thirty-first substrate conductive patterns 32 disposed on a lower surface and thirty-two substrate conductive patterns 34 disposed on an upper surface. The third substrate 30 and the second substrate 20 are electrically connected. That is, the 22nd substrate conductive pattern 24 and the 31st substrate conductive pattern 32 are electrically connected by third solder balls 38 interposed therebetween. Second semiconductor chips 40a and 40b may be stacked and disposed on the third substrate 30. The second semiconductor chips 40a and 40b are of the same type and may be, for example, memory chips. The second semiconductor chips 40a and 40b may be attached to the third substrate 30 by a second adhesive layer 44. The second semiconductor chips 40a and 40b may include chip conductive patterns 42 at both ends. The chip conductive patterns 42 and the 32nd substrate conductive patterns 34 are connected by first wires 46. The second semiconductor chips 40a and 40b and the third substrate 30 may be covered with a second mold layer 48. The third substrate 30, the second semiconductor chips 40a and 40b, and the second mold layer 48 may constitute the second sub-semiconductor package 102.

상기 제 3 기판(30)은 상기 제 1 기판(1) 보다 넓은 폭을 가진다. 본 예에서 상기 제 3 기판(30)의 모든 가장자리는 상기 제 1 기판(1)의 측면 보다 옆으로 돌출될 수 있다. The third substrate 30 has a wider width than the first substrate 1. In this example, all edges of the third substrate 30 may protrude laterally than a side surface of the first substrate 1.

상기 제 1 기판(1)과 상기 제 2 기판(20)은 전기적으로 연결된다. 구체적으로 상기 제 12 기판 도전 패턴들(3b)과 상기 제 21 기판 도전 패턴들(22)은 제 2 와이어들(26)로 연결된다. 상기 제 2 와이어들(26)은 보호부재(28)로 덮여 보호될 수 있다. 상기 보호부재(28)는 몰드막이나 접착 수지일 수 있다. 상기 제 1 와이어들(46) 및 상기 제 2 와이어들(26)은 금, 은, 구리와 같은 적절한 연성 특성을 가지는 금속으로 형성될 수 있다. 상기 제 2 솔더볼들(16)의 높이는 상기 12 기판 도전 패턴(3b)의 표면상의 상기 보호부재(28)의 두께보다 높다. The first substrate 1 and the second substrate 20 are electrically connected. Specifically, the twelfth substrate conductive patterns 3b and the twenty-first substrate conductive patterns 22 are connected by second wires 26. The second wires 26 may be covered and protected by a protection member 28. The protection member 28 may be a mold film or an adhesive resin. The first wires 46 and the second wires 26 may be formed of a metal having appropriate ductility characteristics such as gold, silver, or copper. The height of the second solder balls 16 is higher than the thickness of the protective member 28 on the surface of the 12 substrate conductive pattern 3b.

와이어들의 통상적인 두께는 예를 들면 약 12.5~350㎛일 수 있다. 솔더볼들의 통상적인 직경은 예를 들면 0.3~0.7mm로 이는 300~700㎛에 해당할 수 있다. 따라서 최소값으로 보면 와이어들은 솔더볼의 직경의 약 4/100 에 해당하는 두께를 가질 수 있다. 또한 솔더볼들을 사용할 경우, 솔더볼 부착시 솔더볼들간의 short를 방지하기 위하여 솔더볼들 간에 간격도 수백㎛ 이상 유지되어야한다. 따라서 제 1 반도체 칩(10)과 제 2 반도체 칩들(40a, 40b)을 연결하는 입출력 단자들을 증가시키기 위하여 제한된 반도체 패키지 면적 내에서 솔더볼은 그 크기에 의해 사용 갯수에 제약이 따르게 마련이다. 그러나 본 발명에서는 솔더볼들보다는 매우 얇은 두께를 가지는 제 2 와이어들(26)로 제 1 기판(101)과 제 2 기판(20)을 연결하므로 입출력 단자들의 수를 원하는 만큼 증대시킬 수 있다. Typical thickness of the wires may be, for example, about 12.5-350 μm. The typical diameter of the solder balls is, for example, 0.3-0.7mm, which may correspond to 300-700㎛. Therefore, as a minimum value, the wires can have a thickness corresponding to about 4/100 of the diameter of the solder ball. In addition, when using solder balls, the spacing between the solder balls must be kept at least several hundred μm in order to prevent short between the solder balls when the solder balls are attached. Therefore, in order to increase the number of input/output terminals connecting the first semiconductor chip 10 and the second semiconductor chips 40a and 40b, the number of solder balls used within a limited semiconductor package area is limited by the size. However, in the present invention, since the first substrate 101 and the second substrate 20 are connected with the second wires 26 having a very thin thickness than the solder balls, the number of input/output terminals can be increased as desired.

본 예에 따른 상기 반도체 패키지(200)는 제 1 서브 반도체 패키지(101) 상에 제 2 서브 반도체 패키지(102)가 적층되되 중간에 인터포저 기판(20)이 개재된 패키지 온 패키지 장치에 해당될 수 있다. The semiconductor package 200 according to this example may correspond to a package-on-package device in which a second sub-semiconductor package 102 is stacked on the first sub-semiconductor package 101, and an interposer substrate 20 is interposed therebetween. I can.

도 3 내지 도 10은 도 2의 단면을 가지는 반도체 패키지의 제조 과정을 순차적으로 나타내는 단면도들이다.3 to 10 are cross-sectional views sequentially illustrating a manufacturing process of the semiconductor package having the cross-section of FIG. 2.

도 3을 참조하면, 제 1 기판(1) 상에 제 1 반도체 칩(10)을 제 1 솔더볼들(5)을 이용하여 플립 칩 본딩 방식으로 실장한다. 상기 제 1 기판(1)은 제 11 내지 제 13 기판 도전 패턴들(3a, 3b, 3c)을 포함한다.Referring to FIG. 3, a first semiconductor chip 10 is mounted on a first substrate 1 by flip chip bonding using first solder balls 5. The first substrate 1 includes eleventh to thirteenth substrate conductive patterns 3a, 3b, and 3c.

도 4를 참조하면, 몰딩 공정을 진행하여 상기 제 1 반도체 칩(10)의 측면과 상기 제 1 기판(1)의 상부면을 덮는 제 1 몰드막(12)을 형성한다. 이때 상기 제 1 몰드막(12)은 상기 제 1 기판(1)과 상기 제 1 반도체 칩(10) 사이의 공간을 채울 수 있다. 상기 제 1 몰드막(12)은 몰딩 공정에서 상기 제 1 반도체 칩(10)의 상부면을 노출시키도록 형성될 수 있다. 또는 상기 제 1 몰드막(12)은 상기 제 1 반도체 칩(10)의 상부면까지 덮도록 형성된 후에 후속에 평탄화 식각 공정으로 제거되어 상기 제 1 반도체 칩(10)의 상부면을 노출시킬 수 있다. 이로써 제 1 서브 반도체 패키지(101)를 형성할 수 있다. Referring to FIG. 4, a molding process is performed to form a first mold layer 12 covering a side surface of the first semiconductor chip 10 and an upper surface of the first substrate 1. In this case, the first mold layer 12 may fill a space between the first substrate 1 and the first semiconductor chip 10. The first mold layer 12 may be formed to expose the upper surface of the first semiconductor chip 10 in a molding process. Alternatively, the first mold layer 12 may be formed to cover the upper surface of the first semiconductor chip 10 and then removed by a planarization etching process to expose the upper surface of the first semiconductor chip 10. . Accordingly, the first sub-semiconductor package 101 can be formed.

도 5를 참조하면, 노출된 상기 제 1 반도체 칩(10)의 상부면과 상기 제 1 몰드막(12)의 상부면을 덮도록 제 1 접착막(14)을 형성한다. 상기 제 1 접착막(14)은 양면 테이프이거나 또는 액상 접착제일 수 있다.Referring to FIG. 5, a first adhesive layer 14 is formed to cover the exposed upper surface of the first semiconductor chip 10 and the upper surface of the first mold layer 12. The first adhesive layer 14 may be a double-sided tape or a liquid adhesive.

도 6을 참조하면, 상기 제 1 서브 반도체 패키지(101)를 뒤집는다. 그리고 상기 제 1 접착막(14)을 이용하여 상기 제 1 서브 반도체 패키지(101)를 제 2 기판(20)에 부착한다. 상기 제 2 기파(20)은 하부면과 상부면에 각각 제 21 기판 도전 패턴(22)과 제 22 기판 도전 패턴(24)을 포함한다.Referring to FIG. 6, the first sub semiconductor package 101 is turned over. Then, the first sub-semiconductor package 101 is attached to the second substrate 20 by using the first adhesive layer 14. The second wave 20 includes a 21st substrate conductive pattern 22 and a 22nd substrate conductive pattern 24 on a lower surface and an upper surface, respectively.

도 7을 참조하면, 와이어 본딩 공정을 진행하여 상기 제 12 기판 도전 패턴들(3b)과 상기 제 21 기판 도전 패턴들(22)을 제 2 와이어들(26)로 연결시킨다.Referring to FIG. 7, a wire bonding process is performed to connect the twelfth substrate conductive patterns 3b and the 21st substrate conductive patterns 22 with second wires 26.

도 8을 참조하면, 상기 제 2 와이어들(26)을 덮는 보호 부재(28)을 형성한다. 상기 보호부재(28)는 몰딩 공정이나 프린팅 방법으로 형성될 수 있다. 상기 보호부재(28)는 몰드막이나 접착성 수지 등으로 형성될 수 있다. 상기 보호부재(28)는 더 나아가 상기 제 1 기판(1)의 단부와 측면, 상기 제 1 몰드막(12)과 상기 제 1 접착막(14)의 측면들 및 상기 제 2 기판(20)의 상부면을 덮도록 형성될 수 있다. Referring to FIG. 8, a protective member 28 covering the second wires 26 is formed. The protection member 28 may be formed by a molding process or a printing method. The protection member 28 may be formed of a mold film or an adhesive resin. The protection member 28 further comprises the end and side surfaces of the first substrate 1, the side surfaces of the first mold layer 12 and the first adhesive layer 14, and the second substrate 20. It may be formed to cover the upper surface.

도 9를 참조하면, 상기 제 11 기판 도전 패턴들(3a)에 제 2 솔더볼들(16)을 부착시킨다. Referring to FIG. 9, second solder balls 16 are attached to the eleventh substrate conductive patterns 3a.

도 10을 참조하면, 상기 제 2 기판(20)에 부착된 상기 제 1 서브 반도체 패키지(101)를 뒤집는다. 그리고 제 2 서브 반도체 패키지(102)를 준비한다. 상기 제 1 서브 반도체 패키지(102)는 위에서 설명한 바와 같이 제 3 기판(30), 이 위에 적층된 제 2 반도체 칩들(40a, 40b) 및 이들을 덮는 제 2 몰드막(48), 그리고 상기 제 3 기판(30) 하부에 부착된 제 3 솔더볼들(38) 등을 포함한다. 상기 제 2 기판(20) 상에 상기 제 2 서브 반도체 패키지(102)를 위치시킨다. 그리고 상기 제 3 솔더볼들(38)을 가열하여 상기 제 22 기판 도전 패턴들(24)에 부착시켜 상기 제 2 기판(20)과 상기 제 3 기판(30)을 전기적으로 연결시킨다.Referring to FIG. 10, the first sub semiconductor package 101 attached to the second substrate 20 is turned over. Then, a second sub-semiconductor package 102 is prepared. As described above, the first sub-semiconductor package 102 includes a third substrate 30, second semiconductor chips 40a and 40b stacked thereon, a second mold layer 48 covering them, and the third substrate. (30) It includes third solder balls 38 attached to the lower part. The second sub-semiconductor package 102 is positioned on the second substrate 20. Further, the third solder balls 38 are heated and attached to the 22nd substrate conductive patterns 24 to electrically connect the second substrate 20 and the third substrate 30.

도 11은 본 발명의 다른 예에 따른 반도체 패키지의 단면도이다.11 is a cross-sectional view of a semiconductor package according to another example of the present invention.

도 11을 참조하면, 본 예에 따른 반도체 패키지(201)는 제 1 서브 반도체 패키지(101) 상에 제 2 서브 반도체 패키지(102a)가 배치되나, 이들 사이에 인터포저 기판인 제 2 기판(20)은 존재하지 않는다. 이로써 도 2에 있었던 상기 제 2 기판(20)과 제 3 기판(30)을 전기적으로 연결해주던 제 3 솔더볼들(38)도 존재하지 않는다. 상기 제 1 서브 반도체 패키지(101)는 상기 제 3 기판(30)의 하부면에 제 1 접착막(14)을 개재하여 바로 접착된다. 그리고 제 2 와이어들(26)은 제 12 기판 도전 패턴들(3b)과 제 31 기판 도전 패턴들(32)을 연결한다. 보호 부재(28)는 상기 제 2 와이어들(26), 상기 제 1 기판(1)의 단부와 측면, 상기 제 1 몰드막(12)과 상기 제 1 접착막(14)의 측면들 및 상기 제 3 기판(20)의 하부면을 덮도록 형성될 수 있다. 그 외의 구성은 도 2를 참조하여 설명한 바와 동일/유사할 수 있다. Referring to FIG. 11, in the semiconductor package 201 according to the present example, a second sub-semiconductor package 102a is disposed on a first sub-semiconductor package 101, but a second substrate 20 that is an interposer substrate between them. ) Does not exist. As a result, there are no third solder balls 38 that electrically connect the second substrate 20 and the third substrate 30 in FIG. 2. The first sub-semiconductor package 101 is directly adhered to the lower surface of the third substrate 30 through a first adhesive layer 14. In addition, the second wires 26 connect the twelfth substrate conductive patterns 3b and the 31st substrate conductive patterns 32. The protective member 28 includes the second wires 26, the end and side surfaces of the first substrate 1, the side surfaces of the first mold layer 12 and the first adhesive layer 14, and the first 3 It may be formed to cover the lower surface of the substrate 20. Other configurations may be the same as/similar to those described with reference to FIG. 2.

상기 반도체 패키지(201)는 상기 제 1 서브 반도체 패키지(101)와 상기 제 2 서브 반도체 패키지(102a) 간의 전기적 경로가 모두 상기 제 2 와이어들(26)을 통하여 이루어지므로 입출력 패드 수를 더욱 증대시킬 수 있다. In the semiconductor package 201, since all electrical paths between the first sub-semiconductor package 101 and the second sub-semiconductor package 102a are made through the second wires 26, the number of input/output pads can be further increased. I can.

도 12 내지 도 14는 도 11의 단면을 가지는 반도체 패키지의 제조 과정을 나타내는 단면도들이다.12 to 14 are cross-sectional views illustrating a manufacturing process of the semiconductor package having the cross-section of FIG. 11.

도 12를 참조하면, 도 5의 상태의 제 1 서브 반도체 패키지(101)를 준비한다. 상기 제 1 서브 반도체 패키지(101)를 뒤집어서 상기 제 1 서브 반도체 패키지(101)를 제 2 서브 반도체 패키지(102a)의 제 3 기판(30)에 부착시킨다. Referring to FIG. 12, a first sub semiconductor package 101 in the state of FIG. 5 is prepared. The first sub-semiconductor package 101 is turned over and the first sub-semiconductor package 101 is attached to the third substrate 30 of the second sub-semiconductor package 102a.

도 13을 참조하면, 와이어 본딩 공정을 진행하여 상기 제 12 기판 도전 패턴들(3b)과 상기 제 31 기판 도전 패턴들(32)을 제 2 와이어들(26)로 연결시킨다.Referring to FIG. 13, a wire bonding process is performed to connect the twelfth substrate conductive patterns 3b and the 31st substrate conductive patterns 32 with second wires 26.

도 14를 참조하면, 상기 제 2 와이어들(26)을 덮는 보호 부재(28)을 형성한다. 상기 보호부재(28)는 몰딩 공정이나 프린팅 방법으로 형성될 수 있다. 상기 보호부재(28)는 몰드막이나 접착성 수지 등으로 형성될 수 있다. Referring to FIG. 14, a protective member 28 covering the second wires 26 is formed. The protection member 28 may be formed by a molding process or a printing method. The protection member 28 may be formed of a mold film or an adhesive resin.

후속으로 도 11을 참조하여, 상기 제 11 기판 도전 패턴들(3a)에 제 2 솔더볼들(16)을 부착시킨다.Subsequently, referring to FIG. 11, second solder balls 16 are attached to the eleventh substrate conductive patterns 3a.

도 15는 본 발명의 또 다른 예에 따른 반도체 패키지의 단면도이다.15 is a cross-sectional view of a semiconductor package according to another example of the present invention.

도 15를 참조하면, 본 예에 따른 반도체 패키지(202)에서는 제 1 서브 반도체 패키지(101a)의 제 1 반도체 칩(10)과 제 1 기판(1) 사이의 공간이 언더필 수지막(7)으로 채워진다. 그 외의 구성은 도 2를 참조하여 설명한 바와 동일/유사할 수 있다.Referring to FIG. 15, in the semiconductor package 202 according to the present example, a space between the first semiconductor chip 10 and the first substrate 1 of the first sub semiconductor package 101a is formed as an underfill resin film 7. Is filled. Other configurations may be the same as/similar to those described with reference to FIG. 2.

도 16은 본 발명의 또 다른 예에 따른 반도체 패키지의 단면도이다.16 is a cross-sectional view of a semiconductor package according to still another example of the present invention.

도 16을 참조하면, 본 예에 따른 반도체 패키지(203)에서는, 제 1 서브 반도체 패키지(101b)에서 제 1 반도체 칩(10)의 상부면이 제 1 몰드막(12)으로 덮일 수 있다. 그 외의 구성은 도 2를 참조하여 설명한 바와 동일/유사할 수 있다. Referring to FIG. 16, in the semiconductor package 203 according to the present example, the upper surface of the first semiconductor chip 10 in the first sub-semiconductor package 101b may be covered with the first mold layer 12. Other configurations may be the same as/similar to those described with reference to FIG. 2.

도 17은 본 발명의 또 다른 예에 따른 반도체 패키지의 단면도이다.17 is a cross-sectional view of a semiconductor package according to still another example of the present invention.

도 17을 참조하면, 본 예에 따른 반도체 패키지(204)에서는, 제 1 서브 반도체 패키지(101c)에서, 보호부재(28a)가 단단한 절연성 물질로 이루어질 수 있는 홀더(holder)일 수 있다. 상기 홀더는 예를 들면 폴리아미드와 같은 고분자 물질로 이루어질 수 있다. 도시하지는 않았지만, 상기 홀더인 상기 보호부재(28a)는 상기 와이어(26) 및 상기 제 1 몰드막(12)의 측면과 이격될 수 있다. 도시하지는 않았지만, 상기 보호부재(28a)와 상기 제 1 몰드막(12)의 측면 사이의 공간은 빈 공간으로 남을 수도 있고 또는 접착성 수지막으로 채워질 수 있다. 그 외의 구성은 도 2를 참조하여 설명한 바와 동일/유사할 수 있다. Referring to FIG. 17, in the semiconductor package 204 according to the present example, in the first sub-semiconductor package 101c, the protection member 28a may be a holder formed of a rigid insulating material. The holder may be made of a polymer material such as polyamide. Although not shown, the protection member 28a as the holder may be spaced apart from the side surfaces of the wire 26 and the first mold film 12. Although not shown, the space between the protection member 28a and the side surface of the first mold layer 12 may be left as an empty space or may be filled with an adhesive resin layer. Other configurations may be the same as/similar to those described with reference to FIG. 2.

도 18은 본 발명의 또 다른 예에 따른 반도체 패키지의 단면도이다.18 is a cross-sectional view of a semiconductor package according to still another example of the present invention.

도 18을 참조하면, 본 예에 따른 반도체 패키지(205)에서는, 제 1 서브 반도체 패키지(101d)에서, 제 1 기판(1)의 단부가 계단처럼 단차진 구조를 가질 수 있다. 이러한 단차진 구조에 높이가 다른 제 12 기판 도전 패턴(3b)와 제 14 기판 도전 패턴(3d)가 위치한다. 제 2 기판(20)의 하부면에는 서로 이격된 제 21 기판 도전 패턴(22a)과 제 23 기판 도전 패턴(22b)이 배치된다. 상기 제 12 기판 도전 패턴(3b)과 상기 제 21 기판 도전 패턴(22a)은 제 21 와이어(26a)에 의해 전기적으로 연결된다. 상기 제 14 기판 도전 패턴(3d)과 상기 제 23 기판 도전 패턴(22c)은 제 22 와이어(26b)에 의해 전기적으로 연결된다. 보호 부재(28)는 상기 제 21 및 제 22 와이어들(26a, 26b)을 모두 덮도록 형성된다. 그 외의 구성은 도 2를 참조하여 설명한 바와 동일/유사할 수 있다. Referring to FIG. 18, in the semiconductor package 205 according to the present example, in the first sub-semiconductor package 101d, the end of the first substrate 1 may have a stepped structure like a step. In this stepped structure, a twelfth substrate conductive pattern 3b and a fourteenth substrate conductive pattern 3d having different heights are positioned. A 21st substrate conductive pattern 22a and a 23rd substrate conductive pattern 22b spaced apart from each other are disposed on the lower surface of the second substrate 20. The twelfth substrate conductive pattern 3b and the twenty-first substrate conductive pattern 22a are electrically connected to each other by a 21st wire 26a. The 14th substrate conductive pattern 3d and the 23rd substrate conductive pattern 22c are electrically connected by a 22nd wire 26b. The protection member 28 is formed to cover all of the 21st and 22nd wires 26a and 26b. Other configurations may be the same as/similar to those described with reference to FIG. 2.

상기 반도체 패키지(205)는 상기 제 1 기판(1)의 가장자리가 단차진 구조를 가지므로 하나의 위치에서 상기 제 21 및 제 22 와이어들(26a, 26b)이 쳐져서 서로 맞닿을 위험을 줄일 수 있다. 이로써 입출력 수를 두배 이상으로 늘릴 수 있다.Since the semiconductor package 205 has a structure in which the edge of the first substrate 1 is stepped, the risk of contacting each other by striking the 21st and 22nd wires 26a and 26b at one position can be reduced. . This allows the number of inputs and outputs to be doubled or more.

도 19는 본 발명의 또 다른 예에 따른 반도체 패키지의 단면도이다.19 is a cross-sectional view of a semiconductor package according to another example of the present invention.

도 19를 참조하면, 본 예에 따른 반도체 패키지(206)에서는, 제 1 서브 반도체 패키지(101e)에서, 제 1 반도체 칩(10)은 제 1 기판(1)에 제 3 와이어들(6)을 이용하여 전기적으로 연결된다. 제 1 몰드막(12)은 상기 제 1 반도체 칩(10), 상기 제 1 기판(1) 및 상기 제 3 와이어들(6)을 덮는다. 그 외의 구성은 도 2를 참조하여 설명한 바와 동일/유사할 수 있다.Referring to FIG. 19, in the semiconductor package 206 according to the present example, in the first sub-semiconductor package 101e, the first semiconductor chip 10 connects third wires 6 to the first substrate 1. It is electrically connected by using. The first mold layer 12 covers the first semiconductor chip 10, the first substrate 1 and the third wires 6. Other configurations may be the same as/similar to those described with reference to FIG. 2.

도 20은 본 발명의 또 다른 예에 따른 반도체 패키지의 단면도이다.20 is a cross-sectional view of a semiconductor package according to still another example of the present invention.

도 20을 참조하면, 본 예에 따른 반도체 패키지(207)에서는, 제 2 반도체 패키지(102b)에서, 제 2 반도체 칩(40)이 제 3 기판(30)에 제 4 솔더볼들(45)을 이용하여 전기적으로 연결된다. 그 외의 구성은 도 19를 참조하여 설명한 바와 동일/유사할 수 있다.Referring to FIG. 20, in the semiconductor package 207 according to the present example, in the second semiconductor package 102b, the second semiconductor chip 40 uses the fourth solder balls 45 on the third substrate 30. So it is electrically connected. Other configurations may be the same as/similar to those described with reference to FIG. 19.

도 21은 본 발명의 또 다른 예에 따른 반도체 패키지의 단면도이다.21 is a cross-sectional view of a semiconductor package according to still another example of the present invention.

도 21을 참조하면, 본 예에 따른 반도체 패키지(208)에서는, 제 1 서브 반도체 패키지(101f)에서, 제 2 와이어들(26)이 제 1 기판(1)의 모든 측면들에 배치되지는 않는다. 상기 제 2 와이어들(26)은 상기 제 1 기판(1)의 1~3 측면(들)에 배치될 수 있다. 제 2 기판(20)의 일 가장자리는 상기 제 1 기판(1)의 측면 옆으로 돌출될 수 있다. 보호부재(28) 또한 상기 제 1 기판(1)의 모든 측면을 덮지는 않고 1~3 측면을 덮을 수 있다. 그 외의 구성은 도 2를 참조하여 설명한 바와 동일/유사할 수 있다.Referring to FIG. 21, in the semiconductor package 208 according to the present example, in the first sub-semiconductor package 101f, the second wires 26 are not disposed on all sides of the first substrate 1. . The second wires 26 may be disposed on the first to third side(s) of the first substrate 1. One edge of the second substrate 20 may protrude to the side of the first substrate 1. The protection member 28 may also cover 1 to 3 side surfaces without covering all side surfaces of the first substrate 1. Other configurations may be the same as/similar to those described with reference to FIG. 2.

도 22는 본 발명의 또 다른 예에 따른 반도체 패키지의 단면도이다.22 is a cross-sectional view of a semiconductor package according to another example of the present invention.

도 22를 참조하면, 본 예에 따른 반도체 패키지(209)에서는, 제 1 서브 반도체 패키지(101f)에서, 제 2 기판(20a)이 제 3 기판(30)에 제 3 접착막(25)을 이용하여 부착된다. 제 2 와이어들(26)은 제 12 기판 도전 패턴(3b), 제 21 기판 도전 패턴(22) 및 제 31 기판 도전 패턴(32)을 연속적으로 연결시킬 수 있다. 보호부재(28)는 상기 제 1 기판(1), 상기 제 2 기판(20) 및 상기 제 3 기판(30)의 단부들을 모두 덮을 수 있다. 그 외의 구성은 도 2를 참조하여 설명한 바와 동일/유사할 수 있다. Referring to FIG. 22, in the semiconductor package 209 according to the present example, in the first sub-semiconductor package 101f, the second substrate 20a uses the third adhesive film 25 on the third substrate 30. Attached. The second wires 26 may continuously connect the twelfth substrate conductive pattern 3b, the 21st substrate conductive pattern 22, and the 31st substrate conductive pattern 32. The protection member 28 may cover all ends of the first substrate 1, the second substrate 20, and the third substrate 30. Other configurations may be the same as/similar to those described with reference to FIG. 2.

이와 같이 반도체 패키지들(200~209)의 다양한 구조와 제조 방법에 대하여 설명하였다. 상기 반도체 패키지들(200~209)의 구조는 서로 조합이 가능하다. As described above, various structures and manufacturing methods of the semiconductor packages 200 to 209 have been described. The structures of the semiconductor packages 200 to 209 may be combined with each other.

상술한 반도체 패키지 기술은 다양한 종류의 반도체 소자들 및 이를 구비하는 패키지 모듈에 적용될 수 있다. The above-described semiconductor package technology can be applied to various types of semiconductor devices and package modules including the same.

도 23은 본 발명의 기술이 적용된 반도체 패키지를 포함하는 패키지 모듈의 예를 보여주는 도면이다. 도 23을 참조하면, 패키지 모듈(1200)은 반도체 집적회로 칩(1220) 및 QFP(Quad Flat Package) 패키지된 반도체 집적회로 칩(1230)과 같은 형태로 제공될 수 있다. 본 발명에 따른 반도체 패키지 기술이 적용된 반도체 소자들(1220, 1230)을 기판(1210)에 설치함으로써, 상기 패키지 모듈(1200)이 형성될 수 있다. 상기 패키지 모듈(1200)은 기판(1210) 일측에 구비된 외부연결단자(1240)를 통해 외부전자장치와 연결될 수 있다.23 is a diagram showing an example of a package module including a semiconductor package to which the technology of the present invention is applied. Referring to FIG. 23, the package module 1200 may be provided in the same form as a semiconductor integrated circuit chip 1220 and a semiconductor integrated circuit chip 1230 packaged with a QFP (Quad Flat Package). The package module 1200 may be formed by installing the semiconductor devices 1220 and 1230 to which the semiconductor package technology according to the present invention is applied on the substrate 1210. The package module 1200 may be connected to an external electronic device through an external connection terminal 1240 provided on one side of the substrate 1210.

상술한 반도체 패키지 기술은 전자 시스템에 적용될 수 있다. 도 24는 본 발명의 기술이 적용된 반도체 패키지를 포함하는 전자 장치의 예를 보여주는 블럭도이다. 도 24를 참조하면, 전자 시스템(1300)은 제어기(1310), 입출력 장치(1320) 및 기억 장치(1330)를 포함할 수 있다. 상기 제어기(1310), 입출력 장치(1320) 및 기억 장치(1330)는 버스(1350, bus)를 통하여 결합될 수 있다. 상기 버스(1350)는 데이터들이 이동하는 통로라 할 수 있다. 예컨대, 상기 제어기(1310)는 적어도 하나의 마이크로프로세서, 디지털 신호 프로세서, 마이크로컨트롤러, 그리고 이들과 동일한 기능을 수행할 수 있는 논리 소자들 중에서 적어도 어느 하나를 포함할 수 있다. 상기 제어기(1310) 및 기억 장치(1330)는 본 발명에 따른 반도체 패키지를 포함할 수 있다. 상기 입출력 장치(1320)는 키패드, 키보드 및 표시 장치(display device) 등에서 선택된 적어도 하나를 포함할 수 있다. 상기 기억 장치(330)는 데이터를 저장하는 장치이다. 상기 기억 장치(1330)는 데이터 및/또는 상기 제어기(1310)에 의해 실행되는 명령어 등을 저장할 수 있다. 상기 기억 장치(1330)는 휘발성 기억 소자 및/또는 비휘발성 기억 소자를 포함할 수 있다. 또는, 상기 기억 장치(1330)는 플래시 메모리로 형성될 수 있다. 예를 들면, 모바일 기기나 데스크 톱 컴퓨터와 같은 정보 처리 시스템에 본 발명의 기술이 적용된 플래시 메모리가 장착될 수 있다. 이러한 플래시 메모리는 반도체 디스크 장치(SSD)로 구성될 수 있다. 이 경우 전자 시스템(1300)은 대용량의 데이터를 상기 플래시 메모리 시스템에 안정적으로 저장할 수 있다. 상기 전자 시스템(1300)은 통신 네트워크로 데이터를 전송하거나 통신 네트워크로부터 데이터를 수신하기 위한 인터페이스(1340)를 더 포함할 수 있다. 상기 인터페이스(1340)는 유무선 형태일 수 있다. 예컨대, 상기 인터페이스(1340)는 안테나 또는 유무선 트랜시버 등을 포함할 수 있다. 그리고, 도시되지 않았지만, 상기 전자 시스템(1300)에는 응용 칩셋(Application Chipset), 카메라 이미지 프로세서(Camera Image Processor:CIS), 그리고 입출력 장치 등이 더 제공될 수 있음은 이 분야의 통상적인 지식을 습득한 자들에게 자명하다.The above-described semiconductor package technology can be applied to electronic systems. 24 is a block diagram showing an example of an electronic device including a semiconductor package to which the technology of the present invention is applied. Referring to FIG. 24, the electronic system 1300 may include a controller 1310, an input/output device 1320, and a memory device 1330. The controller 1310, the input/output device 1320, and the memory device 1330 may be coupled through a bus 1350 (bus). The bus 1350 may be referred to as a path through which data moves. For example, the controller 1310 may include at least one microprocessor, a digital signal processor, a microcontroller, and at least one of logic elements capable of performing the same functions as these. The controller 1310 and the memory device 1330 may include a semiconductor package according to the present invention. The input/output device 1320 may include at least one selected from a keypad, a keyboard, and a display device. The memory device 330 is a device that stores data. The memory device 1330 may store data and/or a command executed by the controller 1310. The memory device 1330 may include a volatile memory device and/or a nonvolatile memory device. Alternatively, the memory device 1330 may be formed of a flash memory. For example, a flash memory to which the technology of the present invention is applied may be mounted in an information processing system such as a mobile device or a desktop computer. Such a flash memory may be composed of a semiconductor disk device (SSD). In this case, the electronic system 1300 may stably store a large amount of data in the flash memory system. The electronic system 1300 may further include an interface 1340 for transmitting data to or receiving data from the communication network. The interface 1340 may be wired or wireless. For example, the interface 1340 may include an antenna or a wired/wireless transceiver. Further, although not shown, the electronic system 1300 may further include an application chipset, a camera image processor (CIS), and an input/output device. It is self-evident to one.

상기 전자 시스템(1300)은 모바일 시스템, 개인용 컴퓨터, 산업용 컴퓨터 또는 다양한 기능을 수행하는 로직 시스템 등으로 구현될 수 있다. 예컨대, 상기 모바일 시스템은 개인 휴대용 정보 단말기(PDA; Personal Digital Assistant), 휴대용 컴퓨터, 웹 타블렛(web tablet), 모바일폰(mobile phone), 무선폰(wireless phone), 랩톱(laptop) 컴퓨터, 메모리 카드, 디지털 뮤직 시스템(digital music system) 그리고 정보 전송/수신 시스템 중 어느 하나일 수 있다. 상기 전자 시스템(1300)이 무선 통신을 수행할 수 있는 장비인 경우에, 상기 전자 시스템(1300)은 CDMA, GSM, NADC, E-TDMA, WCDAM, CDMA2000과 같은 3세대 통신 시스템 같은 통신 인터페이스 프로토콜에서 사용될 수 있다. The electronic system 1300 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system includes a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, and a memory card. , A digital music system, and an information transmission/reception system. When the electronic system 1300 is a device capable of performing wireless communication, the electronic system 1300 is in a communication interface protocol such as a 3G communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA2000. Can be used.

상술한 본 발명의 기술이 적용된 반도체 소자는 메모리 카드의 형태로 제공될 수 있다. 도 25는 본 발명의 기술이 적용된 반도체 패키지를 포함하는 메모리 시스템의 예를 보여주는 블럭도이다. 도 25를 참조하면, 메모리 카드(1400)는 비휘발성 기억 소자(1410) 및 메모리 제어기(1420)를 포함할 수 있다. 상기 비휘발성 기억 장치(1410) 및 상기 메모리 제어기(1420)는 데이터를 저장하거나 저장된 데이터를 판독할 수 있다. 상기 비휘발성 기억 장치(1410)는 본 발명에 따른 반도체 패키지 기술이 적용된 비휘발성 기억 소자들 중에서 적어도 어느 하나를 포함할 수 있다. 상기 메모리 제어기(1420)는 호스트(host)의 판독/쓰기 요청에 응답하여 저장된 데이터를 독출하거나, 데이터를 저장하도록 상기 플래쉬 기억 장치(1410)를 제어할 수 있다.The semiconductor device to which the technology of the present invention is applied may be provided in the form of a memory card. 25 is a block diagram showing an example of a memory system including a semiconductor package to which the technology of the present invention is applied. Referring to FIG. 25, a memory card 1400 may include a nonvolatile memory device 1410 and a memory controller 1420. The nonvolatile memory device 1410 and the memory controller 1420 may store data or read stored data. The nonvolatile memory device 1410 may include at least one of nonvolatile memory devices to which the semiconductor package technology according to the present invention is applied. The memory controller 1420 may control the flash memory device 1410 to read stored data or store data in response to a read/write request from a host.

이상의 상세한 설명은 본 발명을 예시하는 것이다. 또한 전술한 내용은 본 발명의 바람직한 실시 형태를 나타내고 설명하는 것에 불과하며, 본 발명은 다양한 다른 조합, 변경 및 환경에서 사용할 수 있다. 즉, 본 명세서에 개시된 발명의 개념의 범위, 저술한 개시 내용과 균등한 범위 및/또는 당업계의 기술 또는 지식의 범위 내에서 변경 또는 수정이 가능하다. 전술한 실시예들은 본 발명을 실시하는데 있어 최선의 상태를 설명하기 위한 것이며, 본 발명과 같은 다른 발명을 이용하는데 당업계에 알려진 다른 상태로의 실시, 그리고 발명의 구체적인 적용 분야 및 용도에서 요구되는 다양한 변경도 가능하다. 따라서, 이상의 발명의 상세한 설명은 개시된 실시 상태로 본 발명을 제한하려는 의도가 아니다. 또한 첨부된 청구범위는 다른 실시 상태도 포함하는 것으로 해석되어야 한다.The detailed description above is illustrative of the present invention. In addition, the above description is only for showing and describing a preferred embodiment of the present invention, and the present invention can be used in various other combinations, modifications and environments. That is, changes or modifications may be made within the scope of the concept of the invention disclosed in the present specification, the scope equivalent to the disclosed contents, and/or the skill or knowledge of the art. The above-described embodiments are for explaining the best state in carrying out the present invention, and in order to use another invention such as the present invention, implementation in another state known in the art, and required in the specific application field and use of the invention Various changes are also possible. Accordingly, the detailed description of the invention is not intended to limit the invention to the disclosed embodiment. In addition, the appended claims should be construed as including other embodiments.

1, 20, 20a, 30: 제 1 기판
3a, 3b, 3c, 3d, 22, 24, 32, 34: 기판 도전 패턴
5, 16, 38: 솔더볼
6, 26, 26a, 26b, 46: 와이어
7: 언더필수지막
10, 40, 40a, 40b: 반도체 칩
12, 48: 몰드막
14, 25, 44: 접착막
28, 28a: 보호부재
101, 101a~101f, 102, 102a: 서브 반도체 패키지
200~209: 반도체 패키지1, 20, 20a, 30: first substrate
3a, 3b, 3c, 3d, 22, 24, 32, 34: substrate conductive pattern
5, 16, 38: solder ball
6, 26, 26a, 26b, 46: wire
7: Underfill last
10, 40, 40a, 40b: semiconductor chip
12, 48: mold film
14, 25, 44: adhesive film
28, 28a: protection member
101, 101a~101f, 102, 102a: sub semiconductor package
200~209: semiconductor package

Claims (20)

제 1 기판;
상기 제 1 기판 상에 실장된 제 1 반도체 칩;
상기 제 1 반도체 칩의 측면과 상기 제 1 기판의 상면을 덮으며 상기 제 1 반도체 칩의 상면을 노출시키는 제 1 몰드막;
상기 제 1 반도체 칩 상에 배치되는 제 2 기판;
상기 제 2 기판 상에 배치되는 적어도 하나의 제 2 반도체 칩;
상기 제 1 반도체 칩과 상기 제 2 기판 사이에 개재되며 상기 제 2 기판과 전기적으로 연결되는 제 3 기판;
상기 제 3 기판과 상기 제 1 반도체 칩 사이 그리고 상기 제 1 몰드막과 상기 제 3 기판 사이에 개재되며, 상기 제 3 기판, 상기 제 1 반도체 칩 및 상기 제 1 몰드막과 동시에 접하는 접착막; 및
상기 제 3 기판과 상기 제 1 기판을 연결시키는 와이어들을 포함하는 반도체 패키지.A first substrate;
A first semiconductor chip mounted on the first substrate;
A first mold layer covering a side surface of the first semiconductor chip and an upper surface of the first substrate and exposing an upper surface of the first semiconductor chip;
A second substrate disposed on the first semiconductor chip;
At least one second semiconductor chip disposed on the second substrate;
A third substrate interposed between the first semiconductor chip and the second substrate and electrically connected to the second substrate;
An adhesive film interposed between the third substrate and the first semiconductor chip and between the first mold film and the third substrate and in contact with the third substrate, the first semiconductor chip, and the first mold film at the same time; And
A semiconductor package including wires connecting the third substrate and the first substrate. 제 1 항에 있어서,
상기 제 1 반도체 칩과 상기 제 1 기판 사이에 개재되는 솔더볼들을 더 포함하며;
상기 제 1 몰드막은 상기 솔더볼들 사이의 공간을 채우는 반도체 패키지. The method of claim 1,
Further comprising solder balls interposed between the first semiconductor chip and the first substrate;
The first mold layer is a semiconductor package filling the space between the solder balls. 제 1 항에 있어서,
상기 제 1 반도체 칩과 상기 제 1 기판 사이에 개재되는 솔더볼들; 및
상기 솔더볼들 사이의 공간을 채우며 상기 제 1 반도체 칩의 하부 측면 및 상기 제 1 기판의 상부면과 일부 접하는 언더필수지막을 더 포함하는 반도체 패키지.The method of claim 1,
Solder balls interposed between the first semiconductor chip and the first substrate; And
A semiconductor package further comprising an underfill resin layer filling a space between the solder balls and partially in contact with a lower side surface of the first semiconductor chip and an upper surface of the first substrate. 제 1 항에 있어서,
상기 제 2 반도체 칩은 복수개로 제공되며 서로 동일한 직사각형 형태를 가지고,
상기 제 2 반도체 칩들은 각각 양 단부들에 배치되는 칩 도전 패턴들을 포함하고,
상기 제 2 반도체 칩들은 상기 제 2 기판 상에 차례로 적층되되, 서로 교차하여, 상기 칩 도전 패턴들이 노출되는 반도체 패키지. The method of claim 1,
The second semiconductor chip is provided in plural and has the same rectangular shape,
Each of the second semiconductor chips includes chip conductive patterns disposed at both ends,
The second semiconductor chips are sequentially stacked on the second substrate, and the second semiconductor chips cross each other to expose the chip conductive patterns. 삭제delete 삭제delete 제 1 항에 있어서,
상기 제 2 기판과 상기 제 3 기판 사이에 개재되어 이들을 전기적으로 연결시키는 솔더볼들을 더 포함하는 반도체 패키지. The method of claim 1,
A semiconductor package further comprising solder balls interposed between the second substrate and the third substrate to electrically connect them. 제 1 항에 있어서,
상기 와이어들을 덮는 보호 부재를 더 포함하는 반도체 패키지. The method of claim 1,
A semiconductor package further comprising a protection member covering the wires. 제 8 항에 있어서,
상기 보호부재는 상기 제 1 몰드막의 측면 및 상기 와이어들과 이격되는 홀더; 및
상기 제 1 몰드막과 상기 홀더 사이를 채우는 접착성 수지막을 포함하는 반도체 패키지.The method of claim 8,
The protection member may include a holder spaced apart from the side surfaces of the first mold film and the wires; And
A semiconductor package comprising an adhesive resin film filling between the first mold film and the holder. 제 1 항에 있어서,
상기 제 1 반도체 칩은 로직 칩이며,
상기 제 2 반도체 칩은 메모리 칩인 반도체 패키지.The method of claim 1,
The first semiconductor chip is a logic chip,
The second semiconductor chip is a memory chip. 제 1 항에 있어서,
상기 제 1 기판의 가장자리는 단차진 구조를 가지는 반도체 패키지. The method of claim 1,
A semiconductor package having a stepped structure at an edge of the first substrate. 제 11 항에 있어서,
상기 제 1 기판은 상부면에 배치되는 제 1 기판 도전 패턴과 상기 단차진 구조 안의 제 2 기판 도전 패턴을 포함하고,
상기 제 2 기판은 서로 이격된 제 3 기판 도전 패턴과 제 4 기판 도전 패턴을 포함하고,
상기 와이어들은 상기 제 1 기판 도전 패턴과 상기 제 3 기판 도전 패턴을 연결하는 제 1 와이어와 상기 단차진 구조 안의 상기 제 2 기판 도전 패턴과 상기 제 4 기판 도전 패턴을 연결하는 제 2 와이어를 포함하는 반도체 패키지. The method of claim 11,
The first substrate includes a first substrate conductive pattern disposed on an upper surface and a second substrate conductive pattern in the stepped structure,
The second substrate includes a third substrate conductive pattern and a fourth substrate conductive pattern spaced apart from each other,
The wires include a first wire connecting the first substrate conductive pattern and the third substrate conductive pattern, and a second wire connecting the second substrate conductive pattern and the fourth substrate conductive pattern in the stepped structure. Semiconductor package. 제 1 항에 있어서,
상기 와이어들은 상기 제 1 기판, 상기 제 2 기판 및 상기 제 3 기판을 연속적으로 연결하는 반도체 패키지. The method of claim 1,
The wires connect the first substrate, the second substrate, and the third substrate in succession. 제 1 항에 있어서,
상기 제 1 기판 하부에 부착되는 솔더볼들을 더 포함하는 반도체 패키지.The method of claim 1,
A semiconductor package further comprising solder balls attached to a lower portion of the first substrate. 차례로 적층된 제 1 서브 반도체 패키지와 제 2 서브 반도체 패키지;
상기 제 1 서브 반도체 패키지와 상기 제 2 서브 반도체 패키지 사이에 개재되는 인터포저 기판; 및
상기 제 1 서브 반도체 패키지와 상기 인터포저 기판을 전기적으로 연결시키는 와이어들을 포함하되,
상기 제 1 서브 반도체 패키지는:
제 1 기판과 이 위에 실장되는 제 1 반도체 칩;
상기 제 1 반도체 칩의 측면과 상기 제 1 기판의 상면을 덮으며 상기 제 1 반도체 칩의 상면을 노출시키는 제 1 몰드막; 및
상기 인터포저 기판과 상기 제 1 서브 반도체 패키지 사이에 개재되며, 상기 인터포저 기판, 상기 제 1 반도체 칩 및 상기 제 1 몰드막과 동시에 접하는 접착막을 포함하는 반도체 패키지. A first sub-semiconductor package and a second sub-semiconductor package sequentially stacked;
An interposer substrate interposed between the first sub-semiconductor package and the second sub-semiconductor package; And
Including wires electrically connecting the first sub-semiconductor package and the interposer substrate,
The first sub semiconductor package:
A first substrate and a first semiconductor chip mounted thereon;
A first mold layer covering a side surface of the first semiconductor chip and an upper surface of the first substrate and exposing an upper surface of the first semiconductor chip; And
A semiconductor package including an adhesive layer interposed between the interposer substrate and the first sub-semiconductor package and in contact with the interposer substrate, the first semiconductor chip, and the first mold layer. 제 15 항에 있어서,
상기 제 1 반도체 칩과 상기 제 1 기판 사이에 개재되는 솔더볼들을 더 포함하며;
상기 제 1 몰드막은 상기 솔더볼들 사이의 공간을 채우는 반도체 패키지.The method of claim 15,
Further comprising solder balls interposed between the first semiconductor chip and the first substrate;
The first mold layer is a semiconductor package filling the space between the solder balls. 제 15 항에 있어서,
상기 제 1 반도체 칩과 상기 제 1 기판 사이에 개재되는 솔더볼들; 및
상기 솔더볼들 사이의 공간을 채우며 상기 제 1 반도체 칩의 하부 측면 및 상기 제 1 기판의 상부면과 일부 접하는 언더필수지막을 더 포함하는 반도체 패키지. The method of claim 15,
Solder balls interposed between the first semiconductor chip and the first substrate; And
A semiconductor package further comprising an underfill resin layer filling a space between the solder balls and partially in contact with a lower side surface of the first semiconductor chip and an upper surface of the first substrate. 제 15 항에 있어서,
상기 제 2 반도체 칩은 복수개로 제공되며 서로 동일한 직사각형 형태를 가지고,
상기 제 2 반도체 칩들은 각각 양 단부들에 배치되는 칩 도전 패턴들을 포함하고,
상기 제 2 반도체 칩들은 상기 제 2 기판 상에 차례로 적층되되, 서로 교차하여, 상기 칩 도전 패턴들이 노출되는 반도체 패키지. The method of claim 15,
The second semiconductor chip is provided in plural and has the same rectangular shape,
Each of the second semiconductor chips includes chip conductive patterns disposed at both ends,
The second semiconductor chips are sequentially stacked on the second substrate, and the second semiconductor chips cross each other to expose the chip conductive patterns. 제 15 항에 있어서,
상기 제 1 몰드막의 측면 및 상기 와이어들과 이격되되 상기 와이어들을 덮는 홀더; 및
상기 제 1 몰드막과 상기 홀더 사이를 채우는 접착성 수지막을 더 포함하는 반도체 패키지.The method of claim 15,
A holder spaced apart from the side surfaces of the first mold film and the wires and covering the wires; And
A semiconductor package further comprising an adhesive resin film filling between the first mold film and the holder. 제 15 항에 있어서,
상기 제 1 기판의 가장자리는 단차진 구조를 가지고,
상기 제 2 서브 반도체 패키지는 제 2 기판을 포함하고,
상기 제 1 기판은 상부면에 배치되는 제 1 기판 도전 패턴과 상기 단차진 구조 안의 제 2 기판 도전 패턴을 포함하고,
상기 제 2 기판은 서로 이격된 제 3 기판 도전 패턴과 제 4 기판 도전 패턴을 포함하고,
상기 와이어들은 상기 제 1 기판 도전 패턴과 상기 제 3 기판 도전 패턴을 연결하는 제 1 와이어와 상기 단차진 구조 안의 상기 제 2 기판 도전 패턴과 상기 제 4 기판 도전 패턴을 연결하는 제 2 와이어를 포함하는 반도체 패키지.
The method of claim 15,
The edge of the first substrate has a stepped structure,
The second sub-semiconductor package includes a second substrate,
The first substrate includes a first substrate conductive pattern disposed on an upper surface and a second substrate conductive pattern in the stepped structure,
The second substrate includes a third substrate conductive pattern and a fourth substrate conductive pattern spaced apart from each other,
The wires include a first wire connecting the first substrate conductive pattern and the third substrate conductive pattern, and a second wire connecting the second substrate conductive pattern and the fourth substrate conductive pattern in the stepped structure. Semiconductor package.
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9666730B2 (en) 2014-08-18 2017-05-30 Optiz, Inc. Wire bond sensor package
US9875993B2 (en) * 2016-01-14 2018-01-23 Micron Technology, Inc. Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
US10438930B2 (en) * 2017-06-30 2019-10-08 Intel Corporation Package on package thermal transfer systems and methods
WO2019133019A1 (en) * 2017-12-30 2019-07-04 Intel Corporation Stacked silicon die architecture with mixed flipchip and wirebond interconnect

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100220492B1 (en) * 1996-12-06 1999-09-15 윤종용 Clip lead package
US20060073635A1 (en) * 2004-09-28 2006-04-06 Chao-Yuan Su Three dimensional package type stacking for thinner package application
US7429786B2 (en) 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7394148B2 (en) * 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
TWI296148B (en) 2006-04-28 2008-04-21 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
TWI339436B (en) 2006-05-30 2011-03-21 Advanced Semiconductor Eng Stackable semiconductor package
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
KR100961309B1 (en) 2008-02-25 2010-06-04 앰코 테크놀로지 코리아 주식회사 Semiconductor package
KR100961308B1 (en) 2008-02-25 2010-06-04 앰코 테크놀로지 코리아 주식회사 Semiconductor package
JP5378707B2 (en) * 2008-05-29 2013-12-25 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7750455B2 (en) 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
KR20100071522A (en) * 2008-12-19 2010-06-29 삼성전자주식회사 High-density and multifunctional pop-type multi chip package architecture
TW201036124A (en) 2009-03-20 2010-10-01 Advanced Semiconductor Eng Package structure and manufacturing method thereof
US8338208B2 (en) 2009-12-31 2012-12-25 Texas Instruments Incorporated Micro-electro-mechanical system having movable element integrated into leadframe-based package
JP2012033875A (en) 2010-06-30 2012-02-16 Canon Inc Stacked-type semiconductor device
US8343810B2 (en) 2010-08-16 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
JP5735339B2 (en) * 2011-04-28 2015-06-17 ルネサスエレクトロニクス株式会社 Semiconductor device
US9324659B2 (en) 2011-08-01 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
US8603859B2 (en) 2011-09-16 2013-12-10 Stats Chippac Ltd. Integrated circuit packaging system with dual side mold and method of manufacture thereof
US8698297B2 (en) 2011-09-23 2014-04-15 Stats Chippac Ltd. Integrated circuit packaging system with stack device
US9530753B2 (en) 2011-09-23 2016-12-27 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with chip stacking and method of manufacture thereof
KR101247342B1 (en) 2011-09-30 2013-03-26 에스티에스반도체통신 주식회사 Manufacturing method of package on package(pop)
US9437512B2 (en) 2011-10-07 2016-09-06 Mediatek Inc. Integrated circuit package structure

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