CN104409366A - Chip encapsulating method and encapsulating substrate - Google Patents
Chip encapsulating method and encapsulating substrate Download PDFInfo
- Publication number
- CN104409366A CN104409366A CN201410663745.6A CN201410663745A CN104409366A CN 104409366 A CN104409366 A CN 104409366A CN 201410663745 A CN201410663745 A CN 201410663745A CN 104409366 A CN104409366 A CN 104409366A
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- China
- Prior art keywords
- substrate
- chip
- divider
- chip package
- package
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- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a chip encapsulating method and an encapsulating substrate. The chip encapsulating method comprises the following steps of: preparing a base plate which is provided with a conductive structure for a chip encapsulating piece; forming dividing strips on the base plate for dividing the base plate into a plurality of areas; forming a chip encapsulating piece in each area; and dividing the base plate along the dividing strips. The chip encapsulating method and the encapsulating substrate disclosed by the invention can be used for preventing the encapsulating pieces from being warped.
Description
Technical field
The present invention relates to a kind of chip packaging method and package substrates, more particularly, relate to a kind of method for packing and the package substrates that can prevent packaging part warpage.
Background technology
Along with the development of electronic technology, have developed the various packaging part comprising one or more semiconductor chip, to realize installing, fixing, sealing, protect IC and strengthen the effect of the aspects such as electric heating property.Usually, in the manufacture process of chip package, same substrate forms several chip packages simultaneously, then make these chip packages separately by cutting, thus can once form multiple chip package, thus can realize large-scale industrial production, enhance productivity.
In the process of chip package, because the encapsulating material (such as EMC) for encapsulating is formed by different materials from the substrate, chip itself, electrical connection circuit etc. forming chip package, thermal coefficient of expansion between them is not identical each other yet, therefore in encapsulation process, easily due to the difference of thermal coefficient of expansion, packaging part is deformed.Therefore may there is the defect of packaging part warpage in the product of final chip package, cause the yield of product to reduce.
Therefore, in order to improve yield, reduce costs, the research of the technology preventing the warpage of packaging part is more and more come into one's own.
Summary of the invention
An aspect of of the present present invention relates to a kind of chip packaging method, and the method comprises: prepare substrate, and described substrate has the conductive structure for chip package; Substrate forms divider, so that substrate is divided into multiple region; Form chip package in each area; Along divider, substrate is separated.
According to a further aspect in the invention, divider can be formed by the material with elasticity or flexibility.Such as, divider can be formed by solder resist material or glue.
According to a further aspect in the invention, a chip package can be formed in each region in multiple region.
According to a further aspect in the invention, multiple chip package can be formed in each region in described multiple region, described method also can comprise: along divider by substrate separately after, along the border between described multiple chip package, described multiple chip package is separated from each other.
Another aspect of the present invention relates to a kind of package substrates, and described package substrates comprises: substrate, has the conductive structure for chip package; Divider, is arranged on a surface of substrate, substrate is divided into multiple region.
According to a further aspect in the invention, divider can be formed by the material with elasticity or flexibility.Such as, divider can be formed by solder resist material or glue.
According to a further aspect in the invention, substrate can be printed circuit board (PCB).
Utilize according to chip packaging method of the present invention and package substrates, the accumulation that the thermal expansion of encapsulating material (contraction) is out of shape can be avoided.In addition, utilize according to chip packaging method of the present invention and package substrates, the problem of packaging part warpage can be prevented.
Accompanying drawing explanation
By the description to embodiment carried out below in conjunction with accompanying drawing, above-mentioned and/or other objects of the present invention and advantage will become apparent, wherein:
Figure 1A to Fig. 1 C is the schematic cross sectional views of the manufacture process of package substrates according to an exemplary embodiment of the present invention.
Fig. 2 A to Fig. 2 C be utilize according to an exemplary embodiment of the present invention package substrates to carry out the schematic cross sectional views of the process of the method for chip package.
Fig. 3 is the plane graph of the chip packaging method schematically shown according to one exemplary embodiment of the present invention.
Fig. 4 is the plane graph of the chip packaging method schematically shown according to another exemplary embodiment of the present invention.
Embodiment
Below, embodiments of the invention are described in detail with reference to accompanying drawing.Exemplary embodiment of the present invention shown in the drawings.But only provide these embodiments with schematic and illustrative object, instead of for restriction object of the present invention.On the contrary, provide these embodiments to make the disclosure to be thoroughly with complete, and scope of the present invention will be conveyed to those skilled in the art fully.In the accompanying drawings, identical Reference numeral represents identical element all the time.
Figure 1A to Fig. 1 C is the schematic cross sectional views of the manufacture process of package substrates according to an exemplary embodiment of the present invention.With reference to Figure 1A to Fig. 1 C, the manufacture process according to the package substrates of exemplary embodiment of the present invention can comprise: prepare substrate 100, and substrate 100 has the conductive structure 110 for chip package; Form divider 125 on the substrate 100, so that substrate 100 is divided into multiple region.
According to one embodiment of present invention, substrate 100 can be printed circuit board (PCB), but the present invention is not limited thereto, and other substrate that those skilled in the art can be used to use or equivalent structure are as substrate 100.
Conductive structure 110 can be formed in substrate 100 one or two on the surface, or the inside of substrate 100 can be embedded in.Conductive structure 110 is used to form chip package.Such as, conductive structure 110 can comprise the conductive pattern for chip and substrate 100 being electrically connected to each other, the conductive pattern being used for conducting electrical signals and be used for the conductive pattern etc. that substrate 100 and external circuit is electrically connected to each other.Conductive structure can be formed by the metal with excellent conductivity of such as copper, and can by copper foil pattern being formed.
Divider 125 can be formed on the substrate 100, so that substrate 100 is divided into multiple region.Wherein, in each region in described multiple region, there is conductive structure 110 respectively, and each region is used to form at least one chip package.
Divider 125 can be formed by the material with elasticity or flexibility.Such as, divider 125 can be formed by making glue etc. conventional in SR (solder resist) material conventional in PCB process or packaging technology.But the present invention is not limited thereto, the material meeting packaging part reliability requirements all can be used for forming divider 125.
Divider 125 can be formed by mask process.Such as, as shown in Figure 1B, form material layer 120 on the substrate 100, wherein, material layer 120 can be formed by the material for the formation of divider 125.Then, material layer 120 forms mask layer 130.Wherein, mask layer 130 can utilize the techniques such as exposure, development to be formed by photoresist, also can be other mask that those skilled in the art can use.Then, utilize mask layer 130 to carry out etched material layer 120 as etching mask, thus form multiple divider 125.But the present invention is not limited thereto, divider 125 also can utilize the methods such as chemical vapour deposition (CVD) to be formed directly on substrate 100.
Fig. 2 A to Fig. 2 C be utilize according to an exemplary embodiment of the present invention package substrates to carry out the schematic cross sectional views of the process of the method for chip package.With reference to Fig. 2 A to Fig. 2 C, package substrates is according to an exemplary embodiment of the present invention utilized to comprise to the method for carrying out chip package: in each region separated by divider 125 of substrate 100, form chip package; Along divider 125 by substrate 100 separately.
As shown in Figure 2 A, first chip 140 is installed to substrate 100 by the correspondence position in the separated multiple region of divider 125, and utilize bonding line 142 etc. that chip 140 is electrically connected with the conductive structure 110 on substrate 100.Illustrated in Fig. 2 A that a chip 140 is attached to substrate 100 by bonding line 142, but the present invention is not limited thereto, multiple chip 140 can be connected to each other in chip-stacked mode, and can be connected to substrate 100 by modes such as flip-chips.
Then, as shown in Figure 2 B, utilize encapsulating material to encapsulate the chip after electrical connection, and form the electrical connector 143 that chip package is connected with outside, to form chip package at the opposite side of substrate 100.According to one embodiment of present invention, encapsulating material can be EMC, but the present invention is not limited thereto, and other encapsulating material also may be used for the present invention.
Then, with reference to Fig. 2 C, along divider 125 by substrate 100 separately, thus each chip package is separated from each other, thus forms multiple chip package.Can make substrate 100 separately by techniques such as blade cuts (Sawing SorterProcess), but the present invention is not limited thereto, other partitioning scheme that those skilled in the art can use also may be used for the present invention.
Fig. 3 is the plane graph schematically showing chip packaging method according to an embodiment of the invention.With reference to Fig. 3, substrate is divided into several regions by multiple divider 125, is formed with a chip package 150 in each region.In this case, when being cut by substrate along divider 125, the chip package 150 be formed in regional is separated from each other, thus forms multiple independent chip package.
Fig. 4 is the plane graph of the chip packaging method schematically shown according to another exemplary embodiment of the present invention.With reference to Fig. 4, substrate is divided into several regions by multiple divider 125, is formed with the packaging part bunches 155 comprising four chip packages 150 in each region.In this case, when substrate being cut along divider 125, being formed in packaging part in regional bunches 155 and being separated from each other, then, along the borderline region between each packaging part 150 by packaging part bunch 155 incisions, thus form multiple independent chip package.Illustrated in Fig. 4 that each packaging part bunches 155 comprises four chip packages 150, but the present invention is not limited thereto, each packaging part bunches 155 can comprise the chip package 150 of other quantity.
According to exemplary embodiment of the present invention, utilize divider that substrate is divided into several regions, and chip package is formed in regional.In this case, because divider makes encapsulating material (such as EMC) be divided into several regions independent of each other, therefore, avoid the accumulation that its thermal expansion (contraction) is out of shape, thus the problem of packaging part warpage can be prevented.In addition, in one embodiment, divider is formed by the material with elasticity or flexibility, in this case, thermal expansion (contraction) distortion of encapsulating material can be absorbed by the divider with elasticity or flexibility, therefore, it is possible to enough prevent the problem of packaging part warpage further.
Although describe the present invention in conjunction with exemplary embodiment of the present invention, but it will be appreciated by those skilled in the art that without departing from the spirit and scope of the present invention, various amendment in form and details and change can be carried out to these embodiments.Scope of the present invention is by claims and equivalents thereof.
Claims (10)
1. a chip packaging method, the method comprises:
Prepare substrate, described substrate has the conductive structure for chip package;
Substrate forms divider, so that substrate is divided into multiple region;
Form chip package in each area;
Along divider, substrate is separated.
2. the method for claim 1, wherein described divider is formed by the material with elasticity or flexibility.
3. method as claimed in claim 2, wherein, described divider is formed by solder resist material or glue.
4. in each region the method for claim 1, wherein in described multiple region, form a chip package.
5. form multiple chip package in each region the method for claim 1, wherein in described multiple region, described method also comprises:
Along divider by substrate separately after, along the border between described multiple chip package, described multiple chip package is separated from each other.
6. a package substrates, described package substrates comprises:
Substrate, has the conductive structure for chip package;
Divider, is arranged on a surface of substrate, substrate is divided into multiple region.
7. package substrates as claimed in claim 6, wherein, described divider is formed by the material with elasticity or flexibility.
8. package substrates as claimed in claim 7, wherein, described divider is formed by solder resist material or glue.
9. package substrates as claimed in claim 6, wherein, each region in described multiple region is for the formation of at least one chip package.
10. package substrates as claimed in claim 6, wherein, described substrate is printed circuit board (PCB).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410663745.6A CN104409366A (en) | 2014-11-19 | 2014-11-19 | Chip encapsulating method and encapsulating substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410663745.6A CN104409366A (en) | 2014-11-19 | 2014-11-19 | Chip encapsulating method and encapsulating substrate |
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| Publication Number | Publication Date |
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| CN104409366A true CN104409366A (en) | 2015-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410663745.6A Pending CN104409366A (en) | 2014-11-19 | 2014-11-19 | Chip encapsulating method and encapsulating substrate |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185756A (en) * | 2015-09-08 | 2015-12-23 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging part and method for manufacturing same |
| CN111668112A (en) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN111668116A (en) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN111696979A (en) * | 2019-03-14 | 2020-09-22 | 联发科技股份有限公司 | Semiconductor packaging structure |
| US11862578B2 (en) | 2017-03-14 | 2024-01-02 | Mediatek Inc. | Semiconductor package structure |
| US11942439B2 (en) | 2017-03-14 | 2024-03-26 | Mediatek Inc. | Semiconductor package structure |
| US11948895B2 (en) | 2017-03-14 | 2024-04-02 | Mediatek Inc. | Semiconductor package structure |
| US12002742B2 (en) | 2017-03-14 | 2024-06-04 | Mediatek Inc. | Semiconductor package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185756A (en) * | 2015-09-08 | 2015-12-23 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging part and method for manufacturing same |
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| US11862578B2 (en) | 2017-03-14 | 2024-01-02 | Mediatek Inc. | Semiconductor package structure |
| US11942439B2 (en) | 2017-03-14 | 2024-03-26 | Mediatek Inc. | Semiconductor package structure |
| US11948895B2 (en) | 2017-03-14 | 2024-04-02 | Mediatek Inc. | Semiconductor package structure |
| US12002742B2 (en) | 2017-03-14 | 2024-06-04 | Mediatek Inc. | Semiconductor package structure |
| CN111668112A (en) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN111668116A (en) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN111668116B (en) * | 2019-03-08 | 2022-08-26 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN111696979A (en) * | 2019-03-14 | 2020-09-22 | 联发科技股份有限公司 | Semiconductor packaging structure |
| CN111696979B (en) * | 2019-03-14 | 2024-04-23 | 联发科技股份有限公司 | Semiconductor packaging structure |
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Application publication date: 20150311 |