CN204243030U - A kind of electronic device - Google Patents
A kind of electronic device Download PDFInfo
- Publication number
- CN204243030U CN204243030U CN201420590059.6U CN201420590059U CN204243030U CN 204243030 U CN204243030 U CN 204243030U CN 201420590059 U CN201420590059 U CN 201420590059U CN 204243030 U CN204243030 U CN 204243030U
- Authority
- CN
- China
- Prior art keywords
- electronic device
- layer
- connecting part
- conducting connecting
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model relates to a kind of electronic device.Electronic device can comprise: integrated circuit; Conducting connecting part, is coupled to integrated circuit; Heat dissipating layer, contiguous integrated circuit and relative with conducting connecting part.Electronic device can comprise: encapsulating material, around integrated circuit and conducting connecting part; Redistributing layer, has the conductive trace being coupled to conducting connecting part; Reinforcement, between heat dissipating layer and redistributing layer; And fan-out parts, between heat dissipating layer and redistributing layer, and be positioned at encapsulating material.Electronic device of the present utility model has the radiating efficiency of improvement, the warpage of minimizing and low material C TE mismatch.Improve reliability in addition, and solve the conflict of flip chip bumps reliability and BGA joint reliability.
Description
Technical field
The disclosure relates to integrated circuit (IC)-components field, and relates more specifically to the encapsulation of integrated circuit (IC)-components.
Background technology
In the electronic device with integrated circuit (IC), IC typically installs on circuit boards.In order to the electric coupling between circuit board and IC connects, IC is typically by " encapsulation ".IC encapsulation is usually provided for the inner wrapping of physical protection IC and is provided for being coupled to the contact pad of circuit board.In some applications, encapsulate IC and can be coupled to circuit board by pedestal.
A kind of means of IC encapsulation comprise quad flat non-pin (QFN) encapsulation.QFN encapsulation can provide some advantages, the lead-in inductance such as reduced, nearly chip dimension footprint, thin side and low weight.In addition, QFN encapsulation typically comprises circumference I/O pad (perimeterI/O pad) so that board traces wiring, and copper die pad (die-pad) technology exposed provides heat and the electrical property of enhancing.QFN encapsulation just in time may be suitable for wherein size, weight and hot and that electrical property is important application.
First with reference to Fig. 1, now typical ball grid array (BGA) electronic device 200 is described.Electronic device 200 comprises heat dissipating layer 201, pair of reinforcing pieces (stiffener) 203a-203b and adhesive layer 202a, 202c between reinforcement and heat dissipating layer.Electronic device 200 comprises the multiple ball contact 207a-2071 wherein having the board layer 205 of conductive trace 208, another adhesive layer 204a-204b between board layer and reinforcement 203a-203b and carried by board layer.Electronic device 200 comprises IC206, IC is coupled to multiple ball contact 209a-209j of board layer 205, adhesive layer 202b between heat dissipating layer 201 and IC and around IC and around the underfill 210 of multiple ball contact.
Some latent defects may be there are in the electronic device 200 of prior art.Due to thermal coefficient of expansion (CTE) mismatch, electronic device 200 may have the integrity problem about ball contact 207a-2071,209a-209j.Due to external physical power and heat, electronic device 200 also may lock into warpage.In addition, the design of electronic device 200 produces the output of high cost manufacturing process and reduction.Electronic device 200 also locks into has large package dimension, simultaneously also thick along with side, wiring is poor, it is bad to dispel the heat, Noise measarement is bad and radio frequency (RF) shields not good problem.
Utility model content
The purpose of this utility model is just to provide a kind of electronic device that can overcome above-mentioned prior art defect.
Generally, electronic device can comprise: integrated circuit; Multiple conducting connecting part, is coupled to integrated circuit; And heat dissipating layer, contiguous integrated circuit and relative with multiple conducting connecting part.Electronic device can comprise: encapsulating material, around integrated circuit and multiple conducting connecting part; Redistributing layer, has the multiple conductive traces being coupled to multiple conducting connecting part; Reinforcement, between heat dissipating layer and redistributing layer; And fan-out parts, between heat dissipating layer and redistributing layer, be positioned at encapsulating material.
More specifically, electronic device may further include the hot boundary layer between heat dissipating layer and integrated circuit.Electronic device may further include the multiple conductive weld being coupled to redistributing layer.Reinforcement can have the outer surface of the inner surface of contiguous encapsulating material and the outer surface of restriction electronic device.Reinforcement can adjoin and remain potted material.
Redistributing layer can comprise dielectric layer.Multiple conductive trace is carried by dielectric layer, and is coupled to multiple conducting connecting part.Fan-out parts can comprise such as ceramic material.Multiple conducting connecting part can comprise at least one in pedestal and guide pillar (pillar).
On the other hand, a kind of electronic device is provided, it is characterized in that, comprising: integrated circuit; Multiple conducting connecting part, is coupled to described integrated circuit; Heat dissipating layer, contiguous described integrated circuit, and relative with described multiple conducting connecting part; Hot boundary layer, between described heat dissipating layer and described integrated circuit; Encapsulating material, around described integrated circuit and described multiple conducting connecting part; Redistributing layer, has the multiple conductive traces being coupled to described multiple conducting connecting part; Reinforcement, between described heat dissipating layer and described redistributing layer, and has the outer surface of the inner surface of contiguous described encapsulating material and the outer surface of the described electronic device of restriction; And fan-out parts, between described heat dissipating layer and described redistributing layer, and be positioned at described encapsulating material.
More specifically, this electronic device comprises the multiple conductive weld being coupled to described redistributing layer further.
More specifically, described reinforcement adjoins described encapsulating material.
More specifically, described redistributing layer comprises dielectric layer; And wherein, described multiple conductive trace is carried by described dielectric layer and is coupled to described multiple conducting connecting part.
More specifically, described fan-out parts comprise ceramic material.
More specifically, described multiple conducting connecting part comprises at least one in pedestal and guide pillar.
Electronic device of the present utility model has the radiating efficiency of improvement, the warpage of minimizing and low material C TE mismatch.Improve reliability in addition, and solve the conflict of flip chip bumps reliability and BGA joint reliability.
Accompanying drawing explanation
Fig. 1 is the sectional view of the electronic device according to prior art.
Fig. 2 is the sectional view according to electronic device of the present disclosure.
Fig. 3-Fig. 9 is the sectional view of each step of method for the manufacture of electronic device in Fig. 2.
Embodiment
Some latent defects may be there are in the electronic device 200 of prior art.Due to thermal coefficient of expansion (CTE) mismatch, electronic device 200 may have the integrity problem about ball contact 207a-2071,209a-209j.Due to external physical power and heat, electronic device 200 also may lock into warpage.In addition, the design of electronic device 200 produces the output of high cost manufacturing process and reduction.Electronic device 200 also locks into has large package dimension, simultaneously also thick along with side, wiring is poor, it is bad to dispel the heat, Noise measarement is bad and radio frequency (RF) shields not good problem.
Describe the disclosure more all sidedly now with reference to accompanying drawing, illustrated therein is some embodiments of the present utility model.But the form that the disclosure can be much different is implemented, and should not be construed as limited to embodiment described herein.Certainly, provide these embodiments to be to make the disclosure fully with complete, and protection range of the present disclosure can be passed on to those skilled in the art comprehensively.Label identical herein represents identical element.
With reference to Fig. 2, describe according to electronic device 10 of the present disclosure.Electronic device 10 schematically comprises IC36, and this IC has multiple conductive contact piece 20a-20e, is connected to multiple conducting connecting part 21a-21e of the conductive contact piece of IC and adjacent I C and the heat dissipating layer 11 relative with multiple conducting connecting part.Multiple conducting connecting part 21a-21e can comprise multiple pedestal or multiple guide pillar (such as, copper, aluminium).
Electronic device 10 schematically comprises: encapsulating material 14, around IC36 and multiple conducting connecting part 21a-21e; Redistributing layer 16, has the multiple conductive trace 18a-18k being coupled to multiple conducting connecting part; Reinforcement 13, between heat dissipating layer 11 and redistributing layer; And fan-out parts 15, between heat dissipating layer and redistributing layer, and be positioned at encapsulating material.Fan-out parts 15 can comprise such as pottery and/or organic material.Fan-out parts 15 are laterally positioned between reinforcement 13 and IC36.Advantageously, the problem of the prior art of the CTE mismatch of board layer 205 and ball contact 207a-2071,209a-209j is solved.
More specifically, electronic device 10 schematically comprises the hot boundary layer 12 between heat dissipating layer 11 and IC36.Electronic device 10 schematically comprises the multiple conductive weld 19a-19k carried by redistributing layer 16, connects to provide BGA type.
Reinforcement 13 has the outer surface 22 of the inner surface 23 of contiguous encapsulating material 14 and the outer surface of restriction electronic device 10.Reinforcement 13 can utilize inner surface 23 adjoin and/or remain potted material 14.
Redistributing layer 16 schematically comprises dielectric layer 17.Multiple conductive trace 18a-18k is carried by dielectric layer 17, and is coupled to multiple conducting connecting part 21a-21e.Advantageously, electronic device 10 does not have below IC36, to use substrate as the prior art means of Fig. 1.In electronic device 10, substrate is replaced by redistributing layer 16.
Additionally, and advantageously, wafer-class encapsulation technology can also be used to manufacture electronic device 10, and electronic device 10 can comprise the Integrated Electronic Component of such as capacitor.In addition, electronic device 10 lacks the silicon insert for fan-out, this silicon insert but be moved to side.Compared with the design of prior art, electronic device 10 also improves reliability, and solves the conflict of flip chip bumps reliability and BGA joint reliability.In addition, electronic device 10 has the radiating efficiency of improvement, the warpage of minimizing and low material C TE mismatch.
Relate to a kind of method manufacturing electronic device 10 on the other hand.The method can comprise: form multiple conducting connecting part 21a-21e, the plurality of conducting connecting part is coupled to IC36; Heat dissipating layer 11 is positioned to adjacent I C and relative with multiple conducting connecting part; And forming encapsulating material 14, this encapsulating material is around IC and multiple conducting connecting part.The method can comprise: location redistributing layer 16, and this redistributing layer 16 has the multiple conductive trace 18a-18k being coupled to multiple conducting connecting part 21a-21e; Reinforcement 13 is positioned between heat dissipating layer 11 and redistributing layer; And fan-out parts 15 to be positioned between heat dissipating layer and redistributing layer and to be positioned at encapsulating material 14.
Now in addition with reference to Fig. 3-Fig. 9, the exemplary embodiment of the method for the manufacture of electronic device 10 is described.Should be understood that the example illustrated creates two electronic devices 10a, 10b, only for illustrating object, and disclosed method can use wafer scale technology to manufacture more device simultaneously.
As shown in Figure 3, for the preparation of the substrate of manufacturing step, this substrate comprises carrier layer 31 and the adhesive layer in carrier layer 31 32.As shown in Figure 4, attachment (PnP, pick and place) machine is such as used IC36a-36b, fan-out parts 15a-15b and reinforcement 13a-13b to be placed on adhesive layer 32.As shown in Figure 5, above carrier layer 31, encapsulating material 14 is formed.As shown in Figure 6, the upper surface of carrier layer 31 is made to stand grinding steps to remove unnecessary encapsulating material 14.As shown in Figure 7, carrier layer 31 is reversed package parts, and forms redistributing layer 16.As shown in Figure 8, be close to redistributing layer 16 and form multiple conductive weld 19a-19k.As shown in Figure 9, illustrated cutter (saw blade) 33 (cutter stop on the way when passing through adhesive layer 32) are used to be separated the panel or wafer or package parts be molded.Next step can comprise and decompose adhesive layer 32 to discharge electronic device 10a, 10b, and is attached corresponding heat dissipating layer 11a, 11b.
Those skilled in the art described above with the instruction that presents in relevant drawings after can expect a lot of amendment of the present disclosure and other embodiments.Therefore, should be understood that the disclosure is not intended to be limited to the specific embodiment of disclosure, and be intended to various amendment and embodiment to comprise within the scope of the appended claims.
Claims (14)
1. an electronic device, is characterized in that, comprising:
Integrated circuit;
Multiple conducting connecting part, is coupled to described integrated circuit;
Heat dissipating layer, contiguous described integrated circuit, and relative with described multiple conducting connecting part;
Encapsulating material, around described integrated circuit and described multiple conducting connecting part;
Redistributing layer, has the multiple conductive traces being coupled to described multiple conducting connecting part;
Reinforcement, between described heat dissipating layer and described redistributing layer; And
Fan-out parts, between described heat dissipating layer and described redistributing layer, and are positioned at described encapsulating material.
2. electronic device according to claim 1, is characterized in that, comprises the hot boundary layer between described heat dissipating layer and described integrated circuit further.
3. electronic device according to claim 1, is characterized in that, comprises the multiple conductive weld being coupled to described redistributing layer further.
4. electronic device according to claim 1, is characterized in that, described reinforcement has the outer surface of the inner surface of contiguous described encapsulating material and the outer surface of the described electronic device of restriction.
5. electronic device according to claim 1, is characterized in that, described reinforcement adjoins described encapsulating material.
6. electronic device according to claim 1, is characterized in that, described redistributing layer comprises dielectric layer; And wherein, described multiple conductive trace is carried by described dielectric layer and is coupled to described multiple conducting connecting part.
7. electronic device according to claim 1, is characterized in that, described fan-out parts comprise ceramic material.
8. electronic device according to claim 1, is characterized in that, described multiple conducting connecting part comprises at least one in pedestal and guide pillar.
9. an electronic device, is characterized in that, comprising:
Integrated circuit;
Multiple conducting connecting part, is coupled to described integrated circuit;
Heat dissipating layer, contiguous described integrated circuit, and relative with described multiple conducting connecting part;
Hot boundary layer, between described heat dissipating layer and described integrated circuit;
Encapsulating material, around described integrated circuit and described multiple conducting connecting part;
Redistributing layer, has the multiple conductive traces being coupled to described multiple conducting connecting part;
Reinforcement, between described heat dissipating layer and described redistributing layer, and has the outer surface of the inner surface of contiguous described encapsulating material and the outer surface of the described electronic device of restriction; And
Fan-out parts, between described heat dissipating layer and described redistributing layer, and are positioned at described encapsulating material.
10. electronic device according to claim 9, is characterized in that, comprises the multiple conductive weld being coupled to described redistributing layer further.
11. electronic devices according to claim 9, is characterized in that, described reinforcement adjoins described encapsulating material.
12. electronic devices according to claim 9, is characterized in that, described redistributing layer comprises dielectric layer; And wherein, described multiple conductive trace is carried by described dielectric layer and is coupled to described multiple conducting connecting part.
13. electronic devices according to claim 9, is characterized in that, described fan-out parts comprise ceramic material.
14. electronic devices according to claim 9, is characterized in that, described multiple conducting connecting part comprises at least one in pedestal and guide pillar.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420590059.6U CN204243030U (en) | 2014-10-11 | 2014-10-11 | A kind of electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420590059.6U CN204243030U (en) | 2014-10-11 | 2014-10-11 | A kind of electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204243030U true CN204243030U (en) | 2015-04-01 |
Family
ID=52772488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420590059.6U Withdrawn - After Issue CN204243030U (en) | 2014-10-11 | 2014-10-11 | A kind of electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204243030U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105514080A (en) * | 2014-10-11 | 2016-04-20 | 意法半导体有限公司 | Electronic device with redistribution layer and reinforcement piece and related method |
-
2014
- 2014-10-11 CN CN201420590059.6U patent/CN204243030U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105514080A (en) * | 2014-10-11 | 2016-04-20 | 意法半导体有限公司 | Electronic device with redistribution layer and reinforcement piece and related method |
| CN105514080B (en) * | 2014-10-11 | 2018-12-04 | 意法半导体有限公司 | Electronic device and correlation technique with redistributing layer and reinforcer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150401 Effective date of abandoning: 20181204 |