CN103354226B - Stack packaged device - Google Patents
Stack packaged device Download PDFInfo
- Publication number
- CN103354226B CN103354226B CN201310248944.6A CN201310248944A CN103354226B CN 103354226 B CN103354226 B CN 103354226B CN 201310248944 A CN201310248944 A CN 201310248944A CN 103354226 B CN103354226 B CN 103354226B
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- CN
- China
- Prior art keywords
- substrate
- attachment spacers
- semiconductor wafer
- packaged device
- potted element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Packaging Frangible Articles (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a kind of PIP stack packaged device, it comprises: have relative first surface and the first substrate of second surface, and it comprises multiple first attachment spacers be arranged on its first surface, is arranged in multiple second attachment spacers on its second surface and is arranged in multiple 3rd attachment spacers on its first surface; Potted element on the first surface being installed on first substrate and in being electrically connected with the 3rd attachment spacers on first substrate; Be positioned over the first semiconductor wafer on interior potted element, it is in electrical contact by the first attachment spacers of bonding line and first substrate; With the first plastic-sealed body be arranged on the first surface of first substrate, its coated interior potted element, the first semiconductor wafer and bonding line.So not only can obtain less package dimension, not high to the requirement of lead key closing process yet.
Description
Technical field
The present invention relates to field of semiconductor package, particularly relate to a kind of PIP (Packageinpackage is called for short PIP) stack packaged device.
Background technology
Now, semiconductor packaging industry, in order to meet the demand of various high-density packages, develops various multi-form packaging structure gradually, and wherein various different system in package design concept is usually used in high-density packages structure.Generally speaking, system in package can be divided into stacked package (packageonpackage in multi-chip module encapsulation, encapsulation, POP) stacked package (packageinpackage, PIP) etc. and in encapsulation, wherein POP and PIP can be referred to as stacked package.The structure of POP refers to and first completes first potted element with substrate, then another complete potted element stacking on the first potted element again, second potted element is electrically connected on the substrate of the first potted element by interconnecting member (such as solder sphere), thus obtains a compound encapsulation structure.The structure of PIP refers to and first forms the potted element that has substrate, afterwards again by this potted element, other semiconductor wafers together plastic packaging in the plastic-sealed body that another is large, thus obtain the compound encapsulation structure also in an encapsulation with another encapsulation.
Fig. 1 shows existing a kind of PIP stack package structure.As shown in Figure 1, the described PIP stack package structure interior potted element 120 that comprises first substrate 110, be installed on the first semiconductor wafer 130 on first substrate 110 and be positioned on the first semiconductor wafer 130.Interior potted element 120 comprises second substrate 121, be installed on the second plastic-sealed body 123 of the second semiconductor wafer 122 on second substrate and coated second semiconductor wafer 122.By bonding line 140, the attachment spacers on second substrate 121 is electrically connected in the attachment spacers of first substrate 110.Described PIP stack package structure also comprises the first plastic-sealed body 150 of coated interior potted element 120, first semiconductor wafer 130 and bonding line 140, and wherein the second semiconductor wafer 122 can be storage chip, and the first semiconductor wafer 130 can be logic chip.
When high number of pins logic chip and high-density laminated storage chip being combined for needs, storage chip area is large, is placed on above logic chip, is then connected with first substrate by bonding line after packaged as enclosed inside element.Now, be limited to package body sizes and wire bonding (wirebonding) technological ability, this PIP structure is often difficult to realize.
Summary of the invention
For problems of the prior art, the present invention puts forward a kind of stack packaged device, and it can reduce package dimension as much as possible, and also not high to the requirement of lead key closing process.
In order to solve the problem, according to an aspect of the present invention, the present invention proposes a kind of stack packaged device, it comprises: have relative first surface and the first substrate of second surface, and it comprises multiple first attachment spacers be arranged on its first surface, is arranged in multiple second attachment spacers on its second surface and is arranged in multiple 3rd attachment spacers on its first surface; Potted element on the first surface being installed on first substrate and in being electrically connected with the 3rd attachment spacers on first substrate; Be positioned over the first semiconductor wafer on interior potted element, it is in electrical contact by the first attachment spacers of bonding line and first substrate; With the first plastic-sealed body be arranged on the first surface of first substrate, its coated interior potted element, the first semiconductor wafer and bonding line.
As one embodiment of the present of invention, first substrate also comprises the circuit line the first attachment spacers on first substrate and the 3rd attachment spacers being electrically connected to the second attachment spacers be arranged in first substrate.
As one embodiment of the present of invention, described interior potted element comprises: have relative first surface and the second substrate of second surface, and it comprises multiple first attachment spacers be arranged on its second surface and multiple second attachment spacers be arranged on its second surface; Be installed on the second semiconductor wafer on second substrate, it is electrical connected by the second attachment spacers on link and second substrate; Second plastic-sealed body, its coated described link; Multiple interconnecting member, the first attachment spacers wherein on the first link of each interconnecting member and second substrate is electrically connected, and the 3rd attachment spacers on the second link and first substrate is electrical connected.First semiconductor wafer is pasted on the first surface of second substrate by adhesive.
As one embodiment of the present of invention, described interior potted element comprises: have relative first surface and the second substrate of second surface, and it comprises multiple first attachment spacers be arranged on its second surface and multiple second attachment spacers be arranged on its first surface; Be installed on the second semiconductor wafer on second substrate, it is electrical connected by the second attachment spacers on link and second substrate; Second plastic-sealed body, its coated described link; Multiple interconnecting member, the first attachment spacers wherein on the first link of each interconnecting member and second substrate is electrically connected, and the 3rd attachment spacers on the second link and first substrate is electrical connected.First semiconductor wafer is positioned on described second semiconductor wafer, and the second semiconductor wafer is logic chip.
As one embodiment of the present of invention, described link is solder sphere, and described interconnecting member is also solder sphere.First semiconductor wafer is memory chip.First substrate and/or second substrate are printed circuit board (PCB).
As one embodiment of the present of invention, described stack packaged device also includes: the multiple external connection terminals be electrically connected with the second attachment spacers on first substrate.
Compared with prior art, in PIP stack packaged device in the present invention, interior potted element is positioned over bottom, and be electrically connected with the mode of solder sphere and first substrate, the second semiconductor wafer be stacked on interior potted element adopts lead key closing process and first substrate to be electrically connected, so not only can obtain less package dimension, not high to the requirement of lead key closing process yet.
Accompanying drawing explanation
Fig. 1 shows PIP stack package structure of the prior art structure cross-sectional schematic in one embodiment;
Fig. 2 shows stack packaged device in the present invention or structure structure cross-sectional schematic in one embodiment;
Fig. 3 shows the structure cross-sectional schematic of the interior potted element in Fig. 2;
Fig. 4 shows stack packaged device in the present invention or structure structure cross-sectional schematic in another embodiment;
Fig. 5 shows the structure cross-sectional schematic of the interior potted element in Fig. 4.
Embodiment
Below in conjunction with accompanying drawing, the present invention is elaborated.
Detailed description of the present invention carrys out the running of direct or indirect simulation technical solution of the present invention mainly through program, step, logical block, process or other symbolistic descriptions.For thorough understanding the present invention, in ensuing description, set forth a lot of specific detail.And when not having these specific detail, the present invention then may still can realize.Affiliated those of skill in the art use the work that these describe and statement effectively introduces them to the others skilled in the art in affiliated field herein essential.In other words, be object of the present invention of avoiding confusion, due to the method known and program easy understand, therefore they are not described in detail.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Wafer herein also can be called as chip or Die.
Fig. 2 shows PIP (PackageinPackage) the stack packaged device 20 structure cross-sectional schematic in one embodiment in the present invention, and Fig. 3 shows the structure cross-sectional schematic of the interior potted element in Fig. 2.Described PIP stack packaged device 20 comprises first substrate 210, the interior potted element 250 be installed on first substrate 210, the second semiconductor wafer 220 and 230 be positioned on interior potted element 250.
First substrate 210 has relative first surface (upper surface in diagram) and second surface (lower surface in diagram), they multiple 3rd attachment spacers 213 comprising multiple first attachment spacers 211 be arranged on its first surface, be arranged in multiple second attachment spacers 212 on its second surface and be arranged on its first surface.First substrate 210 also comprises the circuit line (not shown) the first attachment spacers 211 on first substrate 210 and the 3rd attachment spacers 213 being electrically connected to the second attachment spacers 212 be arranged in first substrate 210.This first substrate 210 can be printed circuit board (PCB).The second attachment spacers 212 on first substrate 210 is electrically connected with multiple external connection terminals 270, wherein said external connection terminals 270 is solder sphere, described PIP stack packaged device 20 can be electrically connected to external circuit, the mainboard of such as mobile electronic device by these external connection terminals 270.
Described interior potted element 250 also can be called as the second potted element, and its first surface being installed on first substrate 210 is electrically connected with the 3rd attachment spacers 213 on first substrate 210.In conjunction with reference to shown in figure 3, interior potted element 250 comprises second substrate 251, the second semiconductor wafer 252 be installed on second substrate 251, link 253, second plastic-sealed body 254 and multiple interconnecting member 255.
Second substrate 251 has relative first surface (upper surface in diagram) and second surface (lower surface in diagram), and it comprises multiple first attachment spacers 2511 be arranged on its second surface and multiple second attachment spacers 2512 be arranged on its second surface.This second substrate 251 can be printed circuit board (PCB).Second substrate 251 also comprises the circuit line the first attachment spacers 2511 on second substrate 251 being electrically connected to the second attachment spacers 2512 be arranged in second substrate 251.
Second semiconductor wafer 252 is electrical connected by link 253 and the second attachment spacers 2512 on second substrate 251, and this link 253 can be solder sphere.The coated described link 253 of second plastic-sealed body 254 is to protect it; in other embodiments; described second plastic-sealed body 254 also the link 253 of coated whole second semiconductor wafer 252 and bottom thereof can provide protection to provide to them; this plastic-sealed body 254 can be moulding material or organic filler material, such as epoxy molding compounds.Illustrate two the second semiconductor wafers 252 in figure, also can only have one or arrange more in other embodiments.Described second semiconductor wafer 252 can be logic chip, can certainly be other wafers.
The first attachment spacers 2511 on first link of each interconnecting member 255 and second substrate 251 is electrically connected, the 3rd attachment spacers 213 on second link and first substrate 210 is electrical connected, to realize the electrical interconnects of the second semiconductor wafer 252 and first substrate 210.Described interconnecting member 255 can be solder sphere.In this embodiment, described interconnecting member 255 is installed on phase the same side of second substrate 251 with the second semiconductor wafer 252, can reduce the integral thickness of interior potted element 250 like this.
Figure 2 illustrates two the first semiconductor wafers (Die) 220 and 230 be positioned on interior potted element, in other embodiments, also can be one or more first semiconductor wafer.Described first semiconductor wafer 220 can be installed on the first semiconductor wafer 230 by adhesive, and the first semiconductor wafer 230 can be installed on the first surface of second substrate 251 by adhesive.First semiconductor wafer 220 and 230 is electrically connected in the first attachment spacers 211 of first substrate 210 by bonding line (bondingwire) 240.Described first semiconductor wafer 220 and 230 can be memory chip, also can be the wafer of other types.
Described PIP stack packaged device 20 also includes the first plastic-sealed body 260; this first plastic-sealed body 260 is formed on the first surface of first substrate 210; and coated described first semiconductor wafer 220 and 230, bonding line 240 and interior potted element 250, to protect them.Described first plastic-sealed body 260 can be moulding material, such as epoxy molding compounds.
Fig. 4 shows the PIP stack packaged device structure cross-sectional schematic in another embodiment in the present invention; Fig. 5 shows the structure cross-sectional schematic of the interior potted element in Fig. 4.Except the structure of interior potted element 250, the PIP stack packaged device in Fig. 4 is substantially identical with the structure of the PIP stack packaged device in Fig. 2.
The structure of the interior potted element in Figure 4 and 5 is also substantially identical with the structure of the interior potted element in Fig. 2 and 3, both differences are: in figures 4 and 5, the interconnecting member 255 of interior potted element and the second semiconductor wafer 252 are arranged at the both sides of second substrate 251 respectively, instead of are the same side being arranged at second substrate 251 as in Fig. 2 and 3.As shown in Figure 5, described second substrate 251 has relative first surface (upper surface) and second surface (lower surface), it comprises multiple first attachment spacers 2511 be arranged on its second surface and multiple second attachment spacers 2512 be arranged on its first surface, second semiconductor wafer 252 is electrical connected by link 253 and the second attachment spacers 2512 on second substrate 251, and the first attachment spacers 2511 on the first link of each interconnecting member 255 and second substrate 251 is electrically connected.In this embodiment, the first semiconductor wafer 220 and 230 is positioned on described second semiconductor wafer 252.
In PIP stack packaged device in the present invention, interior potted element 250 is positioned over bottom, and be electrically connected with the mode of solder sphere and first substrate 210, can be easy to realize connecting, the second semiconductor wafer 220 and 230 be stacked on interior potted element 250 adopts lead key closing process and first substrate 210 to be electrically connected, so not only can obtain less package dimension, not high to the requirement of lead key closing process yet.And the semiconductor wafer in interior potted element 250 can be high number of pins logic chip, and the semiconductor wafer be stacked on interior potted element 250 is memory chip, high like this number of pins logic chip is in bottom, can be easy to realize connecting, memory chip is stacking on upper strata, be applicable to the interconnection of conventional wire bonding technology, technology stability and other scheme of Cost Competition force rate high.
Although describe the present invention by embodiment, those of ordinary skill in the art know, the present invention has many distortion and change and do not depart from spirit of the present invention, and the claim appended by wishing comprises these distortion and change and do not depart from spirit of the present invention.
Claims (10)
1. a stack packaged device, is characterized in that, it comprises:
Have relative first surface and the first substrate of second surface, it comprises multiple first attachment spacers be arranged on its first surface, is arranged in multiple second attachment spacers on its second surface and is arranged in multiple 3rd attachment spacers on its first surface;
Potted element on the first surface being installed on first substrate and in being electrically connected with the 3rd attachment spacers on first substrate;
Be positioned over the first semiconductor wafer on interior potted element, it is in electrical contact by the first attachment spacers of bonding line and first substrate; With
Be arranged at the first plastic-sealed body on the first surface of first substrate, its coated interior potted element, the first semiconductor wafer and bonding line.
2. stack packaged device according to claim 1, is characterized in that, first substrate also comprises the circuit line the first attachment spacers on first substrate and the 3rd attachment spacers being electrically connected to the second attachment spacers be arranged in first substrate.
3. stack packaged device according to claim 1, is characterized in that, interior potted element comprises:
Have relative first surface and the second substrate of second surface, it comprises multiple first attachment spacers be arranged on its second surface and multiple second attachment spacers be arranged on its second surface;
Be installed on the second semiconductor wafer on second substrate, it is electrical connected by the second attachment spacers on link and second substrate;
Second plastic-sealed body, its coated described link;
Multiple interconnecting member, the first attachment spacers wherein on the first link of each interconnecting member and second substrate is electrically connected, and the 3rd attachment spacers on the second link and first substrate is electrical connected.
4. stack packaged device according to claim 3, is characterized in that, the first semiconductor wafer is pasted on the first surface of second substrate by adhesive.
5. stack packaged device according to claim 1, is characterized in that, interior potted element comprises:
Have relative first surface and the second substrate of second surface, it comprises multiple first attachment spacers be arranged on its second surface and multiple second attachment spacers be arranged on its first surface;
Be installed on the second semiconductor wafer on second substrate, it is electrical connected by the second attachment spacers on link and second substrate;
Second plastic-sealed body, its coated described link;
Multiple interconnecting member, the first attachment spacers wherein on the first link of each interconnecting member and second substrate is electrically connected, and the 3rd attachment spacers on the second link and first substrate is electrical connected.
6. stack packaged device according to claim 5, is characterized in that, the first semiconductor wafer is positioned on described second semiconductor wafer, and the second semiconductor wafer is logic chip.
7. the stack packaged device according to claim 3 or 5, is characterized in that, described link is solder sphere, and described interconnecting member is also solder sphere.
8. stack packaged device according to claim 1, is characterized in that, the first semiconductor wafer is memory chip.
9. the stack packaged device according to claim 1,3 or 5, is characterized in that, first substrate and/or second substrate are printed circuit board (PCB).
10. stack packaged device according to claim 1, is characterized in that, it also includes:
The multiple external connection terminals be electrically connected with the second attachment spacers on first substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310248944.6A CN103354226B (en) | 2013-06-21 | 2013-06-21 | Stack packaged device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310248944.6A CN103354226B (en) | 2013-06-21 | 2013-06-21 | Stack packaged device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103354226A CN103354226A (en) | 2013-10-16 |
| CN103354226B true CN103354226B (en) | 2016-02-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310248944.6A Active CN103354226B (en) | 2013-06-21 | 2013-06-21 | Stack packaged device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103354226B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538435A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Multilayer packaging structure with back face of chip slotted |
| CN105845642A (en) * | 2016-05-26 | 2016-08-10 | 武汉华星光电技术有限公司 | Laminated packaging unit and mobile terminal |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100817075B1 (en) * | 2006-11-09 | 2008-03-26 | 삼성전자주식회사 | Multistack package and method of fabricating the same |
| CN101188232A (en) * | 2007-12-19 | 2008-05-28 | 日月光半导体制造股份有限公司 | Laminated encapsulation structure and its making method |
| US8841765B2 (en) * | 2011-04-22 | 2014-09-23 | Tessera, Inc. | Multi-chip module with stacked face-down connected dies |
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2013
- 2013-06-21 CN CN201310248944.6A patent/CN103354226B/en active Active
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| Publication number | Publication date |
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| CN103354226A (en) | 2013-10-16 |
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