CN103354226A - Stack packaging device - Google Patents
Stack packaging device Download PDFInfo
- Publication number
- CN103354226A CN103354226A CN2013102489446A CN201310248944A CN103354226A CN 103354226 A CN103354226 A CN 103354226A CN 2013102489446 A CN2013102489446 A CN 2013102489446A CN 201310248944 A CN201310248944 A CN 201310248944A CN 103354226 A CN103354226 A CN 103354226A
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- CN
- China
- Prior art keywords
- substrate
- semiconductor wafer
- pad
- link
- potted element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a PIP stack packaging device. The device comprises a first substrate, an inner packaging component, a first semiconductor wafer and a first plastic packaging body, wherein the first substrate possesses a first surface and a second surface which are opposite to each other; the first substrate comprises a plurality of first connection gaskets arranged on the first surface, a plurality of second connection gaskets arranged on the second surface and a plurality of third connection gaskets arranged on the first surface; the inner packaging component is installed on the first surface of the first substrate and is electrically connected with the third connection gaskets on the first substrate; the first semiconductor wafer is placed on the inner packaging component and is electrically contacted with the first connection gaskets of the first substrate through a bonding wire; the first plastic packaging body is arranged on the first surface of the first substrate and wraps the inner packaging component, the first semiconductor wafer and the bonding wire. A small packaging size can be obtained and a requirement to a lead bonding technology is not high.
Description
Technical field
The present invention relates to the semiconductor packages field, relate in particular to a kind of PIP (Package in package is called for short PIP) stack packaged device.
Background technology
Now, the semiconductor packages industry develops various multi-form packaging structures gradually in order to satisfy the demand of various high-density packages, and wherein various system in package design concept is usually used in the high-density packages structure.Generally speaking, system in package can be divided into stacked package (package on package in multi-chip module encapsulation, the encapsulation, POP) stacked package (package in package, PIP) etc. and in the encapsulation, wherein POP and PIP can be referred to as stacked package.The structure of POP refers to finish first one and has the first potted element of substrate, then stacking another complete potted element on the first potted element again, second potted element is electrically connected on the substrate of the first potted element by interconnecting member (such as solder sphere), thereby obtains a compound encapsulation structure.The structure of PIP refers to form first a potted element with substrate, afterwards again with this potted element, other semiconductor wafers together plastic packaging in another large plastic-sealed body, thereby obtain also having in the encapsulation compound encapsulation structure of another encapsulation.
Fig. 1 shows existing a kind of PIP stack package structure.As shown in Figure 1, described PIP stack package structure comprises first substrate 110, is installed on the first semiconductor wafer 130 on the first substrate 110 and is positioned over interior potted element 120 on the first semiconductor wafer 130.Interior potted element 120 comprises second substrate 121, be installed on the second semiconductor wafer 122 on the second substrate and coat the second plastic-sealed body 123 of the second semiconductor wafer 122.By bonding line 140 the connection pad on the second substrate 121 is electrically connected on the connection pad of first substrate 110.Described PIP stack package structure also comprises the first plastic-sealed body 150 that coats interior potted element 120, the first semiconductor wafer 130 and bonding line 140, and wherein the second semiconductor wafer 122 can be storage chip, and the first semiconductor wafer 130 can be logic chip.
When need to combine high number of pins logic chip and high-density laminated storage chip, the storage chip area is large, is placed on above the logic chip as inner potted element after packaged, then is connected with first substrate by bonding line.At this moment, be limited to package body sizes and Bonding (wire bonding) technological ability, this PIP structure often is difficult to realize.
Summary of the invention
For problems of the prior art, the present invention puts forward a kind of stack packaged device, and it can reduce package dimension as much as possible, and also not high to the requirement of lead key closing process.
In order to address the above problem, according to an aspect of the present invention, the present invention proposes a kind of stack packaged device, it comprises: have relative first surface and the first substrate of second surface, it comprises that being arranged in a plurality of first on its first surface connects pads, is arranged in and a plurality of the 3rd on connecting pads and being connected its first surface of a plurality of second on its second surface connects pads; Be installed on the first surface of first substrate and with first substrate on the 3rd be connected the interior potted element that pad is electrically connected; Be positioned over the first semiconductor wafer on the interior potted element, it is connected the pad electrical contact by bonding line with first of first substrate; With the first plastic-sealed body on the first surface that is arranged at first substrate, potted element, the first semiconductor wafer and bonding line in it coats.
As one embodiment of the present of invention, first substrate comprises that also the pad and the 3rd that first on the first substrate connected that is arranged in the first substrate connects the circuit line that pad is electrically connected to the second connection pad.
As one embodiment of the present of invention, described interior potted element comprises: have relative first surface and the second substrate of second surface, it comprises a plurality of the second connection pads on being arranged in a plurality of the first connection pads on its second surface and being connected its second surface; Be installed on the second semiconductor wafer on the second substrate, it is connected pad by second on link and the second substrate and is electrical connected; The second plastic-sealed body, it coats described link; A plurality of interconnecting members, wherein first on the first link of each interconnecting member and the second substrate is connected pad and is electrically connected, and the 3rd on the second link and the first substrate is connected pad and is electrical connected.The first semiconductor wafer is pasted on the first surface of second substrate by adhesive.
As one embodiment of the present of invention, described interior potted element comprises: have relative first surface and the second substrate of second surface, it comprises a plurality of the second connection pads on being arranged in a plurality of the first connection pads on its second surface and being connected its first surface; Be installed on the second semiconductor wafer on the second substrate, it is connected pad by second on link and the second substrate and is electrical connected; The second plastic-sealed body, it coats described link; A plurality of interconnecting members, wherein first on the first link of each interconnecting member and the second substrate is connected pad and is electrically connected, and the 3rd on the second link and the first substrate is connected pad and is electrical connected.The first semiconductor wafer is positioned on described the second semiconductor wafer, and the second semiconductor wafer is the logic wafer.
As one embodiment of the present of invention, described link is solder sphere, and described interconnecting member also is solder sphere.The first semiconductor wafer is memory chip.First substrate and/or second substrate are printed circuit board (PCB).
As one embodiment of the present of invention, described stack packaged device also includes: be connected a plurality of external connection terminals that pad is electrically connected with second on the first substrate.
Compared with prior art, in the PIP stack packaged device among the present invention, interior potted element is positioned over the bottom, and be electrically connected with mode and the first substrate of solder sphere, the second semiconductor wafer that is stacked on the interior potted element adopts lead key closing process and first substrate to be electrically connected, so not only can obtain less package dimension, not high to the requirement of lead key closing process yet.
Description of drawings
Fig. 1 shows PIP stack package structure of the prior art structure cross-sectional schematic in one embodiment;
Fig. 2 shows stack packaged device or the structure structure cross-sectional schematic in one embodiment among the present invention;
Fig. 3 shows the structure cross-sectional schematic of the interior potted element among Fig. 2;
Fig. 4 shows stack packaged device or the structure structure cross-sectional schematic in another embodiment among the present invention;
Fig. 5 shows the structure cross-sectional schematic of the interior potted element among Fig. 4.
Embodiment
Below in conjunction with accompanying drawing the present invention is elaborated.
Detailed description of the present invention is mainly come the running of direct or indirect simulation technical solution of the present invention by program, step, logical block, process or other symbolistic descriptions.Be the thorough the present invention that understands, in ensuing description, stated a lot of specific detail.And when not having these specific detail, the present invention then may still can realize.Affiliated those of skill in the art use herein these descriptions and statement essential to the work that the others skilled in the art in the affiliated field effectively introduce them.In other words, be the purpose of the present invention of avoiding confusion, because the easily understanding of the method for knowing and program, so they are not described in detail.
Alleged " embodiment " or " embodiment " refer to be contained in special characteristic, structure or the characteristic at least one implementation of the present invention herein.Different local in this manual " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or the embodiment mutually exclusive with other embodiment optionally.Wafer herein also can be called as chip or Die.
Fig. 2 shows PIP (Package in Package) the stack packaged device 20 structure cross-sectional schematic in one embodiment among the present invention, and Fig. 3 shows the structure cross-sectional schematic of the interior potted element among Fig. 2.Described PIP stack packaged device 20 comprises first substrate 210, be installed on interior potted element 250 on the first substrate 210, be positioned over the second semiconductor wafer 220 and 230 on the interior potted element 250.
Described interior potted element 250 also can be called as the second potted element, its be installed on the first surface of first substrate 210 and with first substrate 210 on the 3rd be connected pad 213 and be electrically connected.Shown in Figure 3 in conjunction with reference, interior potted element 250 comprises second substrate 251, is installed on the second semiconductor wafer 252, link 253, the second plastic-sealed body 254 and a plurality of interconnecting member 255 on the second substrate 251.
The second semiconductor wafer 252 is connected pad 2512 by second on link 253 and the second substrate 251 and is electrical connected, and this link 253 can be solder sphere.The second plastic-sealed body 254 coats described link 253 so that it is protected; in other embodiments; the link 253 that described the second plastic-sealed body 254 also can coat whole the second semiconductor wafer 252 and bottom thereof provides protection to provide to them; this plastic-sealed body 254 can be moulding material or organic filler material, such as the epoxy mold compound.Illustrate two the second semiconductor wafers 252 among the figure, also can only have in other embodiments one or arrange more.Described the second semiconductor wafer 252 can be the logic wafer, can certainly be other wafers.
On the first link of each interconnecting member 255 and the second substrate 251 first is connected pad 2511 and is electrically connected, on the second link and the first substrate 210 the 3rd is connected pad 213 and is electrical connected, to realize the electrical interconnects of the second semiconductor wafer 252 and first substrate 210.Described interconnecting member 255 can be solder sphere.In this embodiment, described interconnecting member 255 and the second semiconductor wafer 252 are installed on phase the same side of second substrate 251, can reduce like this integral thickness of interior potted element 250.
Figure 2 illustrates two the first semiconductor wafers (Die) 220 and 230 that are positioned on the interior potted element, in other embodiments, also can be one or more first semiconductor wafer.Described the first semiconductor wafer 220 can be installed on the first semiconductor wafer 230 by adhesive, and the first semiconductor wafer 230 can be installed on the first surface of second substrate 251 by adhesive.The first semiconductor wafer 220 is electrically connected on the first connection pad 211 of first substrate 210 by bonding line (bonding wire) 240 with being connected.Described the first semiconductor wafer 220 and 230 can be memory chip, also can be the wafer of other types.
Described PIP stack packaged device 20 also includes the first plastic-sealed body 260; this first plastic-sealed body 260 is formed on the first surface of first substrate 210; and coat described the first semiconductor wafer 220 and 230, bonding line 240 and interior potted element 250, so that they are protected.Described the first plastic-sealed body 260 can be moulding material, such as the epoxy mold compound.
Fig. 4 shows the PIP stack packaged device structure cross-sectional schematic in another embodiment among the present invention; Fig. 5 shows the structure cross-sectional schematic of the interior potted element among Fig. 4.Except the structure of interior potted element 250, the PIP stack packaged device among Fig. 4 and the structure of the PIP stack packaged device among Fig. 2 are basic identical.
The structure of the interior potted element among the structure of the interior potted element in the Figure 4 and 5 and Fig. 2 and 3 is also basic identical, both differences are: in Figure 4 and 5, the interconnecting member 255 of interior potted element and the second semiconductor wafer 252 are arranged at respectively the both sides of second substrate 251, rather than are the same side that is arranged at second substrate 251 as in Fig. 2 and 3.As shown in Figure 5, described second substrate 251 has relative first surface (upper surface) and second surface (lower surface), it comprises a plurality of the second connection pads 2512 on being arranged in a plurality of the first connection pads 2511 on its second surface and being connected its first surface, the second semiconductor wafer 252 is connected pad 2512 by second on link 253 and the second substrate 251 and is electrical connected, and first on the first link of each interconnecting member 255 and the second substrate 251 is connected pad 2511 and is electrically connected.In this embodiment, the first semiconductor wafer 220 and 230 is positioned on described the second semiconductor wafer 252.
In the PIP stack packaged device in the present invention, interior potted element 250 is positioned over the bottom, and be electrically connected with mode and the first substrate 210 of solder sphere, can be easy to realize connecting, the second semiconductor wafer 220 and 230 that is stacked on the interior potted element 250 adopts lead key closing process and first substrate 210 to be electrically connected, so not only can obtain less package dimension, not high to the requirement of lead key closing process yet.And the semiconductor wafer in the interior potted element 250 can be high number of pins logic wafer, and the semiconductor wafer that is stacked on the interior potted element 250 is memory chip, high like this number of pins logic wafer is in the bottom, can be easy to realize connecting, memory chip is stacking on the upper strata, be fit to the interconnection of conventional wire bonding technology, other scheme of technology stability and Cost Competition force rate is high.
Although described the present invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wish that appended claim comprises these distortion and variation and do not break away from spirit of the present invention.
Claims (10)
1. stack packaged device is characterized in that it comprises:
Have relative first surface and the first substrate of second surface, it comprises that being arranged in a plurality of first on its first surface connects pads, is arranged in and a plurality of the 3rd on connecting pads and being connected its first surface of a plurality of second on its second surface connects pads;
Be installed on the first surface of first substrate and with first substrate on the 3rd be connected the interior potted element that pad is electrically connected;
Be positioned over the first semiconductor wafer on the interior potted element, it is connected the pad electrical contact by bonding line with first of first substrate; With
Be arranged at the first plastic-sealed body on the first surface of first substrate, potted element, the first semiconductor wafer and bonding line in it coats.
2. stack packaged device according to claim 1 is characterized in that, first substrate comprises that also the pad and the 3rd that first on the first substrate connected that is arranged in the first substrate connects the circuit line that pad is electrically connected to the second connection pad.
3. stack packaged device according to claim 1 is characterized in that, interior potted element comprises:
Have relative first surface and the second substrate of second surface, it comprises a plurality of the second connection pads on being arranged in a plurality of the first connection pads on its second surface and being connected its second surface;
Be installed on the second semiconductor wafer on the second substrate, it is connected pad by second on link and the second substrate and is electrical connected;
The second plastic-sealed body, it coats described link;
A plurality of interconnecting members, wherein first on the first link of each interconnecting member and the second substrate is connected pad and is electrically connected, and the 3rd on the second link and the first substrate is connected pad and is electrical connected.
4. stack packaged device according to claim 3 is characterized in that, the first semiconductor wafer is pasted on the first surface of second substrate by adhesive.
5. stack packaged device according to claim 1 is characterized in that, interior potted element comprises:
Have relative first surface and the second substrate of second surface, it comprises a plurality of the second connection pads on being arranged in a plurality of the first connection pads on its second surface and being connected its first surface;
Be installed on the second semiconductor wafer on the second substrate, it is connected pad by second on link and the second substrate and is electrical connected;
The second plastic-sealed body, it coats described link;
A plurality of interconnecting members, wherein first on the first link of each interconnecting member and the second substrate is connected pad and is electrically connected, and the 3rd on the second link and the first substrate is connected pad and is electrical connected.
6. stack packaged device according to claim 5 is characterized in that, the first semiconductor wafer is positioned on described the second semiconductor wafer, and the second semiconductor wafer is the logic wafer.
7. according to claim 3 or 5 described stack packaged devices, it is characterized in that described link is solder sphere, described interconnecting member also is solder sphere.
8. stack packaged device according to claim 1 is characterized in that, the first semiconductor wafer is memory chip.
9. according to claim 1,3 or 5 described stack packaged devices, it is characterized in that first substrate and/or second substrate are printed circuit board (PCB).
10. stack packaged device according to claim 1 is characterized in that, it also includes:
Be connected a plurality of external connection terminals that pad is electrically connected with second on the first substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310248944.6A CN103354226B (en) | 2013-06-21 | 2013-06-21 | Stack packaged device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310248944.6A CN103354226B (en) | 2013-06-21 | 2013-06-21 | Stack packaged device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103354226A true CN103354226A (en) | 2013-10-16 |
| CN103354226B CN103354226B (en) | 2016-02-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310248944.6A Active CN103354226B (en) | 2013-06-21 | 2013-06-21 | Stack packaged device |
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| Country | Link |
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| CN (1) | CN103354226B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538435A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Multilayer packaging structure with back face of chip slotted |
| CN105845642A (en) * | 2016-05-26 | 2016-08-10 | 武汉华星光电技术有限公司 | Laminated packaging unit and mobile terminal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179068A (en) * | 2006-11-09 | 2008-05-14 | 三星电子株式会社 | Multi stack package and method of fabricating the same |
| CN101188232A (en) * | 2007-12-19 | 2008-05-28 | 日月光半导体制造股份有限公司 | Laminated encapsulation structure and its making method |
| WO2012145370A1 (en) * | 2011-04-22 | 2012-10-26 | Tessera, Inc. | Multi-chip module with stacked face-down connected dies |
-
2013
- 2013-06-21 CN CN201310248944.6A patent/CN103354226B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101179068A (en) * | 2006-11-09 | 2008-05-14 | 三星电子株式会社 | Multi stack package and method of fabricating the same |
| CN101188232A (en) * | 2007-12-19 | 2008-05-28 | 日月光半导体制造股份有限公司 | Laminated encapsulation structure and its making method |
| WO2012145370A1 (en) * | 2011-04-22 | 2012-10-26 | Tessera, Inc. | Multi-chip module with stacked face-down connected dies |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538435A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Multilayer packaging structure with back face of chip slotted |
| CN105845642A (en) * | 2016-05-26 | 2016-08-10 | 武汉华星光电技术有限公司 | Laminated packaging unit and mobile terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103354226B (en) | 2016-02-24 |
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