CN103400810A - Semiconductor chip laminating and packaging structure and manufacturing method thereof - Google Patents
Semiconductor chip laminating and packaging structure and manufacturing method thereof Download PDFInfo
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- CN103400810A CN103400810A CN2013102693077A CN201310269307A CN103400810A CN 103400810 A CN103400810 A CN 103400810A CN 2013102693077 A CN2013102693077 A CN 2013102693077A CN 201310269307 A CN201310269307 A CN 201310269307A CN 103400810 A CN103400810 A CN 103400810A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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Abstract
The invention provides a semiconductor chip laminating and packaging structure and a manufacturing method thereof. The laminating and packaging structure comprises a plurality of packaging units. Each packaging unit comprises a thermally conductive and insulating substrate, a semiconductor chip, a plastic package layer, a through hole and a terminal, wherein the semiconductor chip is attached to the surface of the thermally conductive and insulating substrate; the plastic package layer is covered on a first surface of the thermally conductive and insulating substrate and a first surface of the semiconductor chip, and the surface of the plastic package layer is provided with a conductive pattern which is electrically connected to the semiconductor chip; the through hole penetrates through the thermally conductive and insulating substrate and the plastic package layer and is filled with a conductive material which is electrically connected to the conductive pattern; and the terminal is formed at one end of the through hole and electrically connected with the conductive material filled in the through hole. The packaging unit is combined and electrically connected with an another adjacent packaging unit through the terminal of the packaging unit, and the terminal of the packaging unit is combined and electrically connected with the other end, which is not provided with the terminal, of the through hole of the another adjacent packaging unit.
Description
Technical field
The present invention relates to the semiconductor die package field, specifically, relate to a kind of a kind of laminate packaging structure and method of making the laminate packaging structure of this semiconductor chip of semiconductor chip.
Background technology
, along with the size of electronic installation becomes more and more less, by stacking a plurality of chips or Stacked semiconductor package unit in a semiconductor package, realize high integration density.
Fig. 1 is the schematic cross sectional views of encapsulating structure of the semiconductor chip of prior art.
With reference to Fig. 1, the encapsulating structure 100 of the semiconductor chip of prior art comprises two stacked encapsulation units, that is, be positioned at the encapsulation unit (being called hereinafter " lower encapsulation unit ") of encapsulating structure 100 bottoms and be positioned at the encapsulation unit (be called hereinafter " upper encapsulation unit ") on encapsulating structure 100 tops.Lower encapsulation unit comprises lower printed circuit board (PCB) 110, is positioned at the lower semiconductor chip 130 that is electrically connected on lower printed circuit board (PCB) 110 and with it and is positioned at below lower printed circuit board (PCB) 110 and the soldered ball 160 that is electrically connected to it.Upper encapsulation unit comprises printed circuit board (PCB) 120, be positioned on printed circuit board (PCB) 120 and the semiconductor-on-insulator chip 140 that is electrically connected to it, be positioned at below upper printed circuit board (PCB) 120 and the soldered ball 170 that is electrically connected to it and the plastic packaging layer 150 that covers semiconductor-on-insulator chip 140 and upper printed circuit board (PCB) 120, wherein, semiconductor-on-insulator chip 140 and upper printed circuit board (PCB) 120 are electrically connected to by lead-in wire 180.Upper encapsulation unit and lower encapsulation unit are electrically connected to by soldered ball 170, that is, as shown in fig. 1, soldered ball 170 is between the lower printed circuit board (PCB) 110 of the upper printed circuit board (PCB) 120 of upper encapsulation unit and lower encapsulation unit and they are electrically connected to.
In the encapsulating structure 100 with said structure, because semiconductor chip is arranged on printed circuit board (PCB), so the heat that is produced by semiconductor chip is difficult to leave and accumulation and have a strong impact on the operation of semiconductor chip in encapsulating structure, and semiconductor chip is damaged.Especially, in upper encapsulation unit, due to semiconductor-on-insulator chip 140, be arranged in the space that is formed by plastic packaging layer 150 and printed circuit board (PCB) 120, so heat is more difficult, leave.
In addition,, because semiconductor-on-insulator chip 140 is electrically connected to upper printed circuit board (PCB) 120 by lead-in wire 180, make the height of plastic packaging layer 150 increase, so have larger packaging height in above-mentioned encapsulating structure 100.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, and a kind of a kind of stepped construction and method of making the stepped construction of this semiconductor chip with semiconductor chip that good thermal diffusivity simultaneous altitude obtains reducing is provided.
A kind of stepped construction of semiconductor chip is provided according to an aspect of the present invention.The stepped construction of this semiconductor chip comprises a plurality of encapsulation units, and each encapsulation unit comprises: the heat conductive insulating substrate comprises first surface and back to the second surface of first surface; Semiconductor chip, be attached on the first surface of heat conductive insulating substrate, and comprise that wherein, semiconductor chip is included in the I/O end on first surface in the face of the second surface of heat conductive insulating substrate with back to the first surface of heat conductive insulating substrate; The plastic packaging layer, cover the first surface of heat conductive insulating substrate and the first surface of semiconductor chip, and the surface of plastic packaging layer is formed with the conductive pattern that is electrically connected to semiconductor chip; Through hole, connect heat conductive insulating substrate and plastic packaging layer, is filled with the electric conducting material that is electrically connected to conductive pattern in through hole; Terminal, be formed on an end of through hole and with the electric conducting material in being filled in through hole, be electrically connected to, wherein, encapsulation unit combines and is electrically connected to adjacent another encapsulation unit terminal by a described encapsulation unit, the terminal of a described encapsulation unit in conjunction with and be electrically connected to the other end that does not form terminal of the through hole of adjacent described another encapsulation unit.
According to embodiments of the invention, can be formed with the conductive projection of the I/O end that is electrically connected to semiconductor chip on the first surface of semiconductor chip, conductive pattern is electrically connected to conductive projection.
According to embodiments of the invention, the part of conductive projection can be exposed to the outside of plastic packaging layer.
According to embodiments of the invention, described laminate packaging structure can also comprise the described part of the outside that is exposed to the plastic packaging layer that covers conductive projection and the insulation material layer of conductive pattern.
According to embodiments of the invention, conductive pattern can be formed by the electric conducting material that is filled in the lip-deep groove that is formed at the plastic packaging layer.
According to embodiments of the invention, terminal can be formed on the end that is positioned at the conduction insulated substrate of through hole or be formed on the end that is positioned at the plastic packaging layer of through hole.
According to embodiments of the invention, terminal can be soldered ball or conductive projection.
According to embodiments of the invention, adjacent encapsulation unit can be separated and mechanically combination by terminal.
According to embodiments of the invention, the heat conductive insulating substrate can be ceramic substrate.
According to a further aspect in the invention, provide a kind of method of making the laminate packaging structure of semiconductor chip.Described method comprises the step of the step that forms encapsulation unit and the stacked a plurality of encapsulation units that obtain by the step that forms encapsulation unit.The step that forms encapsulation unit comprises: the heat conductive insulating substrate is provided, and the heat conductive insulating substrate comprises first surface and back to the second surface of first surface; Semiconductor chip is attached on the first surface of heat conductive insulating substrate, semiconductor chip comprises in the face of the second surface of heat conductive insulating substrate with back to the first surface of heat conductive insulating substrate; Cover the first surface of heat conductive insulating substrate and the first surface of semiconductor chip with capsulation material, to form the plastic packaging layer; Surface at the plastic packaging layer forms the conductive pattern that is electrically connected to semiconductor chip, forms the through hole that connects heat conductive insulating substrate and plastic packaging layer and fill the electric conducting material that is electrically connected to conductive pattern in through hole; An end of through hole form be filled in through hole in the terminal that is electrically connected to of electric conducting material, thereby the formation encapsulation unit.The step of stacked a plurality of encapsulation units comprises: with the terminal of an encapsulation unit in conjunction with and be electrically connected to the other end that does not form terminal of the through hole of another encapsulation unit.
According to embodiments of the invention, can be formed with conductive projection on the first surface of semiconductor chip, in the step that forms conductive pattern, conductive pattern can be formed and is electrically connected to conductive projection.
According to embodiments of the invention, before forming the step of conductive pattern, the part on surface that can be by removing the plastic packaging layer makes the part of conductive projection be exposed to the outside of plastic packaging layer.
According to embodiments of the invention, the step that forms encapsulation unit can also comprise: form the described part of the outside that is exposed to the plastic packaging layer that covers conductive projection and the insulation material layer of conductive pattern.
According to embodiments of the invention, can by form groove on the surface that is etched in the plastic packaging layer and in groove the filled conductive material form conductive pattern.
According to embodiments of the invention, terminal can be formed on the end that is positioned at the conduction insulated substrate of through hole or be formed on the end that is positioned at the plastic packaging layer of through hole.
According to embodiments of the invention, terminal can be soldered ball or conductive projection.
According to embodiments of the invention, adjacent encapsulation unit can be separated and mechanically combination by terminal.
According to embodiments of the invention, the heat conductive insulating substrate can be ceramic substrate.
Description of drawings
The following description of the exemplary embodiment of carrying out in conjunction with the drawings, these and/or other aspect of the present invention and advantage will become clear and be easier to and understand, wherein:
Fig. 1 is the schematic cross sectional views of encapsulating structure of the semiconductor chip of prior art;
Fig. 2 is the schematic cross sectional views of the laminate packaging structure of semiconductor chip according to an exemplary embodiment of the present invention;
Fig. 3 a to Fig. 3 i is the schematic cross sectional views of making according to an exemplary embodiment of the present invention the laminate packaging structure of semiconductor chip;
Fig. 4 is the vertical view of Fig. 3 h.
Embodiment
Hereinafter, exemplary embodiment of the present invention is described with reference to the accompanying drawings more fully; Yet exemplary embodiment can be implemented with different forms, and should not be construed as limited to the embodiment that sets forth here.On the contrary, provide these embodiment, making the disclosure will be thoroughly with complete, and scope of the present invention is conveyed to those skilled in the art fully.
Fig. 2 is the schematic cross sectional views of the laminate packaging structure of semiconductor chip according to an exemplary embodiment of the present invention.
, with reference to Fig. 2, according to the laminate packaging structure 200 of the semiconductor chip of exemplary embodiment, comprise the first encapsulation unit 210 and the second encapsulation unit 220.Below will be described in detail the first encapsulation unit 210 and the second encapsulation unit 220 respectively.
The first encapsulation unit 210 comprises: the first heat conductive insulating substrate 211; The first semiconductor chip 212, be attached on the surface of the first heat conductive insulating substrate 211, at the first semiconductor chip 212, comprises the I/O end on the surface of the first heat conductive insulating substrate 211; The first plastic packaging layer 213, cover the first heat conductive insulating substrate 211 and the first semiconductor chip 212, the first conductive pattern 215 that is electrically connected to the first semiconductor chip 212 is located to be formed with in the surface of the first plastic packaging layer 213 surface of the first heat conductive insulating substrate 211 (for example, back to); The first through hole 214, connect the first heat conductive insulating substrate 211 and the first plastic packaging layer 213, and be filled with the electric conducting material that is electrically connected to the first conductive pattern 215 in it; The first terminal 217, be formed on an end of the first through hole 214 and with the electric conducting material in being filled in the first through hole 214, be electrically connected to.
The first heat conductive insulating substrate 211 can be ceramic substrate, yet, the invention is not restricted to this.For example, the substrate of any heat conductive insulating can be used as the first heat conductive insulating substrate 211.
The first semiconductor chip 212 can for example adhere on the surface of the first heat conductive insulating substrate 211 by any suitable means.In addition, the surface back to the first heat conductive insulating substrate 211 of the first semiconductor chip 212 can be provided with the first conductive projection 218 that is electrically connected to the I/O end, in this case, the first conductive pattern 215 is electrically connected to the first conductive projection 218 to be electrically connected to the first semiconductor chip 212.
The part of the first conductive projection 218 can be exposed to the outside of the first plastic packaging layer 213, for example, in manufacture process, (for example can pass through the surface of removal the first plastic packaging layer 213, surface back to the first heat conductive insulating substrate 211) expose the part of the first conductive projection 218, make the surface of the surface of exposure of the first conductive projection 218 and the first plastic packaging layer 213 at grade.In this case, can with insulating material cover the first conductive projection 218 being exposed the part and the first conductive pattern 215 to form the first insulation material layer 216.
The first conductive pattern 215 can be formed by the electric conducting material that is filled in the lip-deep groove that is formed at the first plastic packaging layer 213.In this case, the electric conducting material of filling groove formation the first conductive pattern 215 can be identical with the electric conducting material in filling the first through hole 214, and for example, electric conducting material can be the high molecular polymer that contains conductive particle (Cu particle, Ag particle).Yet, the invention is not restricted to this, for example, can deposit the first conductive pattern 215 on the surface of the first plastic packaging layer 213.
The first terminal 217 can be soldered ball or conductive projection.In addition, as shown in Figure 2, the first terminal 217 is formed on the end that is positioned at the first plastic packaging layer 213 of the first through hole 214, yet, the invention is not restricted to, for example, the first terminal 217 can be formed on the end that is positioned at the first heat conductive insulating substrate 211 of the first through hole 214.
The structural similarity of the structure of the second encapsulation unit 220 and the first encapsulation unit 210.Specifically, the second encapsulation unit 220 comprises: the second heat conductive insulating substrate 221; The second semiconductor chip 222, be attached on the surface of the second heat conductive insulating substrate 221, at the second semiconductor chip 222, comprises the I/O end on the surface of the second heat conductive insulating substrate 221; The second plastic packaging layer 223, be formed with the second conductive pattern 225 that is electrically connected to the second semiconductor chip 222 on the surface of covering the second heat conductive insulating substrate 221 and the second semiconductor chip 222, the second plastic packaging layers 223; The second through hole 224, connect the second heat conductive insulating substrate 221 and the second plastic packaging layer 223, and be filled with the electric conducting material (not shown) that is electrically connected to the second conductive pattern 225 in it; The second terminal 227, be formed on an end of the second through hole 224.
The second heat conductive insulating substrate 221 can be ceramic substrate, yet, the invention is not restricted to this.For example, the substrate of any heat conductive insulating can be used as the second heat conductive insulating substrate 221.
The second semiconductor chip 222 can for example adhere on the surface of the second heat conductive insulating substrate 221 by any suitable means.In addition, the surface back to the second heat conductive insulating substrate 221 of the second semiconductor chip 222 can be provided with the second conductive projection 228 that is electrically connected to the I/O end, in this case, the second conductive pattern 225 is electrically connected to the second conductive projection 228 to be electrically connected to the second conductive chip 222.
The part of the second conductive projection 228 can be exposed to the outside of the second plastic packaging layer 223, for example, in manufacture process, can expose by the surface of grinding the second plastic packaging layer 223 the second conductive projection 228, make the surface of the surface of exposure of the second conductive projection 228 and the second plastic packaging layer 223 at grade.In this case, can with insulating material cover the second conductive projection 228 being exposed the part and the second conductive pattern 225 to form the second insulation material layer 226.
The second conductive pattern 225 can be formed by the electric conducting material that is filled in the lip-deep groove that is formed at the second plastic packaging layer 223.In this case, the electric conducting material of filling groove formation the second conductive pattern 225 can be identical with the electric conducting material in filling the second through hole 224, and for example, electric conducting material can be the high molecular polymer that contains conductive particle (Cu particle, Ag particle).Yet, the invention is not restricted to this, for example, can deposit the second conductive pattern 225 on the surface of the second plastic packaging layer 223.
The second terminal 227 can be soldered ball or conductive projection.In addition, as shown in Figure 2, the second terminal 227 is formed on the end that is positioned at the second plastic packaging layer 223 of the second through hole 224, yet, the invention is not restricted to, for example, the second terminal 227 can be formed on the end that is positioned at the second heat conductive insulating substrate 221 of the second through hole 224.
In the laminate packaging structure 200 of semiconductor chip, the first encapsulation unit 210 and the second encapsulation unit 220 are electrically connected to by the first terminal 217.Specifically, the first terminal 217 is arranged between the first encapsulation unit 210 and the second encapsulation unit 220, and the first terminal 217 is electrically connected to an end that does not form the second terminal 227 of the second through hole 224 so that the first encapsulation unit 210 and the second encapsulation unit 220 are electrically connected to.In addition, the first terminal 210 is separated the first encapsulation unit 210 and the second encapsulation unit 220 certain distance and they is mechanically combined.
Although the laminate packaging structure 200 of the semiconductor chip shown in Fig. 2 is formed by two encapsulation units 210 and 220, the invention is not restricted to.Can be formed by the three or more encapsulation units with said structure according to the laminate packaging structure of semiconductor chip of the present invention.
In the laminate packaging structure of above-mentioned semiconductor chip, because semiconductor chip is arranged on the heat conductive insulating substrate, so the heat that can effectively leave and be produced by semiconductor chip.
In addition, in the laminate packaging structure of above-mentioned semiconductor chip, owing to need not to use lead-in wire that semiconductor chip is connected to printed circuit board (PCB), thus can effectively reduce the height of encapsulation unit, and then reduce the height of the laminate packaging structure of semiconductor chip.
Fig. 3 a to Fig. 3 i is the schematic cross sectional views of making according to an exemplary embodiment of the present invention the laminate packaging structure of semiconductor chip, and Fig. 4 is the vertical view of Fig. 3 h.
Below with reference to Fig. 3 a to Fig. 3 i and Fig. 4, describe method according to the laminate packaging structure of the manufacturing semiconductor chip of exemplary embodiment of the present invention in detail.
At first will the method for manufacturing and encapsulation unit be described as example take the first encapsulation unit 210.
, with reference to 3a, provide the first heat conductive insulating substrate 211.As mentioned above, can, with any substrate with heat conductive insulating performance as the first heat conductive insulating substrate 211, preferably, ceramic substrate be used as the first heat conductive insulating substrate 211.
, with reference to Fig. 3 b, the first semiconductor chip 212 is adhered to (for example, adhering to) to the surface of the first heat conductive insulating substrate 211.The surface back to the first heat conductive insulating substrate 211 of the first semiconductor chip 212 can be provided with the first conductive projection 218 of the I/O end that is electrically connected to the first conductive chip 212.
, with reference to Fig. 3 c, with the capsulation material of resin for example, cover the first semiconductor chip 212 and the first heat conductive insulating substrate 211 to form the first plastic packaging layer 213.
, with reference to Fig. 3 d, remove the surface back to the first conduction heat-insulating shield 211 of (for example, grinding) first plastic packaging layer 213 to expose the first conductive projection 218.
, with reference to Fig. 3 e, form the first groove 215 ' and form the first through hole 214 that connects the first plastic packaging layer 213 and the first heat conductive insulating substrate 211 on the surface of the first plastic packaging layer 213.For example, can be take the first conductive projection 218 of exposing as starting point, utilize surface etching first groove 215 ' of laser at the first plastic packaging layer 213, and utilize laser or machine drilling to form the first through hole 214 that connects the first plastic packaging layer 213 and the first heat conductive insulating substrate 211.
With reference to Fig. 3 f, in the first groove 215 ' the filled conductive material to form the first conductive pattern 215, and in the first through hole 214 the filled conductive material to be electrically connected to the first conductive pattern 215.
, with reference to Fig. 3 g, can cover the part that is exposed of the first projection 218 and the first conductive pattern 215 to form the first insulation material layer 216 with insulating material.
, with reference to Fig. 3 h, form and be electrically connected to the first conductive projection 217 of the electric conducting material in being filled in the first through hole 214 in the end of the first through hole 214, thereby complete the preparation of the first encapsulation unit 210.Fig. 4 shows the vertical view of the first encapsulation unit 210.
Yet, be not limited to the method for above-mentioned formation the first conductive pattern 215, for example, can form the first conductive pattern 215 by deposition on the surface of the first plastic packaging layer 213.
In addition, prepare the second encapsulation unit 220 by the similar method of the method to preparation the first encapsulation unit 210.
Finally,, with reference to Fig. 3 i, the first encapsulation unit 210 and the second encapsulation unit 220 are electrically connected to and mechanically combine by the first terminal 217, thereby complete the preparation of the laminate packaging structure of semiconductor chip according to an exemplary embodiment of the present invention.Particularly, the first terminal 217 is electrically connected to an end that does not form the second terminal 227 of the second through hole 224 so that the first encapsulation unit 210 and the second encapsulation unit 220 are electrically connected to and mechanically combine.
Although described exemplary embodiment of the present invention, but be understood that, the present invention should not be limited to those illustrative embodiments, but in of the present invention as the spirit and scope of advocating here, those of ordinary skills can make various changes and modification.
Claims (10)
1. the laminate packaging structure of a semiconductor chip, is characterized in that, described laminate packaging structure comprises a plurality of encapsulation units, and each encapsulation unit comprises:
The heat conductive insulating substrate, comprise first surface and back to the second surface of first surface;
Semiconductor chip, be attached on the first surface of heat conductive insulating substrate, and comprise that wherein, semiconductor chip is included in the I/O end on first surface in the face of the second surface of heat conductive insulating substrate with back to the first surface of heat conductive insulating substrate;
The plastic packaging layer, cover the first surface of heat conductive insulating substrate and the first surface of semiconductor chip, and the surface of plastic packaging layer is formed with the conductive pattern that is electrically connected to semiconductor chip;
Through hole, connect heat conductive insulating substrate and plastic packaging layer, is filled with the electric conducting material that is electrically connected to conductive pattern in through hole;
Terminal, be formed on an end of through hole and with the electric conducting material in being filled in through hole, be electrically connected to,
Wherein, encapsulation unit combines and is electrically connected to adjacent another encapsulation unit terminal by a described encapsulation unit, the terminal of a described encapsulation unit in conjunction with and be electrically connected to the other end that does not form terminal of the through hole of adjacent described another encapsulation unit.
2. the laminate packaging structure of semiconductor chip according to claim 1, is characterized in that, is formed with the conductive projection of the I/O end that is electrically connected to semiconductor chip on the first surface of semiconductor chip, and conductive pattern is electrically connected to conductive projection.
3. the laminate packaging structure of semiconductor chip according to claim 2, is characterized in that, the part of conductive projection is exposed to the outside of plastic packaging layer.
4. the laminate packaging structure of semiconductor chip according to claim 3, is characterized in that, described laminate packaging structure also comprises the described part of the outside that is exposed to the plastic packaging layer that covers conductive projection and the insulation material layer of conductive pattern.
5. the laminate packaging structure of semiconductor chip according to claim 1, is characterized in that, conductive pattern is formed by the electric conducting material that is filled in the lip-deep groove that is formed at the plastic packaging layer.
6. a method of making the laminate packaging structure of semiconductor chip, is characterized in that, described method comprises the step of the step that forms encapsulation unit and the stacked a plurality of encapsulation units that obtain by the step that forms encapsulation unit,
Wherein, the step of formation encapsulation unit comprises:
The heat conductive insulating substrate is provided, and the heat conductive insulating substrate comprises first surface and back to the second surface of first surface;
Semiconductor chip is attached on the first surface of heat conductive insulating substrate, semiconductor chip comprises in the face of the second surface of heat conductive insulating substrate with back to the first surface of heat conductive insulating substrate;
Cover the first surface of heat conductive insulating substrate and the first surface of semiconductor chip with capsulation material, to form the plastic packaging layer;
Surface at the plastic packaging layer forms the conductive pattern that is electrically connected to semiconductor chip, forms the through hole that connects heat conductive insulating substrate and plastic packaging layer and fill the electric conducting material that is electrically connected to conductive pattern in through hole;
An end of through hole form be filled in through hole in the terminal that is electrically connected to of electric conducting material, thereby the formation encapsulation unit,
Wherein, the step of stacked a plurality of encapsulation units comprises:
With the terminal of an encapsulation unit in conjunction with and be electrically connected to the other end that does not form terminal of the through hole of another encapsulation unit.
7. method according to claim 6, is characterized in that, is formed with conductive projection on the first surface of semiconductor chip, in the step that forms conductive pattern, conductive pattern formed and is electrically connected to conductive projection.
8. method according to claim 7, is characterized in that, before forming the step of conductive pattern, the part on the surface by removing the plastic packaging layer makes the part of conductive projection be exposed to the outside of plastic packaging layer.
9. method according to claim 8, is characterized in that, the step that forms encapsulation unit also comprises: form the described part of the outside that is exposed to the plastic packaging layer that covers conductive projection and the insulation material layer of conductive pattern.
10. method according to claim 6, is characterized in that, by form groove on the surface that is etched in the plastic packaging layer and in groove the filled conductive material form conductive pattern.
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| CN2013102693077A CN103400810A (en) | 2013-06-28 | 2013-06-28 | Semiconductor chip laminating and packaging structure and manufacturing method thereof |
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| CN2013102693077A CN103400810A (en) | 2013-06-28 | 2013-06-28 | Semiconductor chip laminating and packaging structure and manufacturing method thereof |
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| CN108257926A (en) * | 2016-12-28 | 2018-07-06 | 三星电机株式会社 | Fan-out-type semiconductor package module |
| CN108364943A (en) * | 2018-02-24 | 2018-08-03 | 韩德军 | A kind of package module of power conversion circuit |
| CN110190002A (en) * | 2019-07-04 | 2019-08-30 | 环维电子(上海)有限公司 | A kind of semiconductor subassembly and its manufacturing method |
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