CN104425286A - IC carrier plate, semiconductor device having the same and manufacturing method of the IC carrier plate - Google Patents
IC carrier plate, semiconductor device having the same and manufacturing method of the IC carrier plate Download PDFInfo
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- CN104425286A CN104425286A CN201310371056.3A CN201310371056A CN104425286A CN 104425286 A CN104425286 A CN 104425286A CN 201310371056 A CN201310371056 A CN 201310371056A CN 104425286 A CN104425286 A CN 104425286A
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- contact mat
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Abstract
The invention relates to an IC carrier plate, including an interposer and a third conductive circuit layer, a second dielectric layer, an inner layer circuit board, a third dielectric layer and a fourth conductive circuit layer which are sequentially in contact. The inner layer circuit board includes a first bonding region and a first peripheral region which surrounds the first bonding region. The first bonding region of the inner layer circuit board has a first electrical contact pad close to the second dielectric layer side. The third conductive circuit layer is electrically connected with the inner layer circuit board through conductive holes in the second dielectric layer. The fourth conductive circuit layer is electrically connected with the inner layer circuit board through conductive holes in the third dielectric layer. A groove is formed in the first bonding region from the third conductive circuit layer towards the inner layer circuit board, and exposes the first electrical contact pad. The interposer is housed in the groove and two opposite sides of the interposer have a second electrical contact pad and a third electrical contact pad which are electrically connected. The second electrical contact pad is electrically connected with the first electrical contact pad. The invention also relates to a semiconductor device having the IC carrier plate and a manufacturing method of the IC carrier plate.
Description
Technical field
The present invention relates to a kind of IC support plate, there is semiconductor device and the manufacture method thereof of this IC support plate.
Background technology
Growing along with chip technology, the live width line-spacing of chip inside conductor is all more and more thinner.Line pitch for the wire density with chip that make the bearing substrate of carries chips adapts and intermediate plate usually can be used as being connected medium; but because intermediate plate and the chip that is connected electrically give prominence to described bearing substrate; the integral thickness of semiconductor device is increased, is unfavorable for realizing lightening.In addition, intermediate plate is given prominence to its electrical characteristic of bearing substrate and is subject to ectocine.
Summary of the invention
In view of this, be necessary that providing a kind of overcomes the IC support plate of the problems referred to above, the semiconductor device with this IC support plate and manufacture method.
A kind of manufacture method of IC support plate, comprise step: provide an internal layer circuit plate, described internal layer circuit plate comprises the first dielectric layer, multiple first electric contact mat and is positioned at the first conductive circuit layer and second conductive circuit layer of the described first relative both sides of dielectric layer, described first dielectric layer has multiple first conductive hole, and described first electric contact mat and described first conductive circuit layer are positioned at the first dielectric layer homonymy; In described first conductive circuit layer and described first electric contact mat pressing second dielectric layer, described second dielectric layer form multiple second conductive hole and second dielectric layer surface formed the 3rd conductive circuit layer; Described second conductive circuit layer pressing the 3rd dielectric layer, described 3rd dielectric layer form multiple 3rd conductive hole and the 3rd dielectric layer surface formed the 4th conductive circuit layer, described 3rd conductive hole pore-forming direction is identical with the first conductive hole, contrary with the second conductive hole; Form a groove from described 3rd conductive circuit layer to described internal layer circuit plate, described multiple first electric contact mat exposes from bottom portion of groove; And in described groove, an intermediate plate is installed, described intermediate plate has the second electric contact mat and the 3rd electric contact mat of multiple one_to_one corresponding electric connection relative to both sides, and described second electric contact mat and described first electric contact mat one_to_one corresponding are electrically connected.
A kind of IC support plate, it comprises intermediate plate and intermediate plate support plate, described intermediate plate support plate comprises the 3rd conductive circuit layer contacted successively, second dielectric layer, internal layer circuit plate, 3rd dielectric layer and the 4th conductive circuit layer, described internal layer circuit plate comprises the first land and the first surrounding zone around described first land, described internal layer circuit plate has multiple first electric contact mat near described second dielectric layer side, described first electric contact mat is positioned at described first land, each conductive circuit layer is electrically connected by the conductive hole in the dielectric layer that is adjacent and described internal layer circuit plate, in described second dielectric layer, conductive hole pore-forming direction is contrary with conductive hole pore-forming direction in described 3rd dielectric layer, a groove is formed with from described 3rd conductive circuit layer to described internal layer circuit plate in described first land, described in multiple first electric contact mat, bottom portion of groove exposes, described intermediate plate is contained in described groove, the relative both sides of described intermediate plate have the second electric contact mat and the 3rd electric contact mat of one_to_one corresponding electric connection, described second electric contact mat and described first electric contact mat one_to_one corresponding are electrically connected.
A kind of manufacture method of semiconductor device, comprise step: provide an internal layer circuit plate, described internal layer circuit plate comprises the first dielectric layer, multiple first electric contact mat and is positioned at the first conductive circuit layer and second conductive circuit layer of the described first relative both sides of dielectric layer, and described first electric contact mat and described first conductive circuit layer are positioned at the first dielectric layer homonymy; Pressing second dielectric layer in described first conductive circuit layer and described first electric contact mat, and form the 3rd conductive circuit layer at the second dielectric layer surface; At described second conductive circuit layer pressing the 3rd dielectric layer, and form the 4th conductive circuit layer at the 3rd dielectric layer surface; Form a groove from described 3rd conductive circuit layer to described internal layer circuit plate, described multiple first electric contact mat exposes from bottom portion of groove; In described groove, install an intermediate plate, described intermediate plate has the second electric contact mat and the 3rd electric contact mat of multiple one_to_one corresponding electric connection relative to both sides, and described second electric contact mat and described first electric contact mat one_to_one corresponding are electrically connected; And on described intermediate plate, a chip is installed, described chip comprises multiple electronic pads, and described electronic pads and described 3rd electric contact mat one_to_one corresponding are electrically connected.
A kind of semiconductor device, it comprises IC support plate and chip.Described IC support plate comprises intermediate plate and intermediate plate support plate, described intermediate plate support plate comprises the 3rd conductive circuit layer contacted successively, second dielectric layer, internal layer circuit plate, 3rd dielectric layer and the 4th conductive circuit layer, described internal layer circuit plate comprises the first land and the first surrounding zone around described first land, described internal layer circuit plate has multiple first electric contact mat near described second dielectric layer side, described first electric contact mat is positioned at described first land, each conductive circuit layer is electrically connected by the conductive hole in the dielectric layer that is adjacent and described internal layer circuit plate, in described second dielectric layer, conductive hole pore-forming direction is contrary with conductive hole pore-forming direction in described 3rd dielectric layer, a groove is formed with from described 3rd conductive circuit layer to described internal layer circuit plate in described first land, described in multiple first electric contact mat, bottom portion of groove exposes, described intermediate plate is contained in described groove, the relative both sides of described intermediate plate have the second electric contact mat and the 3rd electric contact mat of one_to_one corresponding electric connection, described second electric contact mat and described first electric contact mat one_to_one corresponding are electrically connected.Described chip is arranged on described intermediate plate.Described chip has multiple electronic pads.All described 3rd electric contact mat is electrically connected each electronic pads with one.
IC support plate of the present invention is formed with groove, and to be contained in completely by intermediate plate in described groove and described intermediate plate can be avoided to be affected by the external environment on the one hand, can reduce Total Product thickness on the other hand.In addition, all form build-up circuit in internal layer circuit layer both sides, the problem of plate face warpage after formed product can be prevented.
Accompanying drawing explanation
Fig. 1 is the cutaway view of the internal layer circuit plate that the embodiment of the present invention provides.
Fig. 2 is the cutaway view of the substrate that the forming step first step of the plate of internal layer circuit shown in Fig. 1 provides.
Fig. 3 is that the first dielectric layer surface of the substrate shown in Fig. 2 forms the second conductive circuit layer and cutaway view after form the first conductive hole in described first dielectric layer.
Fig. 4 is the cutaway view after the first copper foil layer shown in Fig. 3 separates with substrate.
Fig. 5 is the cutaway view after the first copper foil layer shown in Fig. 4 being made the first conductive circuit layer and multiple first electric contact mat.
Fig. 6 the first conductive circuit layer shown in Fig. 5 will be formed the second dielectric layer and the 3rd conductive circuit layer, and the cutaway view form the second conductive hole in described second dielectric layer after.
Fig. 7 forms the 3rd dielectric layer and the 4th conductive circuit layer in the second conductive circuit layer shown in Fig. 6, and in described 3rd dielectric layer, form the cutaway view after the 3rd conductive hole.
Fig. 8 is the cutaway view form the first welding resisting layer and the second welding resisting layer respectively in the 3rd conductive circuit layer shown in Fig. 7 and the 4th conductive circuit layer after.
Fig. 9 is the cutaway view after the first welding resisting layer shown in Fig. 8 forms groove to described internal layer circuit plate.
Figure 10 installs the cutaway view that an intermediate plate obtains described IC support plate in the groove shown in Fig. 9.
Figure 11 encapsulates the cutaway view that a chip obtains described semiconductor device on the intermediate plate shown in Figure 10.
Main element symbol description
| Semiconductor device | 100 |
| IC support plate | 60 |
| Internal layer circuit plate | 10 |
| First land | 11 |
| First surrounding zone | 12 |
| First conductive circuit layer | 13 |
| First dielectric layer | 14 |
| First conductive hole | 141 |
| Second conductive circuit layer | 15 |
| First electric contact mat | 16 |
| Diaphragm | 17 |
| Substrate | 130 |
| Second land | 131 |
| Second week border area | 132 |
| Loading plate | 133 |
| Dielectric film | 134 |
| First covers Copper base material | 135 |
| First copper foil layer | 1351 |
| Second dielectric layer | 21 |
| 3rd conductive circuit layer | 22 |
| Second conductive hole | 211 |
| 3rd dielectric layer | 31 |
| 4th conductive circuit layer | 32 |
| 3rd conductive hole | 311 |
| First welding resisting layer | 41 |
| First opening | 411 |
| First weld pad | 412 |
| Second welding resisting layer | 42 |
| Second opening | 421 |
| Second weld pad | 422 |
| Groove | 40 |
| Opening | 23 |
| Intermediate plate | 50 |
| Substrate of glass | 51 |
| Second electric contact mat | 52 |
| 3rd electric contact mat | 53 |
| 4th conductive hole | 511 |
| First conducting wire | 512 |
| First conductive projection | 54 |
| Underfill | 70 |
| Chip | 80 |
| Electronic pads | 81 |
| Second conductive projection | 82 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
The invention provides a kind of IC support plate and have the manufacture method of semiconductor device of this IC support plate, concrete steps are as follows:
The first step, refers to Fig. 1, provides an internal layer circuit plate 10.
Described internal layer circuit plate 10 comprises first land 11 and separates with dotted line in the first surrounding zone 12(figure of described first land 11).Described internal layer circuit plate 10 at least comprises the first conductive circuit layer 13, first dielectric layer 14, second conductive circuit layer 15, multiple first electric contact mat 16 and diaphragm 17.In the present embodiment, described internal layer circuit plate 10 comprises the first conductive circuit layer 13, first dielectric layer 14, second conductive circuit layer 15, multiple first electric contact mat 16 and diaphragm 17.Described first conductive circuit layer 13 and described second conductive circuit layer 15 are formed at the relative both sides of described first dielectric layer 14.Described first conductive circuit layer 13 is positioned at described first surrounding zone 12.Described multiple first electric contact mat 16 and described first conductive circuit layer 13 are positioned at the same side of described first dielectric layer 14, and are positioned at described first land 11.Described diaphragm 17 is formed at described first land 11, and covers the first dielectric layer 14 described first electric contact mat 16 and described first land 11 exposed from described first electric contact mat 16.There is in described first dielectric layer 14 multiple the first conductive hole 141 running through described first dielectric layer 14.Described first conductive circuit layer 13 and described first electric contact mat 16 are electrically connected with described second conductive circuit layer 15 by described first conductive hole 141.
Described internal layer circuit plate 10 is by such as under type acquisition:
First, refer to Fig. 2, a substrate 130 is provided.Described substrate 130 comprises second land 131 and separates with dotted line in the second week border area 132(figure of described second land 131).Described second land 131 is corresponding with described first land 11.Described second week border area 132 is corresponding with described first surrounding zone 12.Described substrate 130 comprises 134, two first, a loading plate 133, two dielectric films and covers Copper base material 135.Described two first cover Copper base material 135 is bonded in described loading plate 133 relative both sides respectively by a dielectric film 134.Described first covers Copper base material 135 all can be one side and covers Copper base material or double-sided copper-clad base material.In the present embodiment, described first covers Copper base material 135 for one side covers Copper base material.Described first covers Copper base material 135 includes the first copper foil layer 1351 and the first dielectric layer 14.All more adjacent described first dielectric layer 14 of each described first copper foil layer 1351 is near described loading plate 133.
Then, refer to Fig. 3, form the first blind hole (not shown) from described first dielectric layer 14 away from laser ablation equal in the first dielectric layer 14 described in described loading plate 133 side direction.Described first blind hole runs through the first dielectric layer 14, and part first copper foil layer 1351 exposes from described first blind via bottom.
Then, on the hole wall and described first dielectric layer 14 of described first blind hole chemical deposition first thin copper layer (not shown) as plating seed layer.
Then, described first dielectric layer 14 is all formed the first plating resist barrier (not shown) with pattern structure, exposes described first blind hole and described first thin copper layer of part.
Then, plating is filled up described first blind hole and is formed described first conductive hole 141, and electroplates formation second conductive circuit layer 15 at described first conductive hole 141 away from the end of described first copper foil layer 1351 and from the first thin copper layer that described first plating resist barrier is exposed.
Then, remove described first plating resist barrier, and fast-etching removes described first thin copper layer of part hidden by described first plating resist barrier.
Then, refer to Fig. 4 and Fig. 5, described first copper foil layer 1351 is all separated with described dielectric film 134, expose described first copper foil layer 1351.Then, by image transfer and etching method, the first copper foil layer 1351 being positioned at described second week border area 132 is made described first conductive circuit layer 13, and the first copper foil layer 1351 being positioned at described second land 131 is made described first electric contact mat 16.
Finally; refer to Fig. 1; first electric contact mat 16 of described second land 131 forms described diaphragm 17; described diaphragm 17 covers the first dielectric layer 14 that described first electric contact mat 16 and described second land 131 are exposed from the first electric contact mat 16, obtains described internal layer circuit plate 10.
Second step, refers to Fig. 6, in described first conductive circuit layer 13 and diaphragm 17 pressing second dielectric layer 21, formed in described second dielectric layer 21 second conductive hole 211 and described second dielectric layer 21 surface formed the 3rd conductive circuit layer 22.
The first dielectric layer 14 that described second dielectric layer 21 covers described diaphragm 17, first conductive circuit layer 13 and exposes from described first conductive circuit layer 13.Described 3rd conductive circuit layer 22 is formed at the surface of described second dielectric layer 21 away from described first conductive circuit layer 13 side.Described 3rd conductive circuit layer 22 region corresponding with described first land 11 is not distributed with conducting wire.Described second conductive hole 211 is formed in described second dielectric layer 21, and runs through described second dielectric layer 21 in a thickness direction.Described 3rd conductive circuit layer 22 is electrically connected by described second conductive hole 211 with described first conductive circuit layer 13.Described second dielectric layer 21, second conductive hole 211 and the 3rd conductive circuit layer 22 are formed at described diaphragm 17, first conductive circuit layer 13 and from the first dielectric layer 14 that described first conductive circuit layer 13 is exposed, wherein said second conductive hole 211 and the 3rd conductive circuit layer 22 are formed by semi-additive process.
Particularly, first, pressing second dielectric layer 21 in described first conductive circuit layer 13 and diaphragm 17.The first dielectric layer 14 that described second dielectric layer 21 covers described first conductive circuit layer 13, diaphragm 17 and exposes from described first conductive circuit layer 13.Then, multiple second blind hole (not shown) is formed away from the second dielectric layer 21 described in described first conductive circuit layer 13 side direction by the mode of laser ablation from described second dielectric layer 21.Described second blind hole runs through described second dielectric layer 21, and part first conductive circuit layer 13 is exposed from described second blind via bottom.Then, in described second dielectric layer 21 surface and hole wall chemical deposition one deck second thin copper layer (not shown) of described multiple second blind hole as plating seed layer.Then, described second dielectric layer 21 forms one deck and there is pattern structure second plating resist barrier (not shown).Multiple second blind hole and part second thin copper layer expose from described second plating resist barrier.Then, described second blind hole is filled up in plating, forms the second conductive hole 211 and forms the 3rd conductive circuit layer 22 at described second conductive hole 211 away from the end of described first conductive circuit layer 13 and from the second thin copper layer that described second plating resist barrier is exposed.Finally, remove described second plating resist barrier and fast-etching remove by described second plating resist barrier hide the second thin copper layer.
3rd step, refers to Fig. 7, in described second conductive circuit layer 15 pressing the 3rd dielectric layer 31, in described 3rd dielectric layer 31 formed the 3rd conductive hole 311 and described 3rd dielectric layer 31 surface formed the 4th conductive circuit layer 32.
The first dielectric layer 14 that described 3rd dielectric layer 31 covers described second conductive circuit layer 15 and exposes from described second conductive circuit layer 15.Described 4th conductive circuit layer 32 is formed at the surface of described 3rd dielectric layer 31 away from described second conductive circuit layer 15 side.Described 3rd conductive hole 311 is formed in described 3rd dielectric layer 31, and it runs through described 3rd dielectric layer 31 in a thickness direction.Described 4th conductive circuit layer 32 is electrically connected by described 3rd conductive hole 311 with described second conductive circuit layer 15.Described 3rd dielectric layer 31, the 3rd conductive hole 311 and the 4th conductive circuit layer 32 are formed in described second conductive circuit layer 15 by semi-additive process, and its concrete generation type is identical with the generation type of described second dielectric layer 21, second conductive hole 211 and the 3rd conductive circuit layer 22.
4th step, refers to Fig. 8, and described 3rd conductive circuit layer 22 forms the first welding resisting layer 41.Described first welding resisting layer 41 covers described 3rd conductive circuit layer 22 and is positioned at described first surrounding zone 12 and the second dielectric layer 21 exposed from described 3rd conductive circuit layer 22, exposes the second dielectric layer 21 of described first land 11.Described first welding resisting layer 41 has multiple first opening 411.Described 3rd conductive circuit layer 22 of part is exposed from described first opening 411, forms the first weld pad 412.
Described 4th conductive circuit layer 32 forms the second welding resisting layer 42.The 3rd dielectric layer 31 that described second welding resisting layer 42 covers described 4th conductive circuit layer 32 and exposes from described 4th conductive circuit layer 32.Described second welding resisting layer 42 has multiple second opening 421.Described 4th conductive circuit layer 32 of part is exposed from described second opening 421, forms the second weld pad 422.
5th step, refers to Fig. 9, forms a groove 40 from described first welding resisting layer 41 to described first conductive circuit layer 13.Multiple described first electric contact mat 16 exposes bottom described groove 40.
Particularly, from described first welding resisting layer 41 to described first conductive circuit layer 13, the border along described first land 11 and the first surrounding zone 12 forms an opening (not shown) by the mode of dragging for type or laser cutting.Described opening ends in the surface of described first dielectric layer 14 away from described second conductive circuit layer 15 side at thickness direction.Then remove the second dielectric layer 21 in described opening and diaphragm 17, expose described multiple first electric contact mat 16.
6th step, refers to Figure 10, in described groove 40, install an intermediate plate 50.Described intermediate plate 50 is contained in described groove 40 completely, and that is, in a thickness direction, described intermediate plate 50 does not exceed the surface of described 3rd conductive circuit layer 22 near described second dielectric layer 21 away from the surface of described first dielectric layer 14.Described intermediate plate 50 comprises the first substrate of glass 51 and is exposed to multiple second electric contact mat 52 and the 3rd electric contact mat 53 of the relative both sides of described first substrate of glass 51.Multiple 4th conductive hole 511 and many articles of the first conducting wires 512 are formed in described first substrate of glass 51.Described multiple 4th conductive hole 511 is positioned at described first substrate of glass 51 near described first conductive circuit layer 13 side, and each described 4th conductive hole 511 near one end of described first conductive circuit layer 13, all described second electric contact mat 52 is electrically connected with one, each described 4th conductive hole 511 is all electrically connected with one article of first conducting wire 512 away from one end of described first conductive circuit layer 13.Described many first conducting wires 512 are positioned at described first substrate of glass 51 away from described first conductive circuit layer 13 side, and away from described first conductive circuit layer 13 one end, all described 3rd electric contact mat 53 is electrically connected with one in the first conducting wire 512 described in every article.Near described first conductive circuit layer 13 one end, all described 4th conductive hole 511 is electrically connected away from one end of described first conductive circuit layer 13 with one in first conducting wire 512 described in every article, to realize each described second electric contact mat 52 all by the electric connection with corresponding described 3rd electric contact mat 53 of the 4th conductive hole 511 and one article of first conducting wire 512.Each described second electric contact mat 52 is all electrically connected with described first electric contact mat 16 by first conductive projection 54, obtains described IC support plate 60.
7th step, refers to Figure 11, and described intermediate plate 50 encapsulates a chip 80 with underfill 70.Described chip 80 has multiple electronic pads 81.Each described electronic pads 81 is all electrically connected with described 3rd electric contact mat 53 by second conductive projection 82.Described underfill 70 is formed at the space between described electronic pads 81, second conductive projection 82 and described 3rd electric contact mat 53, and the space between the space filled up between described intermediate plate 50 and described second dielectric layer 21 and described second electric contact mat 52, first conductive projection 54 and the first electric contact mat 16.So far, described semiconductor device 100 is obtained.
Be understandable that, the internal layer circuit plate provided in the first step can also to be included in the second conductive circuit layer pressing at least one dielectric layer and form conductive circuit layer at described at least one deck dielectric layer surface.
Be understandable that, after the 3rd step completes, described IC support plate and the manufacture method of semiconductor device with this IC support plate also comprise and in described 3rd conductive circuit layer and the 4th conductive circuit layer, form new dielectric layer and conductive circuit layer respectively.Now, described welding resisting layer is formed in new conductive circuit layer.
Be understandable that, in other embodiment, after completing the 3rd step, first can form described groove from described 3rd conductive circuit layer to described first dielectric layer, and then form described first welding resisting layer and the second welding resisting layer in described 3rd conductive circuit layer and the 4th conductive circuit layer.
Be understandable that, after the 4th step completes, described IC support plate and the manufacture method of semiconductor device with this IC support plate are also included on the first weld pad and the second weld pad that expose carries out surface treatment, to avoid weld pad surface oxidation, and then affects its electrical characteristic.Surface-treated mode can adopt the mode such as chemical gilding, chemical nickel plating to form protective layer, or on weld pad, forms organic guarantor weld film (OSP).
Be understandable that, after the 6th step completes, the IC support plate that the technical program provides and the manufacture method of semiconductor device with this IC support plate can also be included in the step described first weld pad and the second weld pad being formed soldered ball and be electrically connected electric component or packaging body by described soldered ball.
Refer to Figure 11, the technical program also provides a kind of semiconductor device 100 made by said method, and it comprises IC support plate 60, underfill 70 and chip 80.
Described IC support plate 60 comprises internal layer circuit plate 10, second dielectric layer 21, the 3rd dielectric layer 31, the 3rd conductive circuit layer 22, the 4th conductive circuit layer 32, first welding resisting layer 41, second welding resisting layer 42 and intermediate plate 50.Wherein, the structure that described internal layer circuit plate 10, second dielectric layer 21, the 3rd dielectric layer 31, the 3rd conductive circuit layer 22 and the 4th conductive circuit layer 32 are formed can regard an intermediate plate support plate as.
Described internal layer circuit plate 10 comprises the first land 11 and separates with dotted line in the first surrounding zone 12(figure of described first land 11).Described internal layer circuit plate 10 comprises the first dielectric layer 14, first conductive circuit layer 13, second conductive circuit layer 15 and multiple first electric contact mat 16.In described first dielectric layer 14, there is multiple first conductive hole 141.Described first conductive hole 141 runs through described first dielectric layer 14.Described first conductive circuit layer 13 and the second conductive circuit layer 15 are positioned at the relative both sides of described first dielectric layer 14.Described first conductive circuit layer 13 is formed at described first surrounding zone 12.Described multiple first electric contact mat 16 and described first conductive circuit layer 13 are positioned at the same side of described first dielectric layer 14.Described first electric contact mat 16 is positioned at described first land 11.Described first conductive circuit layer 13 and multiple first electric contact mat 16 are electrically connected with described second conductive circuit layer 15 by described first conductive hole 141.
Described second dielectric layer 21 is formed at described first conductive circuit layer 13 side, and the first dielectric layer 14 covering described first conductive circuit layer 13 and expose from described first conductive circuit layer 13.There is in described second dielectric layer multiple second conductive hole 211.Described second conductive hole 211 runs through described second dielectric layer 21 in a thickness direction.
Described 3rd conductive circuit layer 22 is formed at described second dielectric layer 21 away from described first conductive circuit layer 13 side, and described 3rd conductive circuit layer 22 region corresponding with described first land 11 is not distributed with conducting wire.Described 3rd conductive circuit layer 22 is electrically connected with described first conductive circuit layer 13 by described second conductive hole 211.
Described 3rd dielectric layer 31 is formed at described second conductive circuit layer 15 side, and covers described second conductive circuit layer 15 and expose the first dielectric layer 14 from described second conductive circuit layer 15.Described 3rd dielectric layer 31 has multiple 3rd conductive hole 311.Described 3rd conductive hole 311 runs through described 3rd dielectric layer 31 in a thickness direction.
Described 4th conductive circuit layer 32 is formed at described 3rd dielectric layer 31 away from described second conductive circuit layer 15 side.Described 4th conductive circuit layer 32 is electrically connected with described second conductive circuit layer 15 by described 3rd conductive hole 311.
Described first welding resisting layer 41 is formed in described 3rd conductive circuit layer 22.Described first welding resisting layer 41 covers the second dielectric layer 21 that described 3rd conductive circuit layer 22 and described first surrounding zone 12 are exposed from described 3rd conductive circuit layer 22.Described first welding resisting layer 41 has multiple first opening 411, and described in exposed portion, the 3rd conductive circuit layer 22 forms the first weld pad 412.
Described second welding resisting layer 42 is formed in described 4th conductive circuit layer 32.The 3rd dielectric layer 31 that described second welding resisting layer 42 covers described 4th conductive circuit layer 32 and exposes from described 4th conductive circuit layer 32.Described second welding resisting layer 42 has multiple second opening 421, and described in exposed portion, the 4th conductive circuit layer 32 forms the second weld pad 422.
A groove 40 is formed with to described first dielectric layer 14 from described first welding resisting layer 41.Described groove 40 is positioned at described first land 11, and runs through described second dielectric layer 21, exposes described first electric contact mat 16 and part of first dielectric layer 14.
Described intermediate plate 50 is contained in described groove 40 completely, and that is, in a thickness direction, described intermediate plate 50 does not exceed the surface of described 3rd conductive circuit layer 22 near described second dielectric layer 21 away from the surface of described first dielectric layer 14.Described intermediate plate 50 comprises the first substrate of glass 51 and is exposed to described first substrate of glass 51 relatively the second electric contact mat 52 of multiple electric connections of both sides and the 3rd electric contact mat 53.Each described second electric contact mat 52 is all electrically connected with described first electric contact mat 16 by first conductive projection 54.
Described chip 80 is installed on described intermediate plate 50.Described chip 80 has multiple electronic pads 81.Each described electronic pads 81 is all electrically connected with described 3rd electric contact mat 53 by second conductive projection 82.
Described underfill 70 is formed at the space between described electronic pads 81, second conductive projection 82 and the 3rd electric contact mat 53, and the space between the space filled up between described intermediate plate 50 and described second dielectric layer 21 and described first electric contact mat 16, first conductive projection 54 and described second electric contact mat 52.
IC support plate of the present invention is formed with groove, and is contained in completely by intermediate plate in described groove, described intermediate plate can be avoided to be affected by the external environment on the one hand, can reduce Total Product thickness on the other hand.In addition, all form build-up circuit in internal layer circuit layer both sides, the problem of plate face warpage after formed product can be prevented.
Be understandable that, for the person of ordinary skill of the art, other various corresponding change and distortion can be made according to the technical conceive of the technical program, and all these change the protection range that all should belong to the technical program claim with distortion.
Claims (8)
1. a manufacture method for IC support plate, comprises step:
An internal layer circuit plate is provided, described internal layer circuit plate comprises the first dielectric layer, multiple first electric contact mat and is positioned at the first conductive circuit layer and second conductive circuit layer of the described first relative both sides of dielectric layer, described first dielectric layer has multiple first conductive hole, and described first electric contact mat and described first conductive circuit layer are positioned at the first dielectric layer homonymy;
In described first conductive circuit layer and described first electric contact mat pressing second dielectric layer, described second dielectric layer form multiple second conductive hole and second dielectric layer surface formed the 3rd conductive circuit layer;
Described second conductive circuit layer pressing the 3rd dielectric layer, described 3rd dielectric layer form multiple 3rd conductive hole and the 3rd dielectric layer surface formed the 4th conductive circuit layer, described 3rd conductive hole pore-forming direction is identical with the pore-forming direction of the first conductive hole, contrary with the pore-forming direction of the second conductive hole;
Form a groove from described 3rd conductive circuit layer to described internal layer circuit plate, described multiple first electric contact mat exposes from bottom portion of groove; And
In described groove, install an intermediate plate, described intermediate plate has the second electric contact mat and the 3rd electric contact mat of multiple one_to_one corresponding electric connection relative to both sides, and described second electric contact mat and described first electric contact mat one_to_one corresponding are electrically connected.
2. the manufacture method of IC support plate as claimed in claim 1, it is characterized in that, described internal layer circuit plate comprises first land and the first surrounding zone around described first land, described multiple first electric contact mat is positioned at described first land, and described first conductive circuit layer is positioned at described first surrounding zone.
3. the manufacture method of IC support plate as claimed in claim 2, it is characterized in that, the manufacture method of described internal layer circuit plate, comprise step: provide a substrate, described substrate comprises second land corresponding with described first land and the second week border area corresponding with described first surrounding zone, and described substrate comprises a loading plate, be positioned at described loading plate relative to two the first copper foil layers of both sides and be positioned at first dielectric layer of two the first copper foil layers away from described loading plate side; The second conductive circuit layer is all formed at the first dielectric layer surface; Described first copper foil layer is all separated with described loading plate; First copper foil layer in described second week border area is all made the first conductive circuit layer, and the first copper foil layer of described second land is all made described first electric contact mat.
4. an IC support plate, it comprises intermediate plate and intermediate plate support plate, described intermediate plate support plate comprises the 3rd conductive circuit layer contacted successively, second dielectric layer, internal layer circuit plate, 3rd dielectric layer and the 4th conductive circuit layer, described internal layer circuit plate comprises the first land and the first surrounding zone around described first land, described internal layer circuit plate has multiple first electric contact mat near described second dielectric layer side, described first electric contact mat is positioned at described first land, each conductive circuit layer is by being adjacent conductive hole in dielectric layer and described internal layer circuit plate is electrically connected, in described second dielectric layer, conductive hole pore-forming direction is contrary with conductive hole pore-forming direction in described 3rd dielectric layer, a groove is formed with from described 3rd conductive circuit layer to described internal layer circuit plate in described first land, expose described multiple first electric contact mat, described intermediate plate is contained in described groove, the relative both sides of described intermediate plate have the second electric contact mat and the 3rd electric contact mat that are mutually electrically connected, described second electric contact mat and described first electric contact mat are electrically connected.
5. IC support plate as claimed in claim 4, it is characterized in that, in a thickness direction, described intermediate plate does not exceed described 3rd conductive circuit layer near described second dielectric layer side surface away from the surface of described first dielectric layer.
6. a manufacture method for semiconductor device, comprises step: provide an IC support plate as described in claim 5 or 6;
And on described intermediate plate, a chip is installed, described chip comprises multiple electronic pads, and described electronic pads and described 3rd electric contact mat one_to_one corresponding are electrically connected.
7. the manufacture method of semiconductor device as claimed in claim 6, it is characterized in that, after described intermediate plate installs a chip, be also included in the step that underfill is filled up in the space between described 3rd electric contact mat and described electronic pads, the space between described intermediate plate and described second dielectric layer and the space between described first electric contact mat and the second electric contact mat.
8. a semiconductor device, it comprises IC support plate as described in any one of claim 5 to 6 and chip, and described chip is arranged on described intermediate plate, and described chip has multiple electronic pads, and all described 3rd electric contact mat is electrically connected each electronic pads with one.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310371056.3A CN104425286A (en) | 2013-08-23 | 2013-08-23 | IC carrier plate, semiconductor device having the same and manufacturing method of the IC carrier plate |
| TW102132132A TWI511250B (en) | 2013-08-23 | 2013-09-06 | Ic substrate,semiconductor device with ic substrate and manufucturing thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310371056.3A CN104425286A (en) | 2013-08-23 | 2013-08-23 | IC carrier plate, semiconductor device having the same and manufacturing method of the IC carrier plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104425286A true CN104425286A (en) | 2015-03-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310371056.3A Pending CN104425286A (en) | 2013-08-23 | 2013-08-23 | IC carrier plate, semiconductor device having the same and manufacturing method of the IC carrier plate |
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| Country | Link |
|---|---|
| CN (1) | CN104425286A (en) |
| TW (1) | TWI511250B (en) |
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| CN111326640A (en) * | 2018-12-13 | 2020-06-23 | 同泰电子科技股份有限公司 | Method for forming window on light-emitting diode carrier plate |
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| CN115052435A (en) * | 2021-03-08 | 2022-09-13 | 欣兴电子股份有限公司 | Circuit board embedded with intermediate substrate and forming method thereof |
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| US9609746B1 (en) * | 2015-12-14 | 2017-03-28 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
| TWI820402B (en) | 2021-03-08 | 2023-11-01 | 欣興電子股份有限公司 | Wiring board with embedded interposer substrate and method of fabricating the same |
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| CN111326640B (en) * | 2018-12-13 | 2022-08-09 | 同泰电子科技股份有限公司 | Method for forming window on light-emitting diode carrier plate |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI511250B (en) | 2015-12-01 |
| TW201513280A (en) | 2015-04-01 |
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