CN102915978A - Semiconductor packaging structure - Google Patents

Semiconductor packaging structure Download PDF

Info

Publication number
CN102915978A
CN102915978A CN2012104440976A CN201210444097A CN102915978A CN 102915978 A CN102915978 A CN 102915978A CN 2012104440976 A CN2012104440976 A CN 2012104440976A CN 201210444097 A CN201210444097 A CN 201210444097A CN 102915978 A CN102915978 A CN 102915978A
Authority
CN
China
Prior art keywords
chip
columnar electrode
layer
soldered ball
metal layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012104440976A
Other languages
Chinese (zh)
Other versions
CN102915978B (en
Inventor
林仲珉
陶玉娟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tongfu Microelectronics Co Ltd
Original Assignee
Nantong Fujitsu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nantong Fujitsu Microelectronics Co Ltd filed Critical Nantong Fujitsu Microelectronics Co Ltd
Priority to CN201210444097.6A priority Critical patent/CN102915978B/en
Publication of CN102915978A publication Critical patent/CN102915978A/en
Priority to US14/074,687 priority patent/US9293338B2/en
Application granted granted Critical
Priority to US15/014,929 priority patent/US9431325B2/en
Publication of CN102915978B publication Critical patent/CN102915978B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)

Abstract

The invention provides a semiconductor packaging structure, comprising a chip, a first bottom metal layer, a first columnar electrode, a first diffusion impervious layer, a first welding ball and a packaging substrate, wherein the first bottom metal layer is arranged on a first surface of the chip; the first columnar electrode is arranged on the first bottom metal layer; a part of the first bottom metal layer is exposed at the periphery of the first columnar electrode; the first diffusion impervious layer is arranged on the surface of the first columnar electrode; the first welding ball is arranged on the first diffusion impervious layer; the first welding ball is at least packaged at the top of the first columnar electrode and the surface of the side wall; the packaging substrate is opposite to the first surface of the chip; and the chip is reversely arranged on the packaging substrate and the first welding ball on the chip is connected with a welding terminal of the packaging substrate. The first welding ball is formed on the first columnar electrode so that the distance between the chip and the packaging substrate becomes large; and a gap between the chip and the packaging substrate can be completely filled when a packaging material is subsequently formed, and the stability and the reliability of the chip are not influenced.

Description

Semiconductor package
Technical field
The present invention relates to semiconductor technology, particularly a kind of semiconductor package.
Background technology
Along with the development of electronic product to miniaturization, in the large scale integrated circuit and very lagre scale integrated circuit (VLSIC) of the consumer electronics field such as notebook computer, panel computer, smart mobile phone, digital camera, requirement to die size is more and more higher, need the semiconductor package of formation more and more less, more and more thinner.
Please refer to Fig. 1, structural representation for a kind of semiconductor package of prior art, specifically comprise: base plate for packaging 10 be positioned at the chip 20 on the described base plate for packaging 10, and the second surface 21 of the first surface 11 of described base plate for packaging 10 and described chip 20 is oppositely arranged; Be positioned at the soldered ball 22 on the second surface 21 of described chip 20, described soldered ball 22 is connected with circuit structure (not shown) electricity in the chip 20, described soldered ball 22 is connected with the conducting terminal 15 of the first surface 11 of base plate for packaging 10, so that the circuit in the described chip 20 is connected with external circuit by described soldered ball 22, conducting terminal 15; End filler 30 between described chip 20 and base plate for packaging 10; Cover the potting resin material 40 on described chip 20 and base plate for packaging 10 surfaces.Because the spacing between described chip 20 and the base plate for packaging 10 is very little, described spacing equals the height of soldered ball 22, therefore directly when described chip 20 and base plate for packaging 10 surface formation potting resin material 40, described potting resin material 40 can not fill up the gap between chip 20 and the base plate for packaging 10, have interior void, easily cause the accumulation of electric charge and steam, so that chip, base plate for packaging corrosion.Even utilizing first the gap between 30 pairs of described chips 20 of end filler and the base plate for packaging 10 fills, recycling potting resin material 40 covers described chip 20 and base plate for packaging 10 surfaces, can be owing to the gap all too is little, still may between chip 20 and base plate for packaging 10, form the cavity, affect stability and the reliability of chip.
More formation methods about described semiconductor package please refer to the american documentation literature that US publication is US2010/0285637A1.
Summary of the invention
The problem that the present invention solves provides a kind of semiconductor package, can avoid having the cavity between chip and the base plate for packaging, affects stability and the reliability of chip.
For addressing the above problem, technical solution of the present invention provides a kind of semiconductor package, comprising: chip, and described chip has first surface and second surface, is positioned at the first bottom metal layers of described chip first surface; Be positioned at the first columnar electrode on described the first bottom metal layers, expose part the first bottom metal layers around described the first columnar electrode; Be positioned at first diffusion impervious layer on the first bottom metal layers surface that exposes around described the first columnar electrode sidewall surfaces, top surface, the first columnar electrode; Be positioned at the first soldered ball on described the first diffusion impervious layer, described the first soldered ball is wrapped in the surface of described the first columnar electrode top and sidewall at least; The base plate for packaging that is oppositely arranged with the first surface of chip, described base plate for packaging has solder terminal, the position of described solder terminal is corresponding with the position of the first soldered ball, and described flip-chip is on the described base plate for packaging and be positioned at the first soldered ball on the described chip and the interconnection of described solder terminal.
Optionally, also comprise: the second bottom metal layers that is positioned at described chip first surface, described the second bottom metal layers and the first bottom metal layers electric isolation, be positioned at second columnar electrode on described the second bottom metal layers surface, expose part the second bottom metal layers around described the second columnar electrode; Be positioned at second diffusion impervious layer on the second bottom metal layers surface that exposes around described the second columnar electrode sidewall surfaces, top surface, the second columnar electrode; Be positioned at the second soldered ball on described the second diffusion impervious layer, described the second soldered ball is wrapped in the surface of described the second columnar electrode top and sidewall at least; Be positioned at the first heating panel of described base plate for packaging, the position of described the first heating panel is corresponding with the position of the second soldered ball, and described the second soldered ball and the interconnection of described the first heating panel.
Optionally, described solder terminal is positioned at the submarginal position of base plate for packaging, described the first heating panel is positioned at the centre position of base plate for packaging, corresponding, the submarginal position of first surface that described the first soldered ball is positioned at described chip, described the second soldered ball are positioned at the first surface of chip near middle position.
Optionally, described the first soldered ball also covers first diffusion impervious layer on described the first bottom metal layers surface, and described the second soldered ball also covers second diffusion impervious layer on described the second bottom metal layers surface
Optionally, the quantity of described the first heating panel is one or more, described the first heating panel be shaped as regular figure or irregular figure.
Optionally, when described the first heating panel was polylith, described the first heating panel distributed for concentrating to distribute or disperse.
Optionally, described base plate for packaging is a kind of in resin substrate, ceramic substrate, glass substrate, silicon substrate, metal substrate, metal framework and the alloy framework.
Optionally, also comprise: the potting resin material on the end filler between described chip and package substrates and the described chip of covering, package substrates surface.
Optionally, also comprise: between described chip and package substrates and cover the potting resin material on described chip, package substrates surface.
Optionally, described potting resin material exposes the second surface of described chip.
Optionally, also comprise, with bonding the second heating panel of described chip second surface, described potting resin material exposes described the second heating panel surface.
Optionally, the altitude range of described the first columnar electrode and the second columnar electrode is 4 μ m ~ 100 μ m.
Compared with prior art, the present invention has the following advantages:
The embodiment of the invention interconnects described chip and base plate for packaging by the first columnar electrode and the first soldered ball that is positioned on described the first columnar electrode, because described the first soldered ball is formed on described the first columnar electrode, so that the spacing between described chip and the base plate for packaging becomes large, can fill the gap between completely described chip and the base plate for packaging when being conducive to follow-up formation potting resin material fully, avoid existing between chip and the base plate for packaging cavity can affect stability and the reliability of chip.
Further, when having the second columnar electrode and the second soldered ball that is positioned on the described columnar electrode on the described chip, described base plate for packaging has the first heating panel, when described flip-chip is to the described base plate for packaging, described the second soldered ball and the interconnection of the first heating panel, the heat that utilizes described the second columnar electrode and the second soldered ball that described chip first surface is produced is directly transferred to the first heating panel and is dispelled the heat, the radiating efficiency of energy Effective Raise semiconductor package.
Description of drawings
Fig. 1 is the structural representation of the semiconductor package of prior art;
Fig. 2 ~ Figure 15 is the structural representation of the semiconductor package of the embodiment of the invention.
Embodiment
As shown in background technology, owing to the size of the soldered ball that utilizes prior art to form is less, so that the spacing between described chip and the base plate for packaging is too small, the potting resin material of follow-up formation can not effectively be filled the space between described chip and the base plate for packaging, have interior void between described chip and the base plate for packaging, easily cause the accumulation of electric charge and steam, so that chip, base plate for packaging corrosion, affect stability and the reliability of chip.And if improve spacing between described chip and the base plate for packaging by the size that increases soldered ball, described larger-size soldered ball can occupy more chip area, reduce the quantity of packaging pin in the chip, be unfavorable for forming the larger encapsulating structure of packaging pin density.
Therefore, the present invention proposes a kind of semiconductor package, comprising: chip, described chip has first surface and second surface, is positioned at the first bottom metal layers of described chip first surface; Be positioned at the first columnar electrode on described the first bottom metal layers, expose part the first bottom metal layers around described the first columnar electrode; Be positioned at first diffusion impervious layer on the first bottom metal layers surface that exposes around described the first columnar electrode sidewall surfaces, top surface, the first columnar electrode; Be positioned at the first soldered ball on described the first diffusion impervious layer, described the first soldered ball is wrapped in the surface of described the first columnar electrode top and sidewall at least; The base plate for packaging that is oppositely arranged with the first surface of chip, described base plate for packaging has solder terminal, the position of described solder terminal is corresponding with the position of the first soldered ball, and described flip-chip is on the described base plate for packaging and be positioned at the first soldered ball on the described chip and the interconnection of described solder terminal.
Described the first soldered ball is formed on described the first columnar electrode, so that the spacing between described chip and the base plate for packaging becomes large, can fill the gap between completely described chip and the base plate for packaging when being conducive to follow-up formation encapsulating material fully, avoid existing between chip and the base plate for packaging cavity can affect stability and the reliability of chip; Owing to having the tension force effect between first diffusion impervious layer on described the first soldered ball and the first columnar electrode surface, so that it is less finally to form the size of the first soldered ball; And described the first diffusion impervious layer not only is formed at described the first columnar electrode sidewall surfaces and top surface, also be formed on the first bottom metal layers that exposes around the first columnar electrode, described the first diffusion impervious layer can improve the adhesion on the first columnar electrode and the first bottom metal layers surface, so that described the first columnar electrode is not easy to break away from from the first surface of chip, guaranteed the stability of semiconductor package.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subjected to the restriction of following public implementation.
The embodiment of the invention provides a kind of formation method of semiconductor package, please refer to Fig. 2 to Figure 15, is the structural representation of the forming process of described semiconductor package.
Concrete, please refer to Fig. 2, chip 100 is provided, described chip 100 has first surface 105 and second surface 106, and the first surface 105 of described chip 100 has pad 101, forms the insulating barrier 110 that exposes described pad 101 on described chip 100 surfaces.
Described chip 100 is wherein a kind of of silicon base, germanium substrate, silicon-on-insulator substrate, be formed with semiconductor device (not shown) and metal interconnect structure (not shown) etc. in the described chip 100, described semiconductor device and described pad can be positioned at the surface, the same side of chip, also can be positioned at the different side surfaces of chip.When described semiconductor device is positioned at the different side surface of chip from described pad, utilize the silicon through hole that runs through described chip that pad is connected with semiconductor device electricity.In the present embodiment, described semiconductor device and pad 101 are positioned at the first surface 105 of described chip, and described semiconductor device is connected with pad 101 electricity, utilize described pad 101 that the circuit structure in the chip is electrically connected with external circuit.
In the present embodiment, the plating seed layer that is positioned at bond pad surface of described pad 101 and follow-up formation consists of metal interconnecting layer.The first follow-up columnar electrode is formed on the described pad.The material of described pad 101 is aluminium, copper, gold or silver-colored etc., and the semiconductor device in the described chip utilizes first columnar electrode, the first soldered ball of described pad 101 and follow-up formation etc. to be connected with external circuit.After forming described pad 101, form insulation material layer at described chip 100 and pad 101 surfaces, and described insulation material layer is carried out etching, expose described pad 101, form insulating barrier 110.Described insulating barrier 110 is silicon oxide layer, silicon nitride layer or polyimide resin layer, benzoxazine resin bed one or more layers stacked structure wherein, with the protection chip.In the present embodiment, described insulating barrier 110 is silicon oxide layer.
In other embodiments, can also form passivation layer, described the first passivation layer cover part pad at described surface of insulating layer.Because the pad of the chip of producing from chip manufacturing factory is often larger, so that the size of the columnar electrode that directly forms at described pad is also larger.Therefore can form the first passivation layer at described surface of insulating layer, described the first passivation layer cover part pad is so that the area reducing of the pad that exposes so that the size of follow-up formation columnar electrode is dwindled, helps to form the high encapsulating structure of closeness again.
Please refer to Fig. 3, form plating seed layer 120 at described pad 101 and insulating barrier 110 surfaces, form the second mask layer 130 on described plating seed layer 120 surfaces, run through the second opening 135 of described the second mask layer in the 130 interior formation of described the second mask layer, described the second opening 135 exposes parcel plating Seed Layer 120.
The material of described plating seed layer 120 is the mixture of aluminium, copper, wherein one or more of gold, silver, and the technique that forms described plating seed layer 120 is sputtering technology or physical gas-phase deposition.When the material of described plating seed layer 120 is aluminium, the technique that forms described plating seed layer 120 is sputtering technology, when the material of described plating seed layer 120 is wherein a kind of of copper, gold, silver, the technique that forms described plating seed layer 120 is physical gas-phase deposition.In the present embodiment, the material of described plating seed layer 120 is copper.
In other embodiments, form projection bottom metal (UBM) layer at described pad and surface of insulating layer, described projection bottom metal (UBM) layer is used for as plating seed layer.
In the present embodiment, described pad 101 consists of metal interconnecting layers with the plating seed layer 120 that is positioned at described pad 101, insulating barrier 110 surfaces, and is follow-up at described plating seed layer formation the first columnar electrode and the second columnar electrode.
In other embodiments, in order to improve package quality, the spacing of the final encapsulation solder joint (i.e. the first soldered ball) that forms, position need rationally to arrange, the position of encapsulation solder joint often rule is fixing, for example unification is near the edge of chip, and the limited location of the pad of semiconductor chip connects up in internal circuit, and it is different from arranging of desirable encapsulation solder joint often to arrange in the position of pad, therefore need to utilize again interconnection metal layer with described pad with encapsulate solder joint electricity and be connected.After forming described plating seed layer, form again interconnection metal layer on described plating seed layer surface, follow-up at described again interconnection metal layer surface formation the first columnar electrode and the second columnar electrode.Described pad, the again interconnection metal layer that is positioned at the plating seed layer of described pad and surface of insulating layer and is positioned at described plating seed layer surface consist of metal interconnecting layer.Described again interconnection metal layer can be single layer structure or multiple-level stack structure.Described again interconnection metal layer one end is positioned at the plating seed layer surface on the described pad, the other end is positioned at the plating seed layer surface on the insulating barrier, and the first columnar electrode of follow-up formation, the second columnar electrode are formed on the again interconnection metal layer surface on the described insulating barrier.In other embodiments, the second columnar electrode of follow-up formation also can form described plating seed layer surface.
Therein among embodiment, the concrete technology that forms described again interconnection metal layer is: form the 3rd mask layer on described plating seed layer surface, in described the 3rd mask layer, form the groove that runs through described the 3rd mask layer, utilize electroplating technology in described groove, to form again interconnection metal layer, described again interconnection metal layer one end is positioned at the plating seed layer surface on the described pad, and the other end is positioned at the plating seed layer surface on the insulating barrier.In other embodiments, also can adopt first sputtering technology or physical gas-phase deposition to form aluminum metal layer, copper metal layer or aluminum bronze metal level etc. on described plating seed layer surface, then utilize dry etch process that described aluminum metal layer, copper metal layer or aluminum bronze metal level etc. are carried out etching, form again interconnection metal layer.
The material of described the second mask layer 130 is photoresist, silica, silicon nitride, wherein one or more of amorphous carbon, and in the present embodiment, the material of described the second mask layer 130 is photoresist.Utilize photoetching process to run through the second opening 135 of described the second mask layer 130, described the second opening 135 follow-up columnar electrodes that are used to form in the 130 interior formation of described the second mask layer.In the present embodiment, the size of overlooking the visual angle of described the second opening 135 can greater than the size of described pad 101, also can be equal to or less than the size of described pad 101.
Please refer to Fig. 4, utilize electroplating technology at described the second opening 135(as shown in Figure 3) in form columnar electrode, described columnar electrode comprises the first columnar electrode 141 and the second columnar electrode 142.
The material of described columnar electrode is copper or other suitable metals.The negative electrode of described plating seed layer 120 with the DC power supply of electroplating is connected, the anode of DC power supply is arranged in the aqueous solution of copper sulphate, described chip is immersed in the copper-bath, then lead to direct current, plating seed layer 120 surfaces that expose at described the second opening 135 form the copper post, become columnar electrode.The height of described columnar electrode can be identical with the degree of depth of the second opening 135, also can be lower than the degree of depth of the second opening 135.
In the present embodiment, be divided into the first columnar electrode 141 and the second columnar electrode 142 at described the second opening 135 interior formation columnar electrodes.In the final semiconductor package that forms, described the first columnar electrode is connected with pad electricity, and described the first columnar electrode is connected with solder terminal electricity in the base plate for packaging, so that the circuit in the chip is connected with external circuit by described the first columnar electrode, solder terminal; Described the second columnar electrode and pad, the first columnar electrode electric isolation, and described the second columnar electrode is connected with the first heating panel in the base plate for packaging, the heat that chip surface produces can be transferred to the first heating panel by described the second columnar electrode dispels the heat, improved the heat-sinking capability of semiconductor package, and can the circuit structure of chip not impacted.
In other embodiments, forming columnar electrode in described the second opening can only be the first columnar electrode also, and described chip is electrically connected with base plate for packaging by the first soldered ball of described the first columnar electrode and follow-up formation.
In the present embodiment, described the first columnar electrode 141 is positioned at the first surface 105 submarginal positions of described chip and is positioned on the pad 101, and described the second columnar electrode 142 is positioned at the first surface 105 of described chip near middle position.In other embodiments, also can be positioned at the first surface of chip near middle position, the submarginal position of first surface that described the second columnar electrode is positioned at chip by described the first columnar electrode; Perhaps also can described the first columnar electrode and the second columnar electrode interval arrange, thereby can dispel the heat better.Because described the first columnar electrode is used for chip is connected with base plate for packaging electricity, described the second columnar electrode is transferred to the first heating panel for the heat with chip surface and dispels the heat, and therefore the position of described the first columnar electrode and the second columnar electrode is separate.
In the present embodiment, the altitude range of described the first columnar electrode 141, the second columnar electrode 142 is 4 μ m ~ 100 μ m.Because the first soldered ball and second soldered ball of follow-up formation are formed on the described columnar electrode, so that the spacing between described chip and the base plate for packaging is the total height of columnar electrode and soldered ball, by controlling the height of described columnar electrode, can regulate the spacing between chip and the base plate for packaging, can guarantee that the packed resin material filling of gap energy between chip and the base plate for packaging is full, can reduce as much as possible again the thickness of described semiconductor package.
In embodiments of the present invention, because the first soldered ball of follow-up formation and the second soldered ball form in top and the sidewall surfaces of described columnar electrode, in reflux course, the scolding tin of molten condition has tension force with the diffusion impervious layer surface that is positioned at the columnar electrode surface, so that described scolding tin covers described diffusion impervious layer surface more equably, so that the area of the shared chip of soldered ball on the described columnar electrode is less than the area of the shared chip of soldered ball of prior art formation, be conducive to improve the solder joint closeness, improve packaging density.
Please refer to Fig. 5, remove described the second mask layer 130(as shown in Figure 4).
The technique of removing described the second mask layer 130 is cineration technics.After removing described the second mask layer 130, expose described plating seed layer 120.In the present embodiment, be electroplating technology because subsequent technique forms the technique of diffusion impervious layer and soakage layer, keep plating seed layer 120 in this step.
In other embodiments, when the technique of follow-up formation diffusion impervious layer and soakage layer is chemical plating process, can remove the parcel plating Seed Layer.The technique of removing described plating seed layer comprises: form the 4th mask layer (not shown) on described plating seed layer surface, described the 4th mask layer covers described columnar electrode, take described the 4th mask layer as mask, utilize wet-etching technology or dry etch process to remove the described plating seed layer that exposes, then reserve part plating seed layer around described columnar electrode removes described the 4th mask layer.
In other embodiments, remove described the second mask layer after, utilize dry etch process to return etching and remove the plating seed layer do not covered by columnar electrode.Because plating seed layer is often very thin, and columnar electrode is very thick, by control etch period and etching power, when removing described plating seed layer, can not affect greatly described columnar electrode.
Please refer to Fig. 6, form the first mask layer 150 on described plating seed layer 120 surfaces, described the first mask layer 150 has the first opening 155 corresponding to the position of the first columnar electrode 141, the second columnar electrode 142, the size of described the first opening 155 is greater than the size of described the first columnar electrode 141, the second columnar electrode 142, and has the gap between described the first opening 155 sidewalls and the first columnar electrode 141, the second columnar electrode 142 sidewalls.
The material of described the first mask layer 150 is photoresist, silica, silicon nitride, wherein one or more of amorphous carbon, and in the present embodiment, described the first mask layer 150 is photoresist layer.Utilize photoetching process in described photoresist layer, to form the first opening 155.Owing to having the gap between the sidewall of described the first opening 155 and the first columnar electrode 141, the second columnar electrode 142 sidewalls, so that the follow-up plating seed layer surface that can expose on every side below sidewall, top and first columnar electrode of described the first columnar electrode forms the first diffusion impervious layer, the plating seed layer surface that exposes around below sidewall, top and second columnar electrode of described the second columnar electrode forms the second diffusion impervious layer, so that the first diffusion impervious layer that forms, the section shape of the second diffusion impervious layer are " several " font.In other embodiments, described columnar electrode below does not expose plating seed layer, and described columnar electrode covers remaining plating seed layer surface fully, so that follow-uply can only form diffusion impervious layer at sidewall and the top of described columnar electrode.
Please refer to Fig. 7, plating seed layer 120 surfaces that expose at described the first columnar electrode 141, the second columnar electrode 142 sidewall surfaces, top surface, the first opening 155 form diffusion impervious layer, wherein, described the first columnar electrode 141 surfaces form the first diffusion impervious layer 161, and described the second columnar electrode 142 surfaces form the second diffusion impervious layer 162.
Because directly contacting to react with the tin in the soldered ball, the copper in the columnar electrode forms the tin copper interface alloy cpd of ε-phase, contracting tin or Non-Dewetting easily occur in described tin copper interface alloy cpd surface, thereby so that whole soldered ball easily come off from the top surface of columnar electrode.Therefore the embodiment of the invention forms diffusion impervious layer on the columnar electrode surface, and the copper in the prevention columnar electrode and the tin in the soldered ball react and forms the tin copper interface alloy cpd of ε-phase.In the present embodiment, described the first diffusion impervious layer 161 and the second diffusion impervious layer 162 are nickel dam.Described nickel dam can stop the copper in the columnar electrode be diffused in the soldered ball with soldered ball in tin react and form the tin copper interface alloy cpd of ε-phase, so that described the first soldered ball, the second soldered ball are not easy to come off from the columnar electrode top surface, and described nickel dam can avoid the columnar electrode surface that oxidation occurs, and affects conducting resistance.In the present embodiment, the technique that forms described the first diffusion impervious layer 161, the second diffusion impervious layer 162 is chemical plating process.In other embodiments, the technique that forms described diffusion impervious layer also can be electroplating technology.
Because chemical plating and plating are to form coating in the metal surface, in the present embodiment, described nickel dam is at described the first columnar electrode 141, the second columnar electrode 142 sidewalls and top surface, plating seed layer 120 surfaces that the first opening 155 exposes form, so that described the first diffusion impervious layer 161, the section shape of the second diffusion impervious layer 162 is " several " font, being parallel to bottom pad 101 surface and being connected with plating seed layer 120 of described diffusion impervious layer, so that the section shape of the soakage layer of follow-up formation also is " several " font, so that the soldered ball of follow-up formation not only can be positioned at the top surface of described columnar electrode, sidewall surfaces, also can be positioned at the diffusion impervious layer surface on the described plating seed layer 120, three Surface Contacts of described soldered ball and diffusion impervious layer, improved the adhesion between soldered ball and the columnar electrode, suppress soldered ball up and down or double swerve, so that soldered ball is not easy to come off, improved the reliability of encapsulating structure.And because the section shape of diffusion impervious layer is " several " font, being parallel to bottom pad 101 surface and being connected with plating seed layer 120 of described diffusion impervious layer, the upper end of described diffusion impervious layer covers described columnar electrode sidewall and top surface, utilize described diffusion impervious layer can improve adhesion between columnar electrode and the plating seed layer 120, so that described columnar electrode is not easy from plating seed layer 120 sur-face peelings.
Please refer to Fig. 8, form soakage layer on described the first diffusion impervious layer 161, the second diffusion impervious layer 162 surfaces, wherein, described the first diffusion impervious layer 161 surfaces form the first soakage layer 171, and described the second diffusion impervious layer 162 surfaces form the second soakage layer 172.
In the present embodiment, the material of described the first soakage layer 171, the second soakage layer 172 comprises wherein a kind of of gold element, silver element, phosphide element or tin element at least, such as gold layer, silver layer, tin layer, sn-ag alloy layer, tin-indium alloy layer etc., the technique that forms described the first soakage layer 171, the second soakage layer 172 is chemical plating process or electroplating technology.
Because nickel also is easier to react with airborne oxygen, and the soakage layer with gold element, silver element, phosphide element or tin element is not easy to react with airborne oxygen, form described soakage layer on described nickel dam surface, can avoid forming oxide layer on the nickel dam surface, and scolding tin has better wettability on the soakage layer surface with gold element, silver element, phosphide element or tin element, so that the soldered ball that follow-up backflow forms afterwards and columnar electrode have stronger adhesion, described soldered ball is not easy to peel off.
Gold, silver, copper have lower resistance, described soakage layer in subsequent technique can to a certain degree with soldered ball, the counterdiffusion of diffusion impervious layer phase, form alloy-layer, the described alloy-layer that contains gold, silver, copper can effectively reduce the interconnection resistance of encapsulating structure.
In the present embodiment, described the first soakage layer 171, the second soakage layer 172 are for electroplating the tin layer that forms, and the electroplate liquid of electrotinning layer comprises every liter of sodium stannate 40 ~ 60 gram, every liter of NaOH 10 ~ 16 gram, every liter of sodium acetate 20 ~ 30 gram, bath temperature is 70 ~ 85 degrees centigrade.Because main component is tin in the soldered ball, the composition of soldered ball and described tin layer is roughly the same, and lower behind the fusing point of scolding tin and tin layer, in follow-up reflux technique, mutually diffusion after being positioned at soldered ball on the columnar electrode and described tin layer and dissolving, form an integral body, because the cross-section structure of described tin layer is " several " font, the final cross-section structure shape of described soldered ball also is " several " font, described soldered ball is wrapped in described columnar electrode top surface, soakage layer surface on the surface of sidewall and the described plating seed layer, described soldered ball is not easy to shake, and has improved the reliability of soldered ball.
In other embodiments, also can not form described soakage layer, form soldered ball on described diffusion impervious layer surface.
Please refer to Fig. 9, remove described the first mask layer 150(and please refer to Fig. 8), the described plating seed layer 120(that exposes be please refer to Fig. 8) carry out etching, form the first bottom metal layers 121 and the second bottom metal layers 122.
In the present embodiment, described metal interconnecting layer comprises pad 101 and is positioned at the plating seed layer 120 on described pad 101, insulating barrier 110 surfaces, after described plating seed layer 120 carried out etching, described metal interconnecting layer was divided into the first bottom metal layers 121 and the second bottom metal layers 122.Described the first bottom metal layers 121 comprises that pad 101(please refer to Fig. 8) please refer to Fig. 8 with the parcel plating Seed Layer 120(that is connected with pad electricity), and described the first columnar electrode 141 is positioned at described the first bottom metal layers 121 surfaces.Described the second bottom metal layers 122 comprises the parcel plating Seed Layer 120 with pad 101 electric isolation, and described the second columnar electrode 142 is positioned at described the second bottom metal layers 122 surfaces.
In other embodiments, when described metal interconnecting layer comprises pad, is positioned at the plating seed layer of described pad and surface of insulating layer and is positioned at the again interconnection metal layer on described plating seed layer surface, etching is removed part again interconnection metal layer and parcel plating Seed Layer, and described metal interconnecting layer is divided into the first bottom metal layers and the second bottom metal layers.Described the first bottom metal layers comprises pad, be positioned at pad is connected the parcel plating Seed Layer and is connected described parcel plating Seed Layer surface and is connected with pad electricity with surface of insulating layer again interconnection metal layer, and described the first columnar electrode to be positioned at described the first bottom metal layers surperficial.Described the second bottom metal layers comprises the parcel plating Seed Layer and the again interconnection metal layer that is positioned at described parcel plating Seed Layer surface with the pad electric isolation, and described the second columnar electrode is positioned at described the second bottom metal layers surface.
The technique of removing described the first mask layer 150 is cineration technics.
Remove the described plating seed layer that exposes, the wiring metal layer process is again: described plating seed layer or again interconnection metal layer surface form the 5th mask layer (not shown), described the 5th mask layer covers described the first columnar electrode and the second columnar electrode, take described the 5th mask layer as mask, utilize wet-etching technology or dry etch process to remove the described plating seed layer that exposes, interconnection metal layer again, then remove described the 5th mask layer.In other embodiments, remove the described plating seed layer that exposes, the technique of interconnection metal layer is again: after removing described the first mask layer, utilize dry etch process to return etching and remove the plating seed layer that is not covered by columnar electrode.Because plating seed layer is often very thin, and the diffusion impervious layer on the columnar electrode or soakage layer are thicker, by control etch period and etching power, when removing described plating seed layer, can not affect greatly described diffusion impervious layer or soakage layer.
Among other embodiment, after etching is removed the parcel plating Seed Layer, can also be at described insulating barrier and interconnection metal layer surface formation passivation layer again, described passivation layer exposes described columnar electrode, utilize described passivation layer with described chip and extraneous electric insulation, the steam insulation.The material of described passivation layer is silicon oxide layer, silicon nitride, silicon oxynitride layer, polyimides, epoxy resin, phenolic resins, wherein one or more of benzoxazine resin.In other embodiments, also can form first soldered ball, form again described passivation layer.
Please refer to Figure 10, soakage layer surface on described columnar electrode forms soldered ball, wherein, the first soakage layer 171 surfaces on described the first columnar electrode 141 form the first soldered ball 191, and the second soakage layer 172 surfaces on described the second columnar electrode 142 form the second soldered ball 192.
Form described soldered ball the first soldered ball 191, the technique of the second soldered ball 192 comprises that solder(ing) paste forms technique and two steps of reflow soldering process, utilize first solder(ing) paste to form technique solder(ing) paste is formed at described the first columnar electrode 141, the second columnar electrode 142 surfaces, the recycling reflux technique refluxes described solder(ing) paste, so that being wrapped in, the first soldered ball 191 that forms is positioned at described the first columnar electrode 141 tops, the first soakage layer 171 surfaces on the surface of sidewall and the plating seed layer, the second soldered ball 192 are wrapped in and are positioned at described the second columnar electrode 142 tops, the second soakage layer 172 surfaces on the surface of sidewall and the plating seed layer.Wherein, described scolder is tin, tin lead mixture or other ashbury metal etc., solder(ing) paste forms technique and comprises that screen painting tin cream, spot welding form the tin ball, chemical plating forms the tin layer, electroplates formation tin layer etc., and reflow soldering process comprises ultrasonic wave reflow soldering process, hot air type reflow soldering process, infrared ray reflow soldering process, laser reflow soldering process, gas phase reflow soldering process etc.The known technology that described solder(ing) paste formation technique and two steps of reflow soldering process are those skilled in the art, therefore not to repeat here.
Because the surface energy of described soakage layer is larger, wettability is better, in reflux technique, scolding tin not only can be positioned at the top of described columnar electrode, also can flow to sidewall and the sidewall bottom of described columnar electrode, and by the amount of the described solder(ing) paste of control, can also be so that described the first soldered ball 191 cover the first soakage layer 171 surfaces on the plating seed layer, described the second soldered ball 192 covers the second soakage layer 172 surfaces on the plating seed layer.Because the soldered ball of the embodiment of the invention and the contact-making surface of columnar electrode comprise top planes and sidewall cambered surface at least, so that external force is when stirring described soldered ball 192, soldered ball is not easy from the columnar electrode sur-face peeling.
In other embodiments, before chip package is to the base plate for packaging, also needs described chip to carry out attenuate, cutting and be divided into independently the techniques such as chip unit.
Please refer to Figure 11, base plate for packaging 200 is provided, described base plate for packaging 200 has solder terminal 210 and the first heating panel 220, the position of described solder terminal 210 is corresponding with the position of the first soldered ball 191, the position of described the first heating panel 220 is corresponding with the position of described the second soldered ball 192, with described chip 100 upside-down mountings to described base plate for packaging 200, be positioned at the first soldered ball 191 and described solder terminal 210 interconnection on the described chip 100, be positioned at the second soldered ball 192 and 220 interconnection of described the first heating panel on the described chip 100.
Described base plate for packaging 200 corresponding with chip 100, in the present embodiment, because described chip 100 has the first columnar electrode 141 and the second columnar electrode 142, described base plate for packaging 200 correspondences have solder terminal 210 and the first heating panel 220.The material of described the first heating panel 220 is the good metal material of heat dispersion, such as copper, aluminium etc.The submarginal position of first surface that described the first soldered ball is positioned at described chip, described the second soldered ball is positioned at the first surface of chip near middle position, corresponding, described solder terminal is positioned at the submarginal position of base plate for packaging, and described the first heating panel is positioned at the centre position of base plate for packaging.In other embodiments, the position of described solder terminal and the first heating panel also can arrange corresponding to the first soldered ball and second soldered ball of chip.
The quantity of described the first heating panel 220 is one or more.In the present embodiment, middle part and several the second soldered balls 192 that described the first heating panel 220 is positioned at described base plate for packaging 200 all are bonded on same the first heating panel 220, in other embodiments, also but one or several second soldered ball utilizes described the first heating panel to dispel the heat corresponding to first heating panel.Because the pyrotoxin of chip 100 is positioned at the first surface 105 that is covered with circuit structure, and the packed resin material parcel of the chip of prior art, radiating effect is not good, the embodiment of the invention utilizes described the second columnar electrode 142 and the second soldered ball 192 that the transfer of heat that described first surface 105 produces is dispelled the heat to the first heating panel, can the Effective Raise radiating efficiency.
Described the first heating panel 220 be shaped as regular figure, such as square, rectangle, triangle etc. also can be irregular figure.In order to improve heat-sinking capability, the first heating panel 220 can arrange in the position that is not formed with arbitrarily solder terminal 210, therefore, described the first heating panel 220 can be to concentrate to distribute and base plate for packaging centre position or marginal position, also can be to disperse to distribute, described the first heating panel 220 and solder terminal 210 intervals arrange.
In other embodiments, because the height of described columnar electrode is larger, if the negligible amounts of described the first columnar electrode, anti-extrusion ability is lower, may cause the first columnar electrode to occur bending and deformation.Therefore by increasing the quantity of described columnar electrode, and the columnar electrode that part does not need to connect for circuit can increase the anti-extrusion ability in chip package and the transportation as the second columnar electrode, avoids columnar electrode to occur bending and deformation or ruptures.
Described base plate for packaging 200 is a kind of in resin substrate, ceramic substrate, glass substrate, silicon substrate, metal substrate, metal framework and the alloy framework.
In the present embodiment, described base plate for packaging 200 is metal framework.In the present embodiment, described solder terminal 210 and the first heating panel 220 are positioned at described base plate for packaging 200 and run through described base plate for packaging 200, described solder terminal 210 surfaces and the first heating panel 220 surfaces that are positioned at the first surface 201 of base plate for packaging 200 interconnect respectively at the first soldered ball 191 and the second soldered ball 192, follow-up when mounting described semiconductor package on the pcb board, the interconnected on solder terminal 210 surfaces that utilize the second surface 202 that is positioned at base plate for packaging 200 and the pcb board.Described semiconductor package mount the Area Ratio conventional package structure of occupying pcb board less, and the aspect ratio conventional package structure of encapsulating structure is lower owing to not needing additionally to form pin, so that the final electronic product that forms can be more and more thinner.
In other embodiments, described base plate for packaging also can not have the first heating panel, corresponding, described chip does not have the first columnar electrode, utilizes described the first columnar electrode with the first soldered ball described chip to be connected with the solder terminal of base plate for packaging.
In other embodiments, the solder terminal of described base plate for packaging also can be positioned at the first surface of described base plate for packaging, the first surface of described base plate for packaging also has the pin that is electrically connected with described solder terminal, utilizes described pin that base plate for packaging is connected with pcb board.
Please refer to Figure 12, between described chip 100 and base plate for packaging 200, form potting resin materials 300 with described chip 100 surfaces, base plate for packaging 200 surfaces.
In the present embodiment, because the spacing between described chip 100 and the base plate for packaging 200 is larger, can utilize traditional potting resin material 300 direct gaps and the described chip of covering 100 surfaces, base plate for packaging 200 surfaces of filling between described chip 100 and the base plate for packaging 200, only need a step plastic package process, technique is simple, and cost is lower.In the present embodiment, described potting resin material 300 materials are epoxy resin.In other embodiments, described potting resin material can also be other suitable resin materials that is used for semiconductor packages.
In other embodiments, can also between described chip and base plate for packaging, fill first filler of the full end, form the potting resin material at described chip and base plate for packaging surface again.Filler of the described end is liquid siliceous epoxide resin material, so that do not have the space between described chip and the base plate for packaging, has guaranteed the reliability of chip.
In other embodiments, please refer to Figure 13, described base plate for packaging 200 can also have opening 205, described opening 205 is the shape of falling T, opening size near base plate for packaging first surface 201 is less, and the opening size that is positioned at base plate for packaging second surface 202 is larger, and the full potting resin material of described opening 205 interior fillings or end filler, so that described potting resin material or end filler be not easy to peel off from base plate for packaging 200, thereby chip 100 is not easy to peel off from base plate for packaging.
In the present embodiment, described potting resin material 300 covers the second surface 106 of described chip 100.In other embodiments, please refer to Figure 14, described potting resin material 300 exposes the second surface 106 of described chip 100, only covers sidewall surfaces and base plate for packaging 200 surfaces of described chip 100, utilize the second surface of described chip to dispel the heat, be conducive to improve radiating effect.
In other embodiments, please refer to Figure 15, can also utilize silver slurry thermal paste to be pasted with the second heating panel 400 at the second surface 106 of described chip 100, because the area of described the second heating panel 400 greater than the area of described chip 100, is conducive to improve the heat-sinking capability of semiconductor structure.The material of described the second heating panel 400 is the good metal material of heat dispersion, such as copper, aluminium etc.And described chip is by described the second heating panel and potting resin material and external insulation, the impact that can avoid extraneous electric charge, steam that the electrical property the subject of knowledge and the object of knowledge of chip is caused.
According to above-mentioned formation method, the embodiment of the invention also provides semiconductor package, and wherein a kind of semiconductor package please refer to Figure 12, comprising: chip 100, and described chip 100 has first surface 105 and second surface 106; Be positioned at the first bottom metal layers 121 of described chip first surface 105, be positioned at the first columnar electrode 141 on described the first bottom metal layers 121, expose part the first bottom metal layers 121 around described the first columnar electrode 141, be positioned at first diffusion impervious layer 161 on the first bottom metal layers 121 surfaces that expose around described the first columnar electrode 141 sidewall surfaces, top surface, the first columnar electrode 141; Be positioned at first soakage layer 171 on described the first diffusion impervious layer 161 surfaces, be positioned at the first soldered ball 191 on described the first soakage layer 171, described the first soldered ball 191 is wrapped in the surface of described the first columnar electrode 141 tops, sidewall and is positioned at the first soakage layer 171 surfaces on the first bottom metal layers 121 that exposes around the first columnar electrode 141; Be positioned at the second bottom metal layers 122 of described chip first surface 105, be positioned at the second columnar electrode 142 on described the second bottom metal layers 122, expose part the second bottom metal layers 122 around described the second columnar electrode 142, be positioned at second diffusion impervious layer 162 on the second bottom metal layers 122 surfaces that expose around described the second columnar electrode 142 sidewall surfaces, top surface, the second columnar electrode 142; Be positioned at second soakage layer 172 on described the second diffusion impervious layer 162 surfaces, be positioned at the second soldered ball 192 on described the second soakage layer 172, described the second soldered ball 192 is wrapped in the surface of described the second columnar electrode 142 tops, sidewall and is positioned at the second soakage layer 172 surfaces on the second bottom metal layers 122 that exposes around the second columnar electrode 142; The base plate for packaging 200 that is oppositely arranged with the first surface 105 of described chip 100, described base plate for packaging 200 has solder terminal 210 and the first heating panel 220, the position of described solder terminal 210 is corresponding with the position of the first soldered ball 191, the position of described the first heating panel 220 is corresponding with the position of the second soldered ball 192, described chip 100 upside-down mountings are on described base plate for packaging 200, be positioned at the first soldered ball 191 and described solder terminal 210 interconnection on the described chip 100, be positioned at the second soldered ball 192 and 220 interconnection of described the first heating panel on the described chip 100; Between described chip 100 and package substrates 200 and cover the potting resin material 300 on described chip 100, package substrates 200 surfaces.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.

Claims (17)

1. a semiconductor package is characterized in that, comprising: chip, and described chip has first surface and second surface, is positioned at the first bottom metal layers of described chip first surface; Be positioned at the first columnar electrode on described the first bottom metal layers, expose part the first bottom metal layers around described the first columnar electrode; Be positioned at first diffusion impervious layer on the first bottom metal layers surface that exposes around described the first columnar electrode sidewall surfaces, top surface, the first columnar electrode; Be positioned at the first soldered ball on described the first diffusion impervious layer, described the first soldered ball is wrapped in the surface of described the first columnar electrode top and sidewall at least; The base plate for packaging that is oppositely arranged with the first surface of chip, described base plate for packaging has solder terminal, the position of described solder terminal is corresponding with the position of the first soldered ball, and described flip-chip is on the described base plate for packaging and be positioned at the first soldered ball on the described chip and the interconnection of described solder terminal.
2. semiconductor package as claimed in claim 1, it is characterized in that, also comprise: the second bottom metal layers that is positioned at described chip first surface, described the second bottom metal layers and the first bottom metal layers electric isolation, be positioned at second columnar electrode on described the second bottom metal layers surface, expose part the second bottom metal layers around described the second columnar electrode; Be positioned at second diffusion impervious layer on the second bottom metal layers surface that exposes around described the second columnar electrode sidewall surfaces, top surface, the second columnar electrode; Be positioned at the second soldered ball on described the second diffusion impervious layer, described the second soldered ball is wrapped in the surface of described the second columnar electrode top and sidewall at least; Be positioned at the first heating panel of described base plate for packaging, the position of described the first heating panel is corresponding with the position of the second soldered ball, and described the second soldered ball and the interconnection of described the first heating panel.
3. semiconductor package as claimed in claim 2, it is characterized in that, described solder terminal is positioned at the submarginal position of base plate for packaging, described the first heating panel is positioned at the centre position of base plate for packaging, corresponding, the submarginal position of first surface that described the first soldered ball is positioned at described chip, described the second soldered ball are positioned at the first surface of chip near middle position.
4. semiconductor package as claimed in claim 2 is characterized in that, the quantity of described the first heating panel is one or more, described the first heating panel be shaped as regular figure or irregular figure.
5. semiconductor package as claimed in claim 4 is characterized in that, when described the first heating panel was polylith, described the first heating panel distributed for concentrating to distribute or disperse.
6. semiconductor package as claimed in claim 1 is characterized in that, described base plate for packaging is a kind of in resin substrate, ceramic substrate, glass substrate, silicon substrate, metal substrate, metal framework and the alloy framework.
7. semiconductor package as claimed in claim 1 or 2, it is characterized in that, described the first soldered ball also covers first diffusion impervious layer on described the first bottom metal layers surface, and described the second soldered ball also covers second diffusion impervious layer on described the second bottom metal layers surface.
8. semiconductor package as claimed in claim 1 or 2 is characterized in that, described the first diffusion impervious layer, the second diffusion impervious layer are nickel dam.
9. semiconductor package as claimed in claim 1 or 2 is characterized in that, also comprises, is positioned at first soakage layer on described the first diffusion impervious layer surface, and described the first soldered ball is formed at described the first soakage layer surface; Be positioned at second soakage layer on described the second diffusion impervious layer surface, described the second soldered ball is formed at described the second soakage layer surface.
10. semiconductor package as claimed in claim 9 is characterized in that, the material of described the first soakage layer, the second soakage layer comprises a kind of in gold element, silver element, phosphide element and the tin element at least.
11. semiconductor package as claimed in claim 1 or 2 is characterized in that, described the first bottom metal layers comprises pad and is positioned at the plating seed layer of described bond pad surface, is formed with the first columnar electrode on described the first bottom metal layers; Described the second bottom metal layers comprises the plating seed layer that is positioned at described chip first surface, is formed with the second columnar electrode on described the second bottom metal layers.
12. semiconductor package as claimed in claim 1 or 2, it is characterized in that, described the first bottom metal layers comprises pad, be positioned at the plating seed layer of described bond pad surface and electrical connection and be positioned at the again interconnection metal layer on described plating seed layer surface, is formed with the first columnar electrode on described the first bottom metal layers; Described the second bottom metal layers is the plating seed layer that is positioned at described chip first surface, perhaps comprise and the plating seed layer that is positioned at described chip first surface and the again interconnection metal layer that is positioned at described plating seed layer surface are formed with the second columnar electrode on described the second bottom metal layers.
13. semiconductor package as claimed in claim 1 is characterized in that, also comprises: the potting resin material on the end filler between described chip and package substrates and the described chip of covering, package substrates surface.
14. semiconductor package as claimed in claim 1 is characterized in that, also comprises: between described chip and package substrates and cover the potting resin material on described chip, package substrates surface.
15. such as claim 13 or 14 described semiconductor packages, it is characterized in that, described potting resin material exposes the second surface of described chip.
16. such as claim 13 or 14 described semiconductor packages, it is characterized in that, also comprise, with bonding the second heating panel of described chip second surface, described potting resin material exposes described the second heating panel surface.
17. semiconductor package as claimed in claim 1 or 2 is characterized in that, the altitude range of described the first columnar electrode and the second columnar electrode is 4 μ m ~ 100 μ m.
CN201210444097.6A 2012-11-08 2012-11-08 Semiconductor package Active CN102915978B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201210444097.6A CN102915978B (en) 2012-11-08 2012-11-08 Semiconductor package
US14/074,687 US9293338B2 (en) 2012-11-08 2013-11-07 Semiconductor packaging structure and method
US15/014,929 US9431325B2 (en) 2012-11-08 2016-02-03 Semiconductor packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210444097.6A CN102915978B (en) 2012-11-08 2012-11-08 Semiconductor package

Publications (2)

Publication Number Publication Date
CN102915978A true CN102915978A (en) 2013-02-06
CN102915978B CN102915978B (en) 2016-02-03

Family

ID=47614292

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210444097.6A Active CN102915978B (en) 2012-11-08 2012-11-08 Semiconductor package

Country Status (1)

Country Link
CN (1) CN102915978B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413769A (en) * 2013-08-27 2013-11-27 南通富士通微电子股份有限公司 Wafer level chip size packaging method
CN104465571A (en) * 2014-12-16 2015-03-25 南通富士通微电子股份有限公司 Wafer packaging structure
CN107993994A (en) * 2017-12-29 2018-05-04 睿力集成电路有限公司 Semiconductor package and its manufacture method
CN110649155A (en) * 2018-06-27 2020-01-03 台湾积体电路制造股份有限公司 Semiconductor structure and forming method thereof
WO2021103489A1 (en) * 2019-11-29 2021-06-03 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor
CN114823573A (en) * 2022-06-24 2022-07-29 威海市泓淋电力技术股份有限公司 Heat dissipation type packaging structure and forming method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726079A (en) * 1996-06-19 1998-03-10 International Business Machines Corporation Thermally enhanced flip chip package and method of forming
CN1697148A (en) * 2004-05-12 2005-11-16 富士通株式会社 Semiconductor device and method of manufacturing the semiconductor device
JP2006108182A (en) * 2004-09-30 2006-04-20 Taiyo Yuden Co Ltd Semiconductor device, its mounter and its manufacturing method
CN1768434A (en) * 2003-03-28 2006-05-03 吉尔科有限公司 LED power package
CN101552253A (en) * 2008-04-02 2009-10-07 旭德科技股份有限公司 Array package substrate
CN102237316A (en) * 2010-04-22 2011-11-09 台湾积体电路制造股份有限公司 Integrated circuit element and forming method of bumping block structure
CN102270590A (en) * 2011-09-01 2011-12-07 苏州晶方半导体科技股份有限公司 Wafer level package structure and method
CN202917468U (en) * 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 Semiconductor packaging structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726079A (en) * 1996-06-19 1998-03-10 International Business Machines Corporation Thermally enhanced flip chip package and method of forming
CN1768434A (en) * 2003-03-28 2006-05-03 吉尔科有限公司 LED power package
CN1697148A (en) * 2004-05-12 2005-11-16 富士通株式会社 Semiconductor device and method of manufacturing the semiconductor device
JP2006108182A (en) * 2004-09-30 2006-04-20 Taiyo Yuden Co Ltd Semiconductor device, its mounter and its manufacturing method
CN101552253A (en) * 2008-04-02 2009-10-07 旭德科技股份有限公司 Array package substrate
CN102237316A (en) * 2010-04-22 2011-11-09 台湾积体电路制造股份有限公司 Integrated circuit element and forming method of bumping block structure
CN102270590A (en) * 2011-09-01 2011-12-07 苏州晶方半导体科技股份有限公司 Wafer level package structure and method
CN202917468U (en) * 2012-11-08 2013-05-01 南通富士通微电子股份有限公司 Semiconductor packaging structure

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413769A (en) * 2013-08-27 2013-11-27 南通富士通微电子股份有限公司 Wafer level chip size packaging method
CN103413769B (en) * 2013-08-27 2016-02-24 南通富士通微电子股份有限公司 Wafer-level chip size package method
CN104465571A (en) * 2014-12-16 2015-03-25 南通富士通微电子股份有限公司 Wafer packaging structure
CN107993994A (en) * 2017-12-29 2018-05-04 睿力集成电路有限公司 Semiconductor package and its manufacture method
CN107993994B (en) * 2017-12-29 2023-07-25 长鑫存储技术有限公司 Semiconductor packaging structure and manufacturing method thereof
CN110649155A (en) * 2018-06-27 2020-01-03 台湾积体电路制造股份有限公司 Semiconductor structure and forming method thereof
CN110649155B (en) * 2018-06-27 2022-11-29 台湾积体电路制造股份有限公司 Semiconductor structure and forming method thereof
US11696510B2 (en) 2018-06-27 2023-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Diffusion layer for magnetic tunnel junctions
WO2021103489A1 (en) * 2019-11-29 2021-06-03 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor
CN114823573A (en) * 2022-06-24 2022-07-29 威海市泓淋电力技术股份有限公司 Heat dissipation type packaging structure and forming method thereof

Also Published As

Publication number Publication date
CN102915978B (en) 2016-02-03

Similar Documents

Publication Publication Date Title
US9431325B2 (en) Semiconductor packaging structure
US7242081B1 (en) Stacked package structure
CN102915978B (en) Semiconductor package
CN102931111B (en) Method for forming semiconductor packaging structures
CN101228625B (en) Semiconductor package with plated connection
US20100270667A1 (en) Semiconductor package with multiple chips and substrate in metal cap
KR20160019739A (en) Semiconductor Devices and Package Substrates Having Pillars, and Semiconductor Packages and Package Stack Structures Having the Same
CN103681607A (en) Semiconductor device and method of manufacturing semiconductor device
TWI398933B (en) Package structure of integrated circuit device and manufacturing method thereof
CN109390306A (en) Electronic package
CN102270590A (en) Wafer level package structure and method
US20080224276A1 (en) Semiconductor device package
CN105448755A (en) A packaging method for copper column salient points and a packaging structure
CN202917468U (en) Semiconductor packaging structure
CN202917474U (en) Semiconductor package structure
US7846829B2 (en) Stacked solder balls for integrated circuit device packaging and assembly
CN102931100A (en) Formation method of semiconductor packaging structure
CN102931097A (en) Method for forming semiconductor packaging structures
CN104681499B (en) Package stack structure and method for fabricating the same
CN103137581B (en) Semiconductor device with conductive bump, package structure and manufacturing method
US20120211257A1 (en) Pyramid bump structure
CN102945836B (en) Semiconductor package
CN102931159B (en) Semiconductor package
CN212303700U (en) System-in-package structure of LED chip
CN111162158B (en) RGB chip flip packaging structure and preparation method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee
CP03 Change of name, title or address

Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288

Patentee after: Tongfu Microelectronics Co., Ltd.

Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288

Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong