CN102931100B - The formation method of semiconductor package - Google Patents
The formation method of semiconductor package Download PDFInfo
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- CN102931100B CN102931100B CN201210444526.XA CN201210444526A CN102931100B CN 102931100 B CN102931100 B CN 102931100B CN 201210444526 A CN201210444526 A CN 201210444526A CN 102931100 B CN102931100 B CN 102931100B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
A formation method for semiconductor package, comprising: provide chip, and described chip surface has metal interconnect structure, forms the insulating barrier exposing described metal interconnect structure at described chip surface; Columnar electrode is formed on metal interconnect structure surface; Diffusion impervious layer is formed at described columnar electrode sidewall surfaces, top surface; Form passivation layer at described surface of insulating layer, described passivation layer covers described columnar electrode; Described passivation layer is ground, until expose described diffusion impervious layer; Soldered ball is formed on the described diffusion impervious layer surface exposed.Expose described in described soldered ball is positioned at diffusion impervious layer surface, diffusion impervious layer make columnar electrode and soldered ball isolated, can not form tin copper interface alloy cpd, described soldered ball is not easy to come off from columnar electrode.
Description
Technical field
The present invention relates to semiconductor packaging, particularly a kind of formation method of semiconductor package of high reliability.
Background technology
In current semicon industry, Electronic Packaging has become an importance of industry development.Through the development of encapsulation technology decades, traditional periphery cloth line style packaged type and BGA Package technology more and more cannot meet current high density, undersized encapsulation requirement, wafer stage chip packaged type (Wafer-LevelChipScalePackagingTechnology, WLCSP) technology has become the packaged type of current hot topic.
Please refer to Fig. 1, for the cross-sectional view of a kind of encapsulating structure of existing wafer stage chip packaged type, comprising: silicon chip 1, be positioned at the insulating barrier 2 on described silicon chip 1 surface, described insulating barrier 2 has opening, and silicon chip 1 surface that described opening exposes has pad 3; Be positioned at the interconnection metal layer again 4 on described pad 3, insulating barrier 2 surface, described interconnection metal layer again 4 is for redistributing the position of BGA Package solder joint; The copper post 5 on interconnection metal layer 4 surface again described in being positioned at, described copper post 5 is connected with pad 3 by interconnection metal layer 4 again; The sealing material layer 6 be made up of organic resin of interconnection metal layer 4, insulating barrier 2 again described in covering, and the top surface of described sealing material layer 6 flushes with the top surface of described copper post 5, is positioned at the soldered ball 7 of the top surface of described copper post 5.More encapsulating structures about wafer stage chip packaged type and formation process please refer to the american documentation literature that publication number is US2001/0094841A1.
But in above-mentioned encapsulating structure, soldered ball 7 easily comes off from the top surface of described copper post 5, thus causes chip failure.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor package, effectively can improve the adhesion of soldered ball, improves the reliability of semiconductor package.
For solving the problem, technical solution of the present invention provides a kind of formation method of semiconductor package, comprising: provide chip, and described chip surface has metal interconnect structure, forms the insulating barrier exposing described metal interconnect structure at described chip surface; Columnar electrode is formed on metal interconnect structure surface; Diffusion impervious layer is formed at described columnar electrode sidewall surfaces, top surface; Form passivation layer at described surface of insulating layer, described passivation layer covers described columnar electrode; Described passivation layer is ground, until expose described diffusion impervious layer; Soldered ball is formed on the described diffusion impervious layer surface exposed.
Optionally, also comprise: form soakage layer on described diffusion impervious layer surface, after forming passivation layer, described passivation layer is ground, until expose described soakage layer, form soldered ball on the described soakage layer surface exposed.
Optionally, the material of described soakage layer at least comprises the one in gold element, silver element, phosphide element and tin element.
Optionally, described diffusion impervious layer is nickel dam.
Compared with prior art, the present invention has the following advantages:
The embodiment of the present invention forms columnar electrode on described metal interconnect structure surface, forms diffusion impervious layer at described columnar electrode sidewall surfaces, top surface, and the diffusion impervious layer surface at described columnar electrode top forms soldered ball.Expose described in described soldered ball is positioned at diffusion impervious layer surface, diffusion impervious layer make columnar electrode and soldered ball isolated, can not form tin copper interface alloy cpd, described soldered ball is not easy to come off from columnar electrode.
Further, soakage layer is formed on described diffusion impervious layer surface, the soldered ball of follow-up formation has preferably wettability on soakage layer surface, improve the adhesion between soldered ball and soakage layer, and described soakage layer is wrapped in sidewall and the top surface of described columnar electrode, when external force is stirred described soldered ball, described soldered ball is not easy from described soakage layer sur-face peeling.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the semiconductor package of prior art;
Fig. 2 is the schematic flow sheet of the formation method of the semiconductor package of first embodiment of the invention;
Fig. 3 to Figure 13 is the cross-sectional view of the forming process of the semiconductor package of first embodiment of the invention;
Figure 14 to Figure 25 is the cross-sectional view of the forming process of the semiconductor package of second embodiment of the invention.
Embodiment
From in background technology, in the encapsulating structure of prior art, soldered ball easily comes off from the top surface of copper post, thus can cause chip failure.
Inventor finds through research, the main cause of the problems referred to above is caused to be: because the material of described soldered ball mainly comprises tin, after described soldered ball is formed in described copper post surface, in the process of high temperature reflux, tin on the contact surface can react with copper and form tin copper interface alloy cpd (IntermetallicCompound, IMC), along with the raising of tin copper interface alloy cpd thickness, tin atom near contact-making surface in scolding tin can reduce gradually, relative makes lead atom in soldered ball, the ratio of silver atoms increases, so that the flexibility of soldered ball is increased, set intensity reduces, thus whole soldered ball is easily come off from the top surface of copper post, and when described tin can with copper react form tin copper interface alloy cpd time, under initial conditions, described tin can react with copper and form η-phase(Eta phase) Cu
6sn
5, described Cu
6sn
5the weight percent content of middle copper is about 40%, but As time goes on, the copper atom in copper post is constantly diffused in the alloy cpd of tin copper interface, forms ε-phase(Epsilon phase) Cu
3sn, described Cu
3in Sn, the weight percent content of copper rises to and is about 66%, described ε-phase(Epsilon phase) Cu
3the surface energy of Sn is far smaller than η-phase(Eta phase) Cu
6sn
5, easily there is contracting tin or Non-Dewetting in tin copper interface alloy cpd surface, thus whole soldered ball is easily come off from the top surface of copper post.
Therefore, the present invention proposes a kind of formation method of semiconductor package, form diffusion impervious layer at described columnar electrode sidewall surfaces, top surface, after described diffusion impervious layer surface forms passivation layer, described passivation layer is ground, until expose described diffusion impervious layer; Soldered ball is formed on the described diffusion impervious layer surface exposed.Expose described in described soldered ball is positioned at diffusion impervious layer surface, diffusion impervious layer make columnar electrode and soldered ball isolated, can not form tin copper interface alloy cpd, described soldered ball is not easy to come off from columnar electrode.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
First embodiment
First embodiment of the invention provide firstly a kind of formation method of semiconductor package, please refer to Fig. 2, is the schematic flow sheet of the formation method of described semiconductor package, specifically comprises:
Step S101, provides chip, and described chip surface has pad, forms the insulating barrier exposing described pad at described chip surface;
Step S102, forms the first passivation layer at described surface of insulating layer, described first passivation layer cover part pad;
Step S103, forms plating seed layer at described pad and the first passivation layer surface, forms the second mask layer, form the second opening running through described second mask layer in described second mask layer on described plating seed layer surface;
Step S104, utilizes electroplating technology to form columnar electrode in described second opening;
Step S105, removes described second mask layer;
Step S106, the first mask layer is formed on described plating seed layer surface, the position that described first mask layer corresponds to columnar electrode has the first opening, and the size of described first opening is greater than the size of described columnar electrode, and has gap between described first opening sidewalls and columnar electrode sidewall;
Step S107, the plating seed layer surface exposed at described columnar electrode sidewall surfaces, top surface, the first opening forms diffusion impervious layer;
Step S108, forms soakage layer on described diffusion impervious layer surface;
Step S109, the plating seed layer removed described first mask layer He expose, form passivation layer, and described passivation layer covers described columnar electrode in described first passivation layer surface;
Step S110, grinds described passivation layer, until expose described diffusion impervious layer;
Step S111, forms soldered ball on the described diffusion impervious layer surface exposed.
Concrete, please refer to Fig. 3 to Figure 13, is the cross-sectional view of the forming process of the semiconductor package of first embodiment of the invention.
Please refer to Fig. 3, provide chip 100, described chip 100 surface has pad 101, forms on described chip 100 surface the insulating barrier 110 exposing described pad 101.
Described chip 100 is silicon base, germanium substrate, silicon-on-insulator substrate one wherein, semiconductor device (not shown) and metal interconnect structure (not shown) etc. is formed in described chip 100, described semiconductor device and described pad can be positioned at the surface, the same side of chip, also can be positioned at the not same surface of chip.Described semiconductor device is connected with pad electricity, when described semiconductor device and described pad are positioned at the not same surface of chip, utilizes the silicon through hole running through described chip to be connected with semiconductor device electricity by pad.
In the present embodiment, the plating seed layer being positioned at bond pad surface of described pad 101 and follow-up formation forms metal interconnect structure.Follow-up columnar electrode is formed on described pad 101.The material of described pad 101 is aluminium, copper, gold or silver-colored etc., and described semiconductor device utilizes described pad 101 to be connected with external circuit with the columnar electrode, soldered ball etc. of follow-up formation.After forming described pad 101, form insulation material layer at described chip 100 and pad 101 surface, and described insulation material layer is etched, expose described pad 101, form insulating barrier 110.Described insulating barrier 110 is silicon oxide layer, silicon nitride layer, polyimide resin layer, benzoxazine resin layer one or more layers stacked structure wherein.In the present embodiment, described insulating barrier 110 is silicon oxide layer.
Please refer to Fig. 4, form the first passivation layer 111, described first passivation layer 111 cover part pad 101 on described insulating barrier 110 surface.
Because the pad of the chip produced from chip manufacturing factory is often comparatively large, make the size of the columnar electrode directly formed on described pad also larger.Therefore the first passivation layer 111 can be formed again on described insulating barrier 110 surface, described first passivation layer 111 cover part pad 101, the area of the pad 101 exposed is reduced, the size of follow-up formation columnar electrode is reduced, contribute to forming the high encapsulating structure of closeness.In other embodiments, also can not form described first passivation layer 111, directly form plating seed layer at described insulating barrier and bond pad surface.The material of described first passivation layer can be identical with the material of insulating barrier, also can be different.
Please refer to Fig. 5, plating seed layer 120 is formed at described pad 101 and the first passivation layer 111 surface, the second mask layer 130 is formed on described plating seed layer 120 surface, in described second mask layer 130, form the second opening 135 running through described second mask layer, described second opening 135 exposes parcel plating Seed Layer 120.
The material of described plating seed layer 120 is the mixture of aluminium, copper, gold, silver wherein one or more, and the technique forming described plating seed layer 120 is sputtering technology or physical gas-phase deposition.In other embodiments, form underbump metallization (UBM) layer at described pad and the first passivation layer surface, described underbump metallization (UBM) layer is used for as plating seed layer.
When the material of described plating seed layer 120 is aluminium, the technique forming described plating seed layer 120 is sputtering technology, when the material of described plating seed layer 120 is copper, gold, silver one wherein, the technique forming described plating seed layer 120 is physical gas-phase deposition.In the present embodiment, the material of described plating seed layer 120 is copper.
The material of described second mask layer 130 is photoresist, silica, silicon nitride, amorphous carbon wherein one or more, and in the present embodiment, the material of described second mask layer 130 is photoresist.Utilize photoetching process in described second mask layer 130, form the second opening 135 running through described second mask layer 130, described second opening 135 is follow-up for the formation of columnar electrode.The size of overlooking visual angle of described second opening 135 can be greater than the size of described pad 101, also can be equal to or less than the size of described pad 101.
Please refer to Fig. 6, utilize electroplating technology at described second opening 135(as shown in Figure 5) in formed columnar electrode 140.
The material of described columnar electrode 140 is copper.The negative electrode of described plating seed layer 120 with the DC power supply of plating is connected, the copper anode of DC power supply is immersed in the aqueous solution of copper sulphate, then logical direct current, plating seed layer 120 surface exposed at described second opening 135 forms copper post, becomes columnar electrode 140.The height of described columnar electrode 140 can be identical with the degree of depth of the second opening 135, also can lower than the degree of depth of the second opening 135.
Please refer to Fig. 7, remove described second mask layer 130(as shown in Figure 6).
In the present embodiment, the technique removing described second mask layer 130 is cineration technics.After removing described second mask layer 130, expose described plating seed layer 120.In the present embodiment, the technique forming diffusion impervious layer and soakage layer due to subsequent technique is electroplating technology, retains plating seed layer 120 in this step.
In other embodiments, when the technique of follow-up formation diffusion impervious layer and soakage layer is chemical plating process, remove part plating seed layer.The technique removing described plating seed layer comprises: form the 4th mask layer (not shown) on described plating seed layer surface, described 4th mask layer covers described columnar electrode, with described 4th mask layer for mask, utilize the plating seed layer exposed described in wet-etching technology or dry etch process removal, then remove described 4th mask layer.
In other embodiments, after removing described second mask layer, utilize dry etch process to return etching and remove not by plating seed layer that columnar electrode covers.Because plating seed layer is often very thin, and columnar electrode is very thick, by controlling etch period and etching power, can not affect greatly while the described plating seed layer of removing to described columnar electrode.
Please refer to Fig. 8, the first mask layer 150 is formed on described plating seed layer 120 surface, the position that described first mask layer 150 corresponds to columnar electrode 140 has the first opening 155, the size of described first opening 155 is greater than the size of described columnar electrode 140, and has gap between described first opening 155 sidewall and columnar electrode 140 sidewall.
The material of described first mask layer 150 is photoresist, silica, silicon nitride, amorphous carbon wherein one or more, and in the present embodiment, described first mask layer 150 is photoresist layer.Utilize photoetching process in described photoresist layer, form the first opening 155.Owing to there is gap between the sidewall of described first opening 155 and columnar electrode 140 sidewall, make follow-uply to form diffusion impervious layer at the sidewall of described columnar electrode and top.In the present embodiment, described first opening 155 also exposes the plating seed layer 120 be positioned at around below columnar electrode 140, makes the section shape of the diffusion impervious layer of follow-up formation be " several " font.In other embodiments, do not expose plating seed layer below described columnar electrode, described columnar electrode covers remaining plating seed layer surface completely, makes follow-uply to form diffusion impervious layer at the sidewall of described columnar electrode and top.
Please refer to Fig. 9, plating seed layer 120 surface exposed at described columnar electrode 140 sidewall surfaces, top surface, the first opening 155 forms diffusion impervious layer 160.
Described diffusion impervious layer 160 forms the tin copper interface alloy cpd of ε-phase for stoping the copper in columnar electrode 140 and the tin in soldered ball to react.In the present embodiment, described diffusion impervious layer 160 is nickel dam.Described nickel dam can stop the copper in columnar electrode 140 to be diffused in soldered ball to react with the tin in soldered ball and forms the tin copper interface alloy cpd of ε-phase, and described nickel dam can avoid columnar electrode surface to be oxidized, and affects conducting resistance.Because diffusion impervious layer is between described columnar electrode and soldered ball, make described columnar electrode and soldered ball isolated, form soldered ball when follow-up on described diffusion impervious layer surface, interface can not be formed tin copper interface alloy cpd, described soldered ball is not easy to come off from columnar electrode top surface.In the present embodiment, the technique forming described diffusion impervious layer 160 is chemical plating process.In other embodiments, the technique forming described diffusion impervious layer can be also electroplating technology, and the electroplate liquid of electroless nickel layer comprises nickel sulfamic acid 700 ~ 800 grams often liter, nickel chloride 6 ~ 8 grams often liter, boric acid 35 ~ 45 grams often liter, pH value is 4 ~ 6, and the temperature of plating solution is 45 ~ 55 degrees Celsius.
Because chemical plating and plating form coating in metal surface, in the present embodiment, described nickel dam is at described columnar electrode 140 sidewall and top surface, plating seed layer 120 surface that first opening 155 exposes is formed, the section shape making described diffusion impervious layer 160 is " several " font, described diffusion impervious layer 160 be parallel to bottom pad 101 surface and be connected with plating seed layer 120, the section shape of the soakage layer of follow-up formation is made also to be " several " font, when external force by described soldered ball upwards or left and right is stirred time, the partial wetting layer of " L " shape bottom columnar electrode can suppress soldered ball to move up, and also can improve the adhesion between soldered ball and columnar electrode in the soakage layer part of columnar electrode sidewall, suppress soldered ball up and down or double swerve, soldered ball is made to be not easy to come off, improve the reliability of encapsulating structure.And due to the section shape of diffusion impervious layer 160 be " several " font, described diffusion impervious layer 160 be parallel to bottom pad 101 surface and be connected with plating seed layer 120, the upper end of described diffusion impervious layer 160 covers described columnar electrode 140 sidewall and top surface, utilize described diffusion impervious layer 160 can improve adhesion between columnar electrode 140 and plating seed layer 120, described columnar electrode 140 is not easy from plating seed layer 120 sur-face peeling.
In other embodiments, when in technique before, plating seed layer around described columnar electrode is removed, described diffusion impervious layer is only formed at described columnar electrode sidewall and top surface, make the section shape of described diffusion impervious layer be " ㄇ " font, make the section shape of the soakage layer of follow-up formation also be " ㄇ " font.When external force by described soldered ball upwards or left and right is stirred time, the adhesion between soldered ball and columnar electrode can be improved in the soakage layer part of columnar electrode sidewall, suppression soldered ball is upper and lower, double swerve, makes soldered ball be not easy to come off, improves the reliability of encapsulating structure.
Please refer to Figure 10, form soakage layer 170 on described diffusion impervious layer 160 surface.
In the present embodiment, described soakage layer 170 at least comprises gold element, silver element, phosphide element or tin element one wherein, such as layer gold, silver layer, tin layers, sn-ag alloy layer, tin-indium alloy layer etc., the technique forming described soakage layer 170 is chemical plating process or electroplating technology.
Because nickel is also easier to react with the oxygen in air, and the soakage layer 170 with gold element, silver element, phosphide element or tin element is comparatively not easy to react with the oxygen in air, described soakage layer is formed on described nickel dam surface, can avoid forming oxide layer on nickel dam surface, and soakage layer 170 surface that scolding tin has gold element, silver element, phosphide element or tin element has preferably wettability, the soldered ball formed after making subsequent reflow and columnar electrode have stronger adhesion, and described soldered ball is not easy to peel off.
Gold, silver have lower resistance, described soakage layer in subsequent technique can to a certain degree with soldered ball, the counterdiffusion of diffusion impervious layer phase, form alloy-layer, the described alloy-layer containing gold, silver effectively can reduce the interconnection resistance of encapsulating structure.
In the present embodiment, described soakage layer 170 is the tin layers that plating is formed, and the electroplate liquid of plating tin layers comprises sodium stannate 40 ~ 60 grams often liter, 10 ~ 16 grams often liter, NaOH, sodium acetate 20 ~ 30 grams often liter, and bath temperature is 70 ~ 85 degrees Celsius.
Because main component in soldered ball is tin, soldered ball is roughly the same with the composition of described tin layers, and the fusing point of scolding tin and tin layers is lower, in follow-up reflux technique, be positioned at after soldered ball on columnar electrode and described tin layers are dissolved and can spread mutually, form an entirety, the mechanical strength between soldered ball and described tin layers can be very large, improves the reliability of soldered ball.And when the thickness of described tin layers is larger, the mechanical strength between soldered ball and described tin layers is larger, effectively can improve the reliability of soldered ball.
In other embodiments, also can not form described soakage layer, after formation diffusion impervious layer, remove described first mask layer.
Please refer to Figure 11, remove described first mask layer 150(and please refer to Figure 10) and the plating seed layer 120(that exposes please refer to Figure 10), form passivation layer 180 on described first passivation layer 111 surface, described passivation layer 180 covers described columnar electrode 140.
In the present embodiment, the technique removing described first mask layer 150 is cineration technics.
In the present embodiment, the technique of the plating seed layer 120 exposed described in removal is: on described columnar electrode, form the 5th mask layer (not shown), described 5th mask layer covers described columnar electrode, expose the plating seed layer 120 around columnar electrode, with described 5th mask layer for mask, utilize the plating seed layer exposed described in wet-etching technology or dry etch process removal, then remove described 5th mask layer.
In other embodiments, the technique of the plating seed layer exposed described in removal is: after removing described first mask layer, utilizes dry etch process to return etching and removes not by plating seed layer that columnar electrode covers.Because plating seed layer is often very thin, and diffusion impervious layer on columnar electrode or soakage layer thicker, by controlling etch period and etching power, can not affect greatly described diffusion impervious layer or soakage layer while the described plating seed layer of removing.
The material of described passivation layer 180 is silicon oxide layer, silicon nitride, silicon oxynitride layer, polyimides, epoxy resin, phenolic resins, benzoxazine resin wherein one or more.In the present embodiment, the material of described passivation layer 180 is epoxy resin, utilize spin coating, epoxide resin material is covered soakage layer 170 surface on described first passivation layer 111, columnar electrode 140 by printing coating technique, resin transfer moulding (RTM) technique, Resin Film Infusion (RFI) technique etc., the thickness of described passivation layer 180 is greater than the gross thickness of columnar electrode 140 and diffusion impervious layer 160, soakage layer 170.
Please refer to Figure 12, described passivation layer 180 is ground, until expose described soakage layer 170.
Described grinding technics is mechanical lapping or cmp.
In the present embodiment, described passivation layer 180 is ground, until expose the soakage layer 170 on described columnar electrode 140 top surface, and the soakage layer 170 on described columnar electrode 140 top surface is not polished completely, make in subsequent reflow process, between soakage layer 170 on soldered ball on described columnar electrode 140 and columnar electrode 140 top surface, there is good wettability, make the adhesion between soldered ball and soakage layer 170 and mechanical strength high, the reliability of encapsulating structure is high; And described grinding technics makes the surface of passivation layer 180 smooth, the soldered ball of follow-up formation is positioned at same level height, is conducive to the reliability improving encapsulating structure, and is conducive to encapsulating with other encapsulating structures such as pcb board; And be not polished completely due to the soakage layer 170 on described columnar electrode 140 top surface, the diffusion impervious layer 160 be positioned on columnar electrode 140 top surface is unaffected, thus can prevent the copper in columnar electrode and the tin in soldered ball from forming ε-phase(Epsilon phase) tin copper interface alloy cpd, affect the adhesion between soldered ball and columnar electrode.
In other embodiments, described passivation layer is ground, until expose the diffusion impervious layer being positioned at described columnar electrode surface, follow-up at described diffusion impervious layer surface formation soldered ball, can prevent the copper in columnar electrode and the tin in soldered ball from forming ε-phase(Epsilon phase) tin copper interface alloy cpd, the reliability of the final soldered ball formed also directly forms the reliability of soldered ball on the copper post surface exposed higher than prior art.
Please refer to Figure 13, form soldered ball 190 on described soakage layer 170 surface exposed.
The technique forming described soldered ball 190 comprises solder formation process and reflux technique two steps, first form solder on described soakage layer 170 surface exposed, described solder refluxes by recycling reflux technique, described in the solder on soakage layer 170 surface that exposes form soldered ball 190.Wherein, described solder is tin, tin lead mixture or other ashbury metal etc., solder formation process comprises screen painting tin cream, spot welding forms tin ball, chemical plating forms tin layers, plating forms tin layers etc., and reflow soldering process comprises ultrasonic wave reflow soldering process, hot air type reflow soldering process, infrared ray reflow soldering process, laser reflow Welding, gas phase reflow soldering process etc.Described solder formation process and reflow soldering process two steps are the known technology of those skilled in the art, and therefore not to repeat here.
In the present embodiment, due to described soakage layer 170(tin layers) and the fusing point of solder all lower, be less than 250 degrees Celsius, in reflux course, diffusion mutually after described soakage layer 170 and solder melt, described soakage layer 170 and the final soldered ball formed are combined, and mechanical strength between the two increases greatly.In the present embodiment, section shape due to described soakage layer 170 is " several " font, when external force by described soldered ball upwards or left and right is stirred time, being positioned at soakage layer 170 parallel with chip plane bottom columnar electrode can suppress soldered ball to move up, and also can improve the adhesion between soldered ball and columnar electrode in soakage layer 170 part of columnar electrode sidewall, suppress soldered ball up and down or double swerve, make soldered ball be not easy to come off, improve the reliability of encapsulating structure.
In other embodiments, when the section shape of described diffusion impervious layer is " ㄇ " font, the section shape of soakage layer is also " ㄇ " font.When external force by described soldered ball upwards or left and right is stirred time, the adhesion between soldered ball and columnar electrode can be improved in the soakage layer part of columnar electrode sidewall, suppression soldered ball is upper and lower, double swerve, makes soldered ball be not easy to come off, improves the reliability of encapsulating structure.
According to above-mentioned formation method, the embodiment of the present invention additionally provides a kind of semiconductor package, please refer to Figure 13, specifically comprise: chip 100, described chip 100 surface has pad 101, be positioned at described chip 100 surface and expose the insulating barrier 110 of described pad 101, being positioned at described insulating barrier 110 surface and the first passivation layer 111 of cover part pad 101; Be positioned at the plating seed layer 120 on described pad 101 and part first passivation layer 111 surface; Be positioned at the columnar electrode 140 on described plating seed layer 120 surface, described columnar electrode 140 bottom periphery exposes parcel plating Seed Layer 120; Be positioned at the diffusion impervious layer 160 of described columnar electrode 140 sidewall surfaces, top surface, columnar electrode 140 bottom periphery; Be positioned at the soakage layer 170 on described diffusion impervious layer 160 surface; Be positioned at described first passivation layer 111 surface and the passivation layer 180 of the soakage layer 170 of covering columnar electrode 140 sidewall, described passivation layer 180 surface flushes with soakage layer 170 surface at columnar electrode 140 top; Be positioned at the soldered ball 190 on soakage layer 170 surface at described columnar electrode 140 top.
Second embodiment
Second embodiment of the invention provides the formation method of another kind of semiconductor package, concrete, please refer to Figure 14 to Figure 25, is the cross-sectional view of the forming process of the semiconductor package of second embodiment of the invention.
Please refer to Figure 14, provide chip 200, described chip 200 surface has pad 201, forms on described chip 200 surface the insulating barrier 210 exposing described pad 201.The plating seed layer being positioned at bond pad surface of described pad 201, follow-up formation and the interconnection metal layer being again positioned at described plating seed layer surface form metal interconnect structure.
Please refer to Figure 15, form plating seed layer 220 at described pad 201 and insulating barrier 210 surface, form the 3rd mask layer 225 on described plating seed layer 220 surface, in described 3rd mask layer 225, form the groove 226 running through described 3rd mask layer 225.
The material of described 3rd mask layer 225 is photoresist, silica, silicon nitride, amorphous carbon wherein one or more, and in the present embodiment, the material of described 3rd mask layer 225 is photoresist.Utilize photoetching process in described 3rd mask layer 225, form the groove 226 running through described 3rd mask layer 225, described groove 226 is follow-up for the formation of interconnection metal layer again.One end of described groove 226 is positioned on described pad 201, and the other end of described groove 226 is positioned on insulating barrier 210.
Please refer to Figure 16, utilize electroplating technology at described groove 226(as shown in figure 15) in form again interconnection metal layer 227.
Described interconnection metal layer again 227 is single layer structure or multilayer lamination structure, and in the present embodiment, described interconnection metal layer again 227 is single-layer metal structure.The material of described interconnection metal layer again 227 is copper.Concrete electroplating technology please refer to the first embodiment.In other embodiments, also sputtering technology or physical gas-phase deposition can be first adopted to form aluminum metal layer, copper metal layer or aluminum bronze metal level etc. on described plating seed layer surface, then utilize dry etch process to etch described aluminum metal layer, copper metal layer or aluminum bronze metal level etc., form interconnection metal layer again.
Described interconnection metal layer again 227 one end is positioned at plating seed layer 220 surface on described pad 201, the other end is positioned at plating seed layer 220 surface on insulating barrier 210, and the columnar electrode of follow-up formation is formed in interconnection metal layer again 227 surface on described insulating barrier 210.Due in order to improve package quality, the spacing of the encapsulation solder joint (i.e. soldered ball) of final formation, position need rationally to arrange, the position of encapsulation solder joint often rule is fixing, and the limited location of the pad of semiconductor chip connects up in internal circuit, the position arrangement of pad is often different from the arrangement of desirable encapsulation solder joint, therefore needs to utilize interconnection metal layer to be connected with encapsulation solder joint electricity by pad again.
Please refer to Figure 17, remove described 3rd mask layer 225(as shown in figure 16), described plating seed layer 220 and again interconnection metal layer 227 surface formed the second mask layer 230, the second opening 235 running through described second mask layer 230 is formed in described second mask layer 230, described second opening 235 exposes partly the surface of interconnection metal layer 227 again, and the size of overlooking visual angle of described second opening 235 is less than the size of the interconnection metal layer again 227 of correspondence position, the surrounding of the interconnection metal layer again 227 exposed is made also to have part interconnection metal layer 227 again.Concrete formation process please refer to the first embodiment.
Please refer to Figure 18, utilize electroplating technology at described second opening 235(as shown in figure 17) in formed columnar electrode 240.Concrete formation process please refer to the first embodiment.
Please refer to Figure 19, remove described second mask layer 230(as shown in figure 18) and Some Species sublayer 220, expose part interconnection metal layer 227 again around described columnar electrode 240.After described second mask layer 230 of removal, expose Seed Layer 220 and interconnection metal layer 227 again, the 4th mask layer (not shown) is formed on described Seed Layer 220, again interconnection metal layer 227 surface, described 4th mask layer covers described columnar electrode 140, again interconnection metal layer 227, with described 4th mask layer for mask, utilize the Some Species sublayer 220 exposed described in wet-etching technology or dry etch process removal, until expose described insulating barrier 210, then remove described 4th mask layer.
Please refer to Figure 20, described insulating barrier 210 and again interconnection metal layer 227 surface formed the first mask layer 250, the position that described first mask layer 250 corresponds to columnar electrode 240 has the first opening 255, the size of described first opening 255 is greater than the size of described columnar electrode 240, and has gap between described first opening 255 sidewall and columnar electrode 240 sidewall.Concrete formation process please refer to the first embodiment.
Please refer to Figure 21, the part exposed at described columnar electrode 240 sidewall surfaces, top surface, the first opening 255 forms diffusion impervious layer 260 in interconnection metal layer 227 surface again.Concrete formation process please refer to the first embodiment.
Please refer to Figure 22, form soakage layer 270 on described diffusion impervious layer 260 surface.Concrete formation process please refer to the first embodiment.
Please refer to Figure 23, remove described first mask layer 250(and please refer to Figure 22), form passivation layer 280 on described insulating barrier 210, again interconnection metal layer 227 surface, described passivation layer 280 covers described columnar electrode 240.Concrete formation process please refer to the first embodiment.
Please refer to Figure 24, described passivation layer 280 is ground, until expose described soakage layer 270.Concrete formation process please refer to the first embodiment.
Please refer to Figure 25, form soldered ball 290 on described soakage layer 270 surface exposed.Concrete formation process please refer to the first embodiment.
According to above-mentioned formation method, second embodiment of the invention additionally provides a kind of semiconductor package, please refer to Figure 25, specifically comprises: chip 200, described chip 200 surface has pad 201, is positioned at described chip 200 surface and exposes the insulating barrier 210 of described pad 201; Be positioned at the plating seed layer 220 on described insulating barrier 210 and pad 201 surface, be positioned at the interconnection metal layer again 227 on plating seed layer 220 surface on described pad 201 and insulating barrier 210, described pad 201 and again interconnection metal layer 227 form metal interconnect structure; The columnar electrode 240 on interconnection metal layer 227 surface again described in being positioned at, described columnar electrode 240 bottom periphery exposes part interconnection metal layer 227 again; Be positioned at the diffusion impervious layer 260 on interconnection metal layer again 227 surface exposed around described columnar electrode 240 sidewall surfaces, top surface, columnar electrode 240; Be positioned at the soakage layer 270 on described diffusion impervious layer 260 surface; Be positioned at described insulating barrier 210 surface and the passivation layer 280 of the soakage layer 270 of covering columnar electrode 240 sidewall, described passivation layer 280 surface flushes with soakage layer 270 surface at described columnar electrode top; Be positioned at the soldered ball 290 on described soakage layer 270 surface.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a formation method for semiconductor package, is characterized in that, comprising:
There is provided chip, described chip surface has metal interconnect structure, forms the insulating barrier exposing described metal interconnect structure at described chip surface;
Columnar electrode is formed on metal interconnect structure surface;
The metal interconnect structure surface exposed at described columnar electrode sidewall surfaces, top surface, columnar electrode bottom periphery in same step forms diffusion impervious layer, makes the section shape of described diffusion impervious layer be " several " font;
Form soakage layer on described diffusion impervious layer surface, the section shape of described soakage layer is also " several " font;
Form passivation layer at described surface of insulating layer, described passivation layer covers described columnar electrode;
Described passivation layer is ground, until expose described soakage layer;
Soldered ball is formed on the described soakage layer surface exposed.
2. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, the material of described soakage layer at least comprises the one in gold element, silver element, phosphide element and tin element.
3. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, described diffusion impervious layer is nickel dam.
4. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, the technique forming described diffusion impervious layer comprises: form the first mask layer at described surface of insulating layer, the position that described first mask layer corresponds to columnar electrode has the first opening, the size of described first opening is greater than the size of described columnar electrode, and has gap between described first opening sidewalls and columnar electrode sidewall; Chemical plating process or electroplating technology is utilized to form diffusion impervious layer at described columnar electrode sidewall surfaces, top surface.
5. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, the technique forming described soakage layer comprises: utilize chemical plating process or electroplating technology to form soakage layer on described diffusion impervious layer surface.
6. the formation method of semiconductor package as claimed in claim 1, it is characterized in that, described metal interconnect structure is pad, and described pad forms columnar electrode.
7. the formation method of semiconductor package as claimed in claim 6, it is characterized in that, the concrete technology forming described columnar electrode comprises: form plating seed layer at described insulating barrier and bond pad surface, the second mask layer is formed on described plating seed layer surface, in described second mask layer, form the second opening running through described second mask layer, described second opening exposes the surface of part pad; Electroplating technology is utilized to form columnar electrode in described second opening; Remove described second mask layer and parcel plating Seed Layer.
8. the formation method of semiconductor package as claimed in claim 1, is characterized in that the interconnection metal layer again that described metal interconnect structure comprises pad and is connected with described pad electricity forms columnar electrode on described interconnection metal layer again.
9. the formation method of semiconductor package as claimed in claim 8, it is characterized in that, the concrete technology forming described columnar electrode comprises: form plating seed layer at described insulating barrier and bond pad surface, form interconnection metal layer again on described plating seed layer surface; Form the second mask layer at described interconnection metal layer again and surface of insulating layer, formed and run through the second opening of described second mask layer in described second mask layer, described second opening to expose described in part interconnection metal layer again; Columnar electrode is formed in described second opening; Remove described second mask layer and parcel plating Seed Layer.
10. the formation method of semiconductor package as claimed in claim 9, it is characterized in that, described in formation, the concrete technology of interconnection metal layer comprises again: form the 3rd mask layer on described plating seed layer surface, the groove running through described 3rd mask layer is formed in described 3rd mask layer, the plating seed layer surface utilizing electroplating technology to expose at described groove forms interconnection metal layer again, then removes described 3rd mask layer.
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| CN104465571A (en) * | 2014-12-16 | 2015-03-25 | 南通富士通微电子股份有限公司 | Wafer packaging structure |
| CN105845659B (en) * | 2015-01-15 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | Lead wire welding mat structure and forming method thereof |
| CN109148495A (en) * | 2018-07-02 | 2019-01-04 | 复旦大学 | A kind of cmos image sensor three-dimension packaging method |
| CN110536564B (en) * | 2019-08-30 | 2022-04-22 | 宁波华远电子科技有限公司 | Method for manufacturing circuit board with boss as bonding pad |
| CN111627880A (en) * | 2020-06-04 | 2020-09-04 | 厦门通富微电子有限公司 | Semiconductor bump, manufacturing method thereof and packaging structure |
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| CN101106116A (en) * | 2006-07-14 | 2008-01-16 | 冲电气工业株式会社 | Semiconductor device and method of producing the same |
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| US8492891B2 (en) * | 2010-04-22 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with electrolytic metal sidewall protection |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |