TWI478300B - Flip-chip package substrate and fabrication method thereof - Google Patents
Flip-chip package substrate and fabrication method thereof Download PDFInfo
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- TWI478300B TWI478300B TW097123294A TW97123294A TWI478300B TW I478300 B TWI478300 B TW I478300B TW 097123294 A TW097123294 A TW 097123294A TW 97123294 A TW97123294 A TW 97123294A TW I478300 B TWI478300 B TW I478300B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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Description
本發明係有關於一種半導體結構及其製法，尤指一種封裝基板及其製法。The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a package substrate and a method of fabricating the same.
隨著電子產業的發達，半導體封裝技術亦隨之開發出不同的封裝型態，其中，覆晶封裝(Flip Chip Package)技術係將半導體晶片之電極墊直接電性連接封裝基板之電性接觸墊，而不使用打線式(wire bonding)之金線，使得覆晶技術不僅可提高封裝結構佈線密度，且可降低封裝結構整體尺寸，以達微型化(Miniaturization)的封裝需求，甚至因不需使用導電路徑較長之金線，而可提高電性功能；請參閱第1A至1E圖，係提供習知覆晶式封裝結構之製法。With the development of the electronics industry, semiconductor packaging technology has also developed different package types. Among them, Flip Chip Package technology directly electrically connects the electrode pads of semiconductor wafers to the electrical contact pads of the package substrate. Instead of using wire bonding gold wires, flip chip technology not only increases the package structure wiring density, but also reduces the overall size of the package structure to meet the needs of miniaturization packaging, even because it is not needed. The gold wire with a long conductive path can improve the electrical function; please refer to Figures 1A to 1E to provide a conventional method for fabricating a flip chip package.
如第1A圖所示，首先，係提供表面具有複數電性接觸墊110之基板本體11；如第1B圖所示，於該基板本體11及該些電性接觸墊110上形成防焊層12，且該防焊層12形成複數開孔120，以對應顯露各該電性接觸墊110；如第1C圖所示，於顯露之電性接觸墊110上形成焊料凸塊13；如第1D圖所示，提供一半導體晶片14，且該半導體晶片14具有電極墊141以電性連接焊料凸塊13，而使半導體晶片14置於基板本體11上且電性連接該電性接觸墊110；如第1E圖所示，最後，於該半導體晶片14與防焊層12之間形成底膠15，以包覆焊料凸塊13，且強化半 導體晶片14與基板本體11之間之機械性連接。As shown in FIG. 1A, first, a substrate body 11 having a plurality of electrical contact pads 110 is provided; as shown in FIG. 1B, a solder resist layer 12 is formed on the substrate body 11 and the electrical contact pads 110. And the solder resist layer 12 forms a plurality of openings 120 to correspondingly expose the respective electrical contact pads 110; as shown in FIG. 1C, the solder bumps 13 are formed on the exposed electrical contact pads 110; as shown in FIG. As shown, a semiconductor wafer 14 is provided, and the semiconductor wafer 14 has an electrode pad 141 for electrically connecting the solder bumps 13, and the semiconductor wafer 14 is placed on the substrate body 11 and electrically connected to the electrical contact pads 110; Finally, in FIG. 1E, a primer 15 is formed between the semiconductor wafer 14 and the solder resist layer 12 to coat the solder bumps 13 and strengthen the half. A mechanical connection between the conductor wafer 14 and the substrate body 11 is achieved.
然而，習知覆晶式封裝結構之製法不易控制底膠15之流動範圍，而易造成底膠15流動超過預定範圍，即底膠15溢流現象，於製造過程中，當底膠15漫流過基板本體11表面之預定範圍時，該底膠15將沾黏在生產治具上或基板本體11表面之其他元件；因此，將造成使用者不僅需清潔治具而浪費時間，且若使沾著底膠15之治具繼續工作時，將使底膠15沾著於另一基板本體11表面之其他部位，而影響接合功效，導致產品的品質不佳。However, the conventional method of flip-chip package structure is not easy to control the flow range of the primer 15, and it is easy to cause the primer 15 to flow beyond a predetermined range, that is, the underfill 15 overflows. During the manufacturing process, the primer 15 flows over the manufacturing process. When the surface of the substrate body 11 is within a predetermined range, the primer 15 will adhere to other components on the surface of the production fixture or the substrate body 11; therefore, the user will not only need to clean the fixture but waste time, and if it is stained When the jig of the primer 15 continues to work, the primer 15 is adhered to other portions of the surface of the other substrate body 11, which affects the bonding efficiency, resulting in poor quality of the product.
因此，鑒於上述之問題，如何提供一種避免底膠溢流發生之封裝基板，實已成目前亟欲解決的重要課題。Therefore, in view of the above problems, how to provide a package substrate that avoids the occurrence of adhesive overflow has become an important issue that is currently being solved.
鑑於上述習知技術之缺失，本發明之主要目的係在於提供一種避免底膠溢流發生之封裝基板及其製法。In view of the above-mentioned deficiencies of the prior art, the main object of the present invention is to provide a package substrate which avoids the occurrence of overfill overflow and a method of manufacturing the same.
為達上述目的，本發明揭露一種封裝基板，係包括：基板本體，其至少一表面具有一置晶區，該置晶區具有複數電性接觸墊；第一防焊層，係設於該基板本體表面及該些電性接觸墊上，且具有複數開孔，以對應顯露各該電性接觸墊；以及第二防焊層，係設於部分該第一防焊層上，且具有一開口，以顯露位在該置晶區中之部份該第一防焊層及部分該些電性接觸墊，且於該置晶區周圍之該第二防焊層與該第一防焊層係呈現階梯狀。To achieve the above objective, the present invention discloses a package substrate, comprising: a substrate body having at least one surface having a crystallized region, the crystallographic region having a plurality of electrical contact pads; and a first solder resist layer disposed on the substrate The surface of the body and the electrical contact pads have a plurality of openings to correspondingly expose the electrical contact pads; and the second solder mask is disposed on a portion of the first solder resist layer and has an opening. The first solder resist layer and a portion of the electrical contact pads are exposed in a portion of the crystallized region, and the second solder resist layer and the first solder resist layer are disposed around the crystallographic region Stepped.
上述之封裝基板復可包括焊料凸塊，係設於該電性接觸墊上，且該焊料凸塊係可為錫(Sn)、鉛(Pb)、銀(Ag)、 銅(Cu)、鋅(Zn)、鉍(Bi)、鎳(Ni)、鈀(Pd)或金(Au)所組成之群組。The package substrate may include solder bumps on the electrical contact pads, and the solder bumps may be tin (Sn), lead (Pb), silver (Ag), A group consisting of copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd) or gold (Au).
本發明復提供一種封裝基板之製法，係包括：提供一基板本體，該基板本體至少一表面具有一置晶區，且該置晶區上具有複數電性接觸墊；於基板本體及該些電性接觸墊上形成第一防焊層，且於該第一防焊層中形成複數開孔，以對應顯露各該電性接觸墊；以及於部分該第一防焊層上形成第二防焊層，且於第二防焊層形成一開口，以顯露位在該置晶區中之部份該第一防焊層及部分該些電性接觸墊，且於該置晶區周圍之該第二防焊層與該第一防焊層係呈現階梯狀。The invention provides a method for manufacturing a package substrate, comprising: providing a substrate body, the substrate body having a crystallized area on at least one surface thereof, and the plurality of electrical contact pads on the crystallized area; the substrate body and the electricity Forming a first solder resist layer on the contact pad, and forming a plurality of openings in the first solder resist layer to correspondingly expose the respective electrical contact pads; and forming a second solder resist layer on a portion of the first solder resist layer Forming an opening in the second solder resist layer to expose a portion of the first solder resist layer and a portion of the electrical contact pads located in the crystallographic region, and the second portion around the crystallographic region The solder resist layer and the first solder resist layer are stepped.
上述之製法復可包括於電性接觸墊上形成複數焊料凸塊，且該焊料凸塊之材料係可為錫(Sn)、鉛(Pb)、銀(Ag)、銅(Cu)、鋅(Zn)、鉍(Bi)、鎳(Ni)、鈀(Pd)或金(Au)所組成之群組。The above method may include forming a plurality of solder bumps on the electrical contact pads, and the material of the solder bumps may be tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn). ), a group consisting of bismuth (Bi), nickel (Ni), palladium (Pd) or gold (Au).
相較於習知技術，本發明之封裝基板係藉由於第一防焊層上設置第二防焊層，且藉由第二防焊層之開口而顯露位在置晶區上之第一防焊層及電性接觸墊，以使該第二防焊層設於置晶區的外圍，相較於習知技術，當填入底膠置晶區時，本發明之第二防焊層具有止擋作用以限制底膠之流動範圍，而達到避免底膠溢流之目的。Compared with the prior art, the package substrate of the present invention is characterized in that the first solder resist layer is disposed on the first solder resist layer, and the first anti-shield layer is exposed by the opening of the second solder resist layer. a solder layer and an electrical contact pad, so that the second solder resist layer is disposed on the periphery of the crystallizing region, and the second solder resist layer of the present invention has a filler layer when the primer is placed in the crystallizing region as compared with the prior art The stop function is to limit the flow range of the primer, so as to avoid the overflow of the primer.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地 瞭解本發明之其他優點及功效。The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easily Other advantages and effects of the present invention are understood.
請參閱第2A至2E圖，係詳細說明本發明之封裝基板及其製法之剖視流程圖。其中，第2C’係為第2C圖之上視圖。2A to 2E are cross-sectional views showing the package substrate of the present invention and a method of manufacturing the same. Here, the second C' is a top view of the second C-picture.
如第2A圖所示，首先，提供至少一表面具有置晶區21a之基板本體21，且該置晶區21a內具有複數電性接觸墊211。As shown in FIG. 2A, first, at least one substrate body 21 having a crystallizing region 21a is provided, and the plurality of electrical contact pads 211 are disposed in the crystallizing region 21a.
如第2B圖所示，於該基板本體21表面及該些電性接觸墊211上形成第一防焊層22a，且於該第一防焊層22a上形成複數開孔220a，以對應顯露各該電性接觸墊211之局部表面。As shown in FIG. 2B, a first solder resist layer 22a is formed on the surface of the substrate body 21 and the electrical contact pads 211, and a plurality of openings 220a are formed on the first solder resist layer 22a to correspondingly expose The electrical contact pad 211 is a partial surface.
如第2C及2C’圖所示，於部分該第一防焊層22a上形成第二防焊層22b，且於該第二防焊層22b上形成一開口220b，以顯露位在置晶區21a中之部分該第一防焊層22a及由開孔220a顯露之部份該些電性接觸墊211，且於該置晶區21a周圍之該第二防焊層22b與該第一防焊層22a係呈現階梯狀，以完成本發明之封裝基板。As shown in FIGS. 2C and 2C', a second solder resist layer 22b is formed on a portion of the first solder resist layer 22a, and an opening 220b is formed on the second solder resist layer 22b to be exposed in the crystal region. a portion of the first solder mask 22a and a portion of the electrical contact pads 211 exposed by the opening 220a, and the second solder resist 22b around the crystal region 21a and the first solder resist Layer 22a is stepped to complete the package substrate of the present invention.
如第2D圖所示，於後續製程中，該第一防焊層22a之開孔220a中以印刷、電鍍或微植球方式形成有焊料凸塊25，且該焊料凸塊25係為錫(Sn)、鉛(Pb)、銀(Ag)、銅(Cu)、鋅(Zn)、鉍(Bi)、鎳(Ni)、鈀(Pd)及金(Au)所組成之群組之其中一者。As shown in FIG. 2D, in the subsequent process, solder bumps 25 are formed in the openings 220a of the first solder resist layer 22a by printing, plating or micro-balling, and the solder bumps 25 are tin ( One of a group consisting of Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), and gold (Au) By.
如第2E圖所示，接著，提供一具有作用面26a之半導體晶片26，且該作用面26a上具有複數電極墊261，以 藉各該電極墊261結合至焊料凸塊25而電性連接該電性接觸墊211，俾使該半導體晶片26設於置晶區21a上；再於半導體晶片26之作用面26a與置晶區21a之間形成係為高分子樹脂材料所製成之底膠27，藉以包覆該焊料凸塊25，並使該半導體晶片26與基板本體21之間形成良好機械性連接。As shown in FIG. 2E, a semiconductor wafer 26 having an active surface 26a is provided, and the active surface 26a has a plurality of electrode pads 261 thereon. The electrode pads 261 are electrically connected to the solder bumps 25 to electrically connect the electrical contact pads 211, so that the semiconductor wafers 26 are disposed on the crystallizing region 21a; and the active surface 26a and the crystallizing region of the semiconductor wafer 26 are further disposed. A primer 27 made of a polymer resin material is formed between 21a to cover the solder bumps 25, and a good mechanical connection is formed between the semiconductor wafer 26 and the substrate body 21.
由於第二防焊層22b的高度高於第一防焊層22a，以使設於置晶區21a外圍之第二防焊層22b具有止擋作用，以限制該底膠27之流動範圍，而避免底膠27溢流至該置晶區21a的外圍。Since the height of the second solder resist layer 22b is higher than that of the first solder resist layer 22a, the second solder resist layer 22b provided on the periphery of the crystallizing region 21a has a stopper function to limit the flow range of the underfill 27, and The underfill 27 is prevented from overflowing to the periphery of the crystallizing region 21a.
本發明復揭露一種封裝基板，係包括：基板本體21，其至少一表面具有一置晶區21a，該置晶區21a具有複數電性接觸墊211；第一防焊層22a，係設於該基板本體21表面及該些電性接觸墊211上，且該第一防焊層22a具有複數開孔220a，以對應顯露各該電性接觸墊211；以及第二防焊層22b，係設於部分該第一防焊層22a上，且該第二防焊層22b具有一開口220b，以顯露位在該置晶區21a中之部分該第一防焊層22a及部分該些電性接觸墊211，且於該置晶區21a周圍之該第二防焊層22b與該第一防焊層22a係呈現階梯狀。The present invention discloses a package substrate, comprising: a substrate body 21 having at least one surface having a crystallized region 21a having a plurality of electrical contact pads 211; the first solder resist layer 22a is disposed on the substrate The surface of the substrate body 21 and the electrical contact pads 211, and the first solder resist layer 22a has a plurality of openings 220a to correspondingly expose the respective electrical contact pads 211; and the second solder resist layer 22b is a portion of the first solder resist layer 22a, and the second solder resist layer 22b has an opening 220b for exposing a portion of the first solder resist layer 22a and some of the electrical contact pads located in the crystallizing region 21a. 211, and the second solder resist layer 22b around the crystallizing region 21a and the first solder resist layer 22a are stepped.
所述之封裝基板復包括設於該電性接觸墊211上之焊料凸塊25，其材料係為錫(Sn)、鉛(Pb)、銀(Ag)、銅(Cu)、鋅(Zn)、鉍(Bi)、鎳(Ni)、鈀(Pd)及金(Au)所組成之群組之其中一者。The package substrate further includes a solder bump 25 disposed on the electrical contact pad 211, and the material thereof is tin (Sn), lead (Pb), silver (Ag), copper (Cu), and zinc (Zn). One of a group consisting of bismuth (Bi), nickel (Ni), palladium (Pd), and gold (Au).
綜上所述，本發明之封裝基板主要藉由將具有一開口之第二防焊層設於第一防焊層上，不僅顯露位在置晶區中之第一防焊層及電性接觸墊，且使第二防焊層高於置晶區之第一防焊層，以使第二防焊層具有止擋作用，而有效達到避免底膠溢流之目的，進而提高封裝之良率。In summary, the package substrate of the present invention is mainly provided by disposing a second solder resist layer having an opening on the first solder resist layer, thereby not only revealing the first solder resist layer and the electrical contact in the crystallographic region. Pad, and the second solder mask is higher than the first solder resist layer of the crystallizing zone, so that the second solder resist layer has a stop function, thereby effectively achieving the purpose of avoiding the overflow of the primer, thereby improving the yield of the package. .
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
11,21‧‧‧基板本體11, 21‧‧‧ substrate body
110,211‧‧‧電性接觸墊110,211‧‧‧Electrical contact pads
12‧‧‧防焊層12‧‧‧ solder mask
120,220a‧‧‧開孔120, 220a‧‧‧ openings
13,25‧‧‧焊料凸塊13,25‧‧‧ solder bumps
14,26‧‧‧半導體晶片14,26‧‧‧Semiconductor wafer
141,261‧‧‧電極墊141,261‧‧‧electrode pads
15,27‧‧‧底膠15,27‧‧‧Bottom
21a‧‧‧置晶區21a‧‧‧Setting area
22a‧‧‧第一防焊層22a‧‧‧First solder mask
22b‧‧‧第二防焊層22b‧‧‧Second solder mask
220b‧‧‧開口220b‧‧‧ openings
26a‧‧‧作用面26a‧‧‧Action surface
第1A至1E圖係為習知覆晶式封裝結構之製法之剖視示意圖；以及第2A至2E圖係為本發明之封裝基板及其製法之剖視示意圖；其中，第2C’係為第2C圖之上視圖。1A to 1E are schematic cross-sectional views showing a conventional method for fabricating a flip-chip package structure; and FIGS. 2A to 2E are cross-sectional views showing a package substrate of the present invention and a method for manufacturing the same; wherein the 2C' is a View above the 2C chart.
21‧‧‧基板本體21‧‧‧Substrate body
21a‧‧‧置晶區21a‧‧‧Setting area
211‧‧‧電性接觸墊211‧‧‧Electrical contact pads
22a‧‧‧第一防焊層22a‧‧‧First solder mask
220a‧‧‧開孔220a‧‧‧ opening
22b‧‧‧第二防焊層22b‧‧‧Second solder mask
220b‧‧‧開口220b‧‧‧ openings
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097123294A TWI478300B (en) | 2008-06-23 | 2008-06-23 | Flip-chip package substrate and fabrication method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097123294A TWI478300B (en) | 2008-06-23 | 2008-06-23 | Flip-chip package substrate and fabrication method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201001640A TW201001640A (en) | 2010-01-01 |
| TWI478300B true TWI478300B (en) | 2015-03-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW097123294A TWI478300B (en) | 2008-06-23 | 2008-06-23 | Flip-chip package substrate and fabrication method thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI478300B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI416680B (en) * | 2010-01-18 | 2013-11-21 | Unimicron Technology Corp | Package substrate and fabrication method thereof |
| US20120032337A1 (en) * | 2010-08-06 | 2012-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flip Chip Substrate Package Assembly and Process for Making Same |
| JP2013048205A (en) * | 2011-07-25 | 2013-03-07 | Ngk Spark Plug Co Ltd | Method of manufacturing wiring board |
| TWI606565B (en) * | 2016-08-31 | 2017-11-21 | 金寶電子工業股份有限公司 | Package structure and manufacturing method thereof |
| US12014969B2 (en) | 2021-08-30 | 2024-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method for forming the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040165362A1 (en) * | 2003-02-20 | 2004-08-26 | Farnworth Warren M. | Chip scale package structures and method of forming conductive bumps thereon |
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2008
- 2008-06-23 TW TW097123294A patent/TWI478300B/en active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040165362A1 (en) * | 2003-02-20 | 2004-08-26 | Farnworth Warren M. | Chip scale package structures and method of forming conductive bumps thereon |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201001640A (en) | 2010-01-01 |
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