TWI416680B - Package substrate and fabrication method thereof - Google Patents

Abstract

A method of fabricating a package substrate is disclosed, comprising providing a core layer having a die-mounting area defined on one surface thereof and a plurality of first solder pads disposed surrounding the inner edge of the die-mounting area; forming a first insulating protection layer on the surface and each of the solder pads and forming a first insulating protection layer opening in the first insulating protection layer; forming a metal layer on the surface, the first solder pads and the first insulating protection layer on an area that is slightly larger than the die-mounting area; forming a first dielectric layer on the surface, the first insulating protection layer and the metal layer; forming a second circuit layer with second solder pads on the first dielectric layer; forming a second insulating protection layer on the second circuit layer and the first dielectric layer; removing the first dielectric layer form the die-mounting area; and removing the metal layer, thereby providing a package substrate having a relatively compact size and better good yield. The invention further discloses a package substrate fabricated by the method as described above.

Description

Package substrate and its preparation method

The invention relates to a package substrate and a preparation method thereof, in particular to a package substrate with high quality and yield and a preparation method thereof.

With the rapid development of the electronics industry, electronic products have gradually entered the trend of multi-function and high-performance. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, for more active and passive components and lines to be carried, the semiconductor package substrate is gradually evolved from double layer to multi-layer.俾Using an interlayer connection in a limited space to expand the layout area available on the semiconductor package substrate, thereby reducing the thickness of the package substrate in accordance with the need for a high circuit density integrated circuit. To meet the needs of light and short electronic products.

However, with the popularity of portable electronic products such as mobile phones, digital cameras, and digital cameras, traditional packaging technologies have been difficult to meet their needs, and the industry has developed a cavity-up line. For the wire bonding package substrate, please refer to FIGS. 1A to 1C, which are schematic cross-sectional views of a conventional cavity-up line type package substrate and a method for manufacturing the same.

As shown in FIG. 1A, two core plates 10, 11 and a dielectric layer 12, such as a prepreg (PP) material, are provided, the core plate 10 and the dielectric layer 12 respectively having openings 100 therethrough. 120.

As shown in FIG. 1B, the core plates 10, 11 and the dielectric layer 12 are integrally pressed together to form a substrate body 1 having openings 100, 120 for inserting the semiconductor wafer, and formed through the substrate body 1. Conductive through hole 13.

As shown in FIG. 1C, solder resist layers 14 and 15 are formed on opposite surfaces of the substrate body 1, respectively, and the solder resist layers 14 and 15 respectively form an opening 140 and a plurality of openings 150 for the portion of the crystal side. The circuit layer is exposed to the opening 140 as a wire pad 16 so that a portion of the wiring layer on the ball-balling side is exposed to the opening 150 as a ball-laying pad 17 to complete the package substrate 2.

As shown in FIG. 1D, in the application example of the package substrate 2, a semiconductor wafer 18 is placed on the surface of the core board 11 in the openings 100, 120 of the package substrate 2, and is made by a wire bond 181. The semiconductor wafer 18 is electrically connected to the wire bonding pad 16, and finally the wire 181, the wire bonding pad 16 and the semiconductor wafer 18 are covered with a packaging material 19, thus completing a package structure.

However, in the foregoing method, the core plates 10 and 11 are joined to each other by the dielectric layer 12, and the volume of the dielectric layer 12 is not easily controlled accurately, and the dielectric layer 12 is often caused to irregularly overflow; Moreover, since the thickness of the core plates 10 and 11 is relatively thick (usually greater than 200 micrometers), the structures on both sides of the bonded package substrate 2 have a large asymmetry, and the package substrate 2 is easily warped ( The warpage phenomenon, the above defects all seriously affect the yield and reliability of the final package structure; in addition, since the package structure includes two core boards 10, 11, the thickness and volume of the overall structure of the package substrate 2 cannot be reduced.

Therefore, how to avoid the problems that the package substrate in the prior art is susceptible to dielectric layer overflow, substrate warpage, and large overall size, which leads to problems such as lower quality and yield of the final package structure, has become a problem. The problem to be solved.

In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a package substrate which is less prone to overflow and warpage of a dielectric layer and a method of fabricating the same.

To achieve the above and other objects, the present invention discloses a package substrate comprising: a core layer having opposite first and second surfaces, and having a crystallizing region and a first circuit layer on the first surface, the first a circuit layer having a plurality of first finger pads disposed on the edge of the crystal region and a first line electrically connected to the first finger pad; and a first insulating protective layer disposed on the first surface a first soldering pad and a first insulating layer have a first insulating protective layer opening, so that each of the first finger pads is correspondingly exposed to the first insulating protective layer opening; An electrical layer is disposed on the first surface, the first line, and the first insulating protective layer, and the first dielectric layer has a first dielectric layer opening, so that the opening of the first dielectric layer is correspondingly exposed a first surface, a first finger pad, and a first insulating protective layer; the second circuit layer is disposed on the first dielectric layer and has a plurality of second finger pads; and a second An insulating protective layer is disposed on the second circuit layer and the first dielectric layer, and the second insulating protective layer is The second insulating protective layer has an opening, and the second finger pad is exposed to the second insulating protective layer opening.

In the above package substrate, the first dielectric layer opening has a notch adjacent to the bottom surface of the first dielectric layer of each of the first finger pads, and is disposed on each of the first and second finger pads. The first metal protective layer may be provided with a material of nickel/gold (Ni/Au), electroless Palladium/Immersion Gold (ENEPIG), and tin (Sn). ), silver (Ag), or gold (Au).

According to the package substrate, a third circuit layer is disposed on the second surface, and a second dielectric layer is disposed on the second surface and the third circuit layer, and the second dielectric layer is disposed on the second surface The fourth layer may be provided with a fourth circuit layer, and the fourth circuit layer may have a plurality of electrical contact pads, and may further comprise a conductive via extending through the core layer, the first dielectric layer and the second dielectric layer. The conductive vias are electrically connected to the first circuit layer, the second circuit layer, the third circuit layer, and the fourth circuit layer.

In the foregoing package substrate, the third insulating protective layer is disposed on the second dielectric layer and the fourth circuit layer, and the third insulating protective layer may have a plurality of third insulating protective layer openings Each of the electrical contact pads is correspondingly exposed to each of the third insulating protective layer openings, and a second metal protective layer is disposed on each of the electrical contact pads, and the second metal protective layer may be made of nickel. / Gold (Ni/Au), Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG), Tin (Sn), Silver (Ag), or Gold (Au).

The invention provides a method for manufacturing a package substrate, comprising: providing a core layer having opposite first and second surfaces, and having a crystallizing region and a first circuit layer on the first surface, the first line The layer has a plurality of first finger pads disposed on the edge of the crystal region, and a first line electrically connected to the first finger pad; forming on the first surface, the first finger pad and the first line a first insulating protective layer, and a first insulating protective layer opening is formed in the first insulating protective layer, so that each of the first finger pads is correspondingly exposed to the first insulating protective layer opening; Forming a metal layer disposed on the first surface, the first finger pad and the first insulating protective layer in the region of the crystal region; forming a first layer on the first surface, the first line, the first insulating protective layer and the metal layer a dielectric layer; a second circuit layer having a plurality of second finger pads formed on the first dielectric layer; a second insulating protective layer formed on the second circuit layer and the first dielectric layer, and the second Forming a second insulating protective layer opening in the insulating protective layer, so that the second finger pad is a first dielectric layer in the crystallographic region is exposed to the second insulating protective layer opening; removing the first dielectric layer in the crystallizing region to expose the metal layer in the crystallizing region; and removing The metal layer.

According to the manufacturing method of the package substrate, the process for forming the metal layer may include: forming a conductive layer on the first surface, the first finger pad, the first line and the first insulating protective layer; and the conductive layer Forming a first resist layer thereon, and forming a first opening slightly larger than the crystallographic region in the first resistive layer, so that a portion of the conductive layer is correspondingly exposed to the first opening; plating on the conductive layer in the first opening Forming the metal layer; and removing the first resist layer and the conductive layer covered thereby while reducing the thickness of the metal layer.

In the foregoing method, removing the metal layer may include removing the conductive layer covered by the metal layer.

In the above method for manufacturing a package substrate, before the removing the first dielectric layer in the crystallographic region, the second dielectric layer, the second insulating protective layer and the second finger pad are formed to form a second resistance. a second opening formed in the second resist layer, wherein the first dielectric layer in the crystallographic region is exposed to the second opening, and the removing may include removing the metal layer Two resistive layers.

In the above method, the first dielectric layer can be removed by laser ablation, and the material forming the conductive layer can be copper (Cu), and the material forming the metal layer can be copper (Cu), and the metal The thickness of the layer can be less than 5 microns (μm).

In the method of manufacturing the package substrate of the present invention, the first metal pad is formed on each of the first and second finger pads, and the material forming the first metal protection layer is nickel/gold ( Ni/Au), Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG), Tin (Sn), Silver (Ag), or Gold (Au).

In the above method for manufacturing a package substrate, the method further includes forming a third circuit layer on the second surface, and further comprising forming a second dielectric layer on the second surface and the third circuit layer, and in the second Forming a fourth circuit layer on the dielectric layer, the fourth circuit layer having a plurality of electrical contact pads, and further comprising forming a conductive via extending through the core layer, the first dielectric layer and the second dielectric layer, The conductive vias are electrically connected to the first circuit layer, the second circuit layer, the third circuit layer, and the fourth circuit layer.

Furthermore, in the above method, the third insulating layer is formed on the second dielectric layer and the fourth circuit layer, and a plurality of third insulating protective layer openings are formed in the third insulating protective layer. Each of the electrical contact pads is exposed to each of the third insulating protective layer openings, and further includes a second metal protective layer formed on each of the electrical contact pads, and the material forming the second metal protective layer may be nickel/ Gold (Ni/Au), Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG), Tin (Sn), Silver (Ag), or Gold (Au).

It can be seen from the above that the method for manufacturing the package substrate of the present invention is to complete the cavity layer upward-facing package substrate in a core layer build-up process, without using a dielectric layer to bond the two core plates as is conventional. Therefore, there is no dielectric layer overflow phenomenon, and because the thickness of the dielectric layer for layering is much thinner than the core plate (usually less than 50 microns), it is less conventionally easy to warp and larger overall size. Such disadvantages not only facilitate the packaging substrate with high line density, but also the final product is relatively light and thin.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

2A to 2K are schematic cross-sectional views showing a package substrate of the present invention and a method of manufacturing the same, wherein the second A' is a plan view of Fig. 2A.

As shown in FIGS. 2A and 2A', first, a core layer 20 is provided having an opposite first surface 20a and a second surface 20b having a crystallographic region 200 and a first wiring layer 21 on the first surface 20a. The first circuit layer 21 has a plurality of first finger pads 211 disposed on the inner edge of the crystal region 200, and a first line 212 electrically connected to the first finger pads 211, and on the second surface 20b. Forming a third circuit layer 31 thereon; then, forming a first insulating protective layer 22 on the first surface 20a (including the seeding region 200), the first finger pads 211 and the first line 212, and the first insulating protection layer A first insulating protective layer opening 220 is formed in the layer 22, so that each of the first finger pads 211 is correspondingly exposed to the first insulating protective layer opening 220.

As shown in FIG. 2B, a conductive layer 23 is formed on the first surface 20a, the first finger pad 211, the first line 212, and the first insulating protective layer 22. The material of the conductive layer 23 may be copper (Cu). ).

As shown in FIG. 2C, a first resist layer 24 is formed on the conductive layer 23, the second surface 20b, and the third wiring layer 31, and a first portion of the first resist layer 24 is formed to be slightly larger than the first crystal region 200. The opening 240 is such that a portion of the conductive layer 23 is correspondingly exposed to the first opening 240.

As shown in FIG. 2D, a metal layer 25 is formed on the conductive layer 23 in the first opening 240. The material forming the metal layer 25 may be copper (Cu), and the thickness of the metal layer 25 may be less than 5 micrometers. (μm).

As shown in FIG. 2E, the first resist layer 24 and the conductive layer 23 covered therein are removed, and at the same time, the thickness of the metal layer 25 is reduced.

As shown in FIG. 2F, a first dielectric layer 26a is formed on the first surface 20a, the first line 212, the first insulating protective layer 22 and the metal layer 25, and the second surface 20b and the third circuit layer are formed on the second surface 20b. A second dielectric layer 26b is formed on 31.

As shown in FIG. 2G, a second wiring layer 27a having a plurality of second finger pads 271a is formed on the first dielectric layer 26a, and a fourth wiring layer 27b is formed on the second dielectric layer 26b. The fourth circuit layer 27b has a plurality of electrical contact pads 271b; then, a conductive via 32 extending through the core layer 20, the first dielectric layer 26a and the second dielectric layer 26b is formed, and the conductive via 32 is electrically connected. Connecting the first circuit layer 21, the second circuit layer 27a, the third circuit layer 31, and the fourth circuit layer 27b; then forming a second insulating protective layer on the second circuit layer 27a and the first dielectric layer 26a a second insulating protective layer opening 280a is formed in the second insulating protective layer 28a, and the second dielectric pad 271a and the first dielectric layer 26a in the crystallizing region 200 are exposed to the second insulating protection. a third insulating layer 28b is formed on the second dielectric layer 26b and the fourth wiring layer 27b, and a plurality of third insulating protective layer openings 280b are formed in the third insulating protective layer 28b. Each of the electrical contact pads 271b is correspondingly exposed to each of the third insulating protective layer openings 280b.

As shown in FIG. 2H, a second resist layer 29 is formed on the first dielectric layer 26a, the second insulating protective layer 28a, the second finger pads 271a, the electrical contact pads 271b, and the third insulating protective layer 28b. A second opening 290 is formed in the second resist layer 29 to expose the first dielectric layer 26a in the crystallizing region 200 to the second opening 290.

As shown in FIG. 2I, the first dielectric layer 26a in the crystal region 200 is removed to form a first dielectric layer opening 260a, and the metal layer 25 in the crystal region 200 is exposed. A dielectric layer 26a can be removed by laser ablation.

As shown in FIG. 2J, the metal layer 25 and the conductive layer 23 covered by the metal layer 25 are removed. At this time, the first dielectric layer opening 260a is adjacent to the first dielectric layer 26a of each of the first finger pads 211. The bottom side wall is formed with a notch 261a.

As shown in FIG. 2K, the second resist layer 29 is removed, and a first metal protective layer 30a is formed on each of the first finger pads 211 and the second finger pads 271a, and each of the electrical contact pads A second metal protective layer 30b is formed on the 271b; wherein the material forming the first metal protective layer 30a and the second metal protective layer 30b may be nickel/gold (Ni/Au), nickel-palladium immersion gold (Electroless Nickel / Electroless) Palladium / Immersion Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au).

The present invention further provides a package substrate, comprising: a core layer 20 having opposite first and second surfaces 20a and 20b, and having a crystallized region 200 and a first circuit layer 21 on the first surface 20a. A circuit layer 21 has a plurality of first finger pads 211 disposed on the inner edge of the crystal region 200, and a first line 212 electrically connected to the first finger pads 211; and a first insulating protection layer 22 is disposed on The first surface 20a, the first finger pad 211 and the first line 212, and the first insulating protective layer 22 has a first insulating protective layer opening 220, so that the first finger pads 211 are correspondingly exposed. The first insulating protective layer opening 220; the first dielectric layer 26a is disposed on the first surface 20a, the first line 212, and the first insulating protective layer 22, and the first dielectric layer 26a has a first a dielectric layer opening 260a, such that the first dielectric layer opening 260a correspondingly exposes the first surface 20a, the first finger pad 211, and the first insulating protection layer 22 in the crystallizing area 200; the second line The layer 27a is disposed on the first dielectric layer 26a and has a plurality of second finger pads 271a; and a second insulating protective layer 28a is disposed on the layer The second circuit layer 27a and the first dielectric layer 26a have a second insulating protective layer opening 280a, and the second finger pad 271a is exposed to the second insulating protective layer. Hole 280a.

In the package substrate, the first dielectric layer opening 260a is adjacent to the bottom surface of the first dielectric layer 26a of each of the first finger pads 211 and has a notch 261a.

The first metal protective layer 30a is disposed on each of the first finger pads 211 and the second finger pads 271a according to the package substrate, and the material of the first metal protection layer 30a may be nickel/gold. (Ni/Au), Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG), Tin (Sn), Silver (Ag), or Gold (Au).

Further, in the package substrate, a third circuit layer 31 is disposed on the second surface 20b, and a second dielectric layer 26b is disposed on the second surface 20b and the third circuit layer 31, and The second dielectric layer 26b is further provided with a fourth circuit layer 27b. The fourth circuit layer 27b has a plurality of electrical contact pads 271b, and further includes a core layer 20, a first dielectric layer 26a and a second layer. The conductive via 32 of the dielectric layer 26b electrically connects the conductive via 32 to the first wiring layer 21, the second wiring layer 27a, the third wiring layer 31, and the fourth wiring layer 27b.

The package substrate as described above further includes a third insulating protective layer 28b disposed on the second dielectric layer 26b and the fourth wiring layer 27b, and the third insulating protective layer 28b has a plurality of third insulating protective layers. Opening the hole 280b, so that each of the electrical contact pads 271b is correspondingly exposed to each of the third insulating protective layer openings 280b, and the second metal protective layer 30b is disposed on each of the electrical contact pads 271b, and the second metal is The material of the protective layer 30b may be nickel/gold (Ni/Au), Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG), tin (Sn), silver (Ag), or gold (Au).

In summary, the method for manufacturing the package substrate of the present invention is to complete the cavity layer upward-facing package substrate in a core layer build-up process, without using a dielectric layer to bond the two core plates as is conventional. In this way, there is no leakage of the dielectric layer, and because the thickness of the dielectric layer for the build-up layer is much thinner than that of the core plate, the asymmetrical structure on both sides is less known to cause warpage and overall size. The disadvantages are not only convenient for making high-density package substrates, but also the final product is relatively light and thin.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10,11‧‧‧ core board

12‧‧‧Dielectric layer

100,120,140‧‧‧ openings

13,32‧‧‧ conductive through holes

1‧‧‧Substrate body

14,15‧‧‧ solder mask

150‧‧‧opening

16‧‧‧Line mat

17‧‧‧Ball mat

2‧‧‧Package substrate

18‧‧‧Semiconductor wafer

181‧‧‧ wire

19‧‧‧Packaging materials

20‧‧‧ core layer

20a‧‧‧ first surface

20b‧‧‧second surface

200‧‧‧Setting area

21‧‧‧First line layer

211‧‧‧First finger pad

212‧‧‧First line

31‧‧‧ third circuit layer

22‧‧‧First insulation protection layer

220‧‧‧First insulation protection opening

23‧‧‧ Conductive layer

24‧‧‧First resistance layer

240‧‧‧First opening

25‧‧‧metal layer

26a‧‧‧First dielectric layer

260a‧‧‧First dielectric opening

26b‧‧‧Second dielectric layer

27a‧‧‧Second circuit layer

271a‧‧‧Second finger pad

27b‧‧‧fourth circuit layer

271b‧‧‧Electrical contact pads

28a‧‧‧Second insulation protection layer

280a‧‧‧Second insulation protection opening

28b‧‧‧3rd insulation protection layer

280b‧‧‧3rd insulating protective layer opening

29‧‧‧Second resistance layer

290‧‧‧ second opening

261a‧‧ ‧ gap

30a‧‧‧First metal protective layer

30b‧‧‧Second metal protective layer

1A to 1D are schematic cross-sectional views showing a conventional package substrate, a method of manufacturing the same, and an application example;

2A to 2K are schematic cross-sectional views showing a package substrate of the present invention and a method of manufacturing the same, wherein the second A' is a plan view of Fig. 2A.

20‧‧‧ core layer

20a‧‧‧ first surface

20b‧‧‧second surface

200‧‧‧Setting area

211‧‧‧First finger pad

212‧‧‧First line

31‧‧‧ third circuit layer

22‧‧‧First insulation protection layer

220‧‧‧First insulation protection opening

26a‧‧‧First dielectric layer

260a‧‧‧First dielectric opening

26b‧‧‧Second dielectric layer

27a‧‧‧Second circuit layer

271a‧‧‧Second finger pad

27b‧‧‧fourth circuit layer

271b‧‧‧Electrical contact pads

32‧‧‧Electrical through holes

28a‧‧‧Second insulation protection layer

280a‧‧‧Second insulation protection opening

28b‧‧‧3rd insulation protection layer

280b‧‧‧3rd insulating protective layer opening

261a‧‧ ‧ gap

30a‧‧‧First metal protective layer

30b‧‧‧Second metal protective layer

Claims (21)

A package substrate includes:
The core layer has a first surface and a second surface opposite to each other, and has a crystallizing region and a first circuit layer on the first surface, the first circuit layer having a plurality of first fingers for setting the edge of the crystal region a solder pad, and a first line electrically connected to the first finger pad;
a first insulating protective layer is disposed on the first surface, the first finger pad and the first line, and the first insulating protective layer has a first insulating protective layer opening, so that each of the first finger pads Correspondingly exposed to the first insulating protective layer opening;
a first dielectric layer is disposed on the first surface, the first line, and the first insulating protective layer, and the first dielectric layer has a first dielectric layer opening, so that the first dielectric layer is opened The hole corresponding to the first surface in the crystallizing area, the first finger pad, and the first insulating protective layer;
a second circuit layer is disposed on the first dielectric layer and has a plurality of second finger pads; and a second insulating protection layer is disposed on the second circuit layer and the first dielectric layer, and the The second insulating protective layer has a second insulating protective layer opening, and the second finger pad is exposed to the second insulating protective layer opening. The package substrate of claim 1, wherein the first dielectric layer opening has a notch adjacent to a bottom sidewall of the first dielectric layer of each of the first finger pads. The package substrate of claim 1, wherein the first metal pad and the second finger pad are provided with a first metal protective layer. The package substrate of claim 1, wherein the third circuit layer is disposed on the second surface. The package substrate of claim 4, wherein a second dielectric layer is disposed on the second surface and the third circuit layer, and a fourth circuit layer is disposed on the second dielectric layer. The package substrate of claim 5, further comprising a conductive via extending through the core layer, the first dielectric layer and the second dielectric layer, wherein the conductive via is electrically connected to the first circuit layer and the second a circuit layer, a third circuit layer, and a fourth circuit layer. The package substrate of claim 5, wherein the fourth circuit layer has a plurality of electrical contact pads. The package substrate of claim 7 further comprising a third insulating protective layer disposed on the second dielectric layer and the fourth circuit layer, and the third insulating protective layer has a plurality of third insulating protective layers open The holes are such that the electrical contact pads are correspondingly exposed to the openings of the third insulating protective layer. The package substrate of claim 7, wherein a second metal protective layer is disposed on each of the electrical contact pads. A method for manufacturing a package substrate, comprising:
Providing a core layer having a first surface and a second surface, the first surface having a crystallizing region and a first circuit layer, the first circuit layer having a plurality of rings and a first edge of the crystal region a solder pad, and a first line electrically connected to the first finger pad;
Forming a first insulating protective layer on the first surface, the first finger pad and the first line, and forming a first insulating protective layer opening in the first insulating protective layer, so that each of the first finger pads corresponds to Exposing the opening of the first insulating protective layer;
Forming a metal layer disposed on the first surface, the first finger pad and the first insulating protective layer in a region larger than the crystallizing region;
Forming a first dielectric layer on the first surface, the first line, the first insulating protective layer and the metal layer;
Forming a second circuit layer having a plurality of second finger pads on the first dielectric layer;
Forming a second insulating protective layer on the second circuit layer and the first dielectric layer, and forming a second insulating protective layer opening in the second insulating protective layer, so that the second finger pad and the crystallizing area are The first dielectric layer is exposed to the second insulating protective layer opening;
Removing the first dielectric layer in the seed region to expose the metal layer in the crystal region; and removing the metal layer. The method for manufacturing a package substrate according to claim 10, wherein the process for forming the metal layer comprises:
Forming a conductive layer on the first surface, the first finger pad, the first line and the first insulating protective layer;
Forming a first resist layer on the conductive layer, and forming a first opening in the first resistive layer that is larger than the first crystal region, so that a portion of the conductive layer is correspondingly exposed to the first opening;
Forming the metal layer on the conductive layer in the first opening; and removing the first resist layer and the conductive layer covered thereby, and simultaneously reducing the thickness of the metal layer. The method of manufacturing a package substrate according to claim 11, wherein the removing the metal layer comprises removing the conductive layer covered by the metal layer. The method for manufacturing a package substrate according to claim 10, wherein the first dielectric layer, the second insulating protective layer and the second finger solder are included before removing the first dielectric layer in the crystallographic region. A second resist layer is formed on the pad, and a second opening is formed in the second resist layer to expose the first dielectric layer in the crystallographic region to the second opening. The method for manufacturing a package substrate according to claim 13 is to include removing the second resist layer after removing the metal layer. The method for manufacturing a package substrate according to claim 10, further comprising forming a first metal protection layer on each of the first finger pads and the second finger pads. The method for manufacturing a package substrate according to claim 10, further comprising forming a third circuit layer on the second surface. The method for manufacturing a package substrate according to claim 16, further comprising forming a second dielectric layer on the second surface and the third circuit layer, and forming a fourth circuit layer on the second dielectric layer. The method for manufacturing a package substrate according to claim 17, further comprising forming a conductive via extending through the core layer, the first dielectric layer and the second dielectric layer, and electrically connecting the conductive via to the first circuit layer a second circuit layer, a third circuit layer, and a fourth circuit layer. The method of manufacturing a package substrate according to claim 17, wherein the fourth circuit layer has a plurality of electrical contact pads. The method for manufacturing a package substrate according to claim 19, further comprising forming a third insulating protective layer on the second dielectric layer and the fourth circuit layer, and forming a plurality of third insulating protective layers in the third insulating protective layer Opening the holes so that the electrical contact pads are correspondingly exposed to the openings of the third insulating protective layer. The method for manufacturing a package substrate according to claim 19, further comprising forming a second metal protective layer on each of the electrical contact pads.