200941680 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝基板及其製法 ’尤指一種高 散熱封裝基板及其製法。 【先前技術】 由於電子產品曰趨輕薄短小，故對於用於承載半導體 晶片或電子元件之封裝基板亦需隨之縮減，而半導體封裝 技術的演進已開發出不同的封褒型態，其中如球栅陣列式 ❹咖11 gi*idarray’ BGA)’係為一種先進的半導體封裝技 術，能在相同單位面積之封裝基板上可以容納更多輸入/ 輸出連接端（I/O connecti〇n)以符合高度集積化 (Integration)之半導體晶片所需。200941680 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a package substrate and a method of manufacturing the same, and more particularly to a high heat dissipation package substrate and a method of fabricating the same. [Prior Art] Since electronic products are becoming lighter and thinner, package substrates for carrying semiconductor wafers or electronic components are also required to be reduced, and the evolution of semiconductor packaging technology has developed different sealing types, such as balls. Grid array type 11 gi*idarray 'BGA)' is an advanced semiconductor packaging technology that can accommodate more input/output connections (I/O connecti〇n) on the same unit area of the package substrate. Highly integrated semiconductor wafers are required.
Window BGA)半導體封裝爲例， 封裝產品之封裝尺寸，因而得以 以開窗型球栅陣列式（Window BaU Grid Array ，Window BGA) is a case of a semiconductor package that can be packaged in a window-type ball grid array (Window BaU Grid Array,
110643 俾於後續之打線作業（WireB〇ndi叩) 路板之打線墊均具有相同性質之材質 5 200941680 -而有較佳之結合性，以提昇兩者之電性 請參閱第1圖，係為習知開窗接。 ' 白夭開*型球柵陣列式（Window 之==封裝結構之剖視圖;習知開窗型球栅陣列式 構，係包含基板1〇以及半導體晶片η， 體！具有至少一貫穿之開口1〇°，而該半導 llb曰曰、有一作用®lla及與其相對應之非作用面 以=用面lla具複數電極墊lu，且該半導體晶片 1 (、作用面lla接置於該基板10之一表面，並封住該 :::::口100 一端，以藉由打線連接(wire b°nding) 連接^f12穿過該開σ⑽’使該半導體晶片11電性 曰^基板10另-表面之電性接觸㈣，並於該半導體 及導線12上形成封裝材料15，其中該電性接觸 3上形成係為錄/金層之金屬保㈣14，使該導線a =基板10之電性接觸墊13均具有相同.性質之材質而具有 之、° σ丨生，另外，於該基板10上其餘電性接觸墊13 ❹之金屬保護層14上另接置有一導電元件16。 惟於前述結構中，該半導體晶片u係藉由該導線12 穿過該開口 100以電性連接該基板10另一表面之電性接 觸墊13’使該導線12之長度增加而影響訊號傳輸速度盘 且該半導體晶片u係接置於該基板1〇之開口 1〇〇 端，並以封裝材料15覆蓋該導線12及半導體晶片u， 使得整體之封裝尺寸較高，且散熱不易。 因此，如何提出一種高散熱封裝基板及其製法，以克 服習知開窗型球柵陣列式之半導體封裝結構中，整體之封 6 110643 200941680 裝尺寸較同、不易散熱等問題，實已成 ..決之課題。 ⑴菜界亟待解 •【發明内容】 鑒f上述習知技術之缺失，本發明之主要目的在於接 供-種尚散熱封裝基板及其製法’具有 、 提升散熱效率，進而捭進桩署I μ ψ $煎…功此，月匕 本發明之又 +導體晶片的效能。 本月之又—目的在於提供一種 其製法，能降低封裝基板之整體厚度。 丨裝基板及 〇其制另一目的在於提供-種高散熱封裝基板及 其衣法，此降低訊號損失及增快訊號傳輪速度。 為達土述及其他目的，本發明提出一種高散熱封裝基 ’係匕括.核心板’係具有第一表面及相對應之第二表 面’於該第一表面及第二表面上分別設有第一線路層及第 -線路層，且該第一線路層具有一晶片置放區；第一壓合 層，係設於該第一表面及第一線路層上’並具有第一開口 ❹以顯露該晶片置放區’且於該第一開口之孔壁及晶片置放 區上設有一導體層；第二壓合層，係設於該第二表面及第 二綠路層上；第三線路層，係設於該第一壓合層上，並具 有複數第一打線墊及位於該第一開口周圍之複數第二^ 線墊，且該第二打線墊係連接該第一開口之孔壁上之導體 層；第四線路層，係設於該第二壓合層上，並具有複數焊 球墊；第一防焊層，係設於該第一壓合層及第三線路層 上，並具有第二開口，以顯露該導體層及該第二打線墊， 且具有複數第一開孔，以對應顯露各該第一打線墊；以及 110643 7 200941680 第二防焊層，係設於該第二壓合層及第四線路層上，並具 有複數第二開孔，以對應顯露各該焊球塾。 依上述結構，該核心板係為具有内層線路之線路板或 絕緣板。 又依上述結構，復包括導電通孔’係貫穿該核心板、 第一及第二壓合層，並電性連接該第一、第二、第三及第 四線路層；復包括金屬保護層，係設於該第一打線;、第 二打線墊、導體層及焊球墊上。 ❺ 本發明復提供一種高散熱封裝基板之製法，係包 提供一具有相對應第一表面及第-表 ' ❹ 一不私w久乐一录面之核心板，於該第 一表面及第二表面上分別形成第—線路層及第二線路 層，且該第一線路層具有一晶片置放區；於該第一表面及 第一線路層上形成第一壓合層，並於該第二表面及第二線 路層上形成第二壓合層；於該第一壓合層形成一第一開口 以顯露該晶片置放區；於該第一壓合層上形成第三線路 層，該第三線路層具有複數第一打線墊及位於該第一開口 周圍之複數第二打線塾，且於該第一開口之孔壁及晶片置 放區上形成一導體層，該導體層並連接該第二打線墊，且 於該第二壓合層上形成第四線路層，該第四線路層具有複 數焊球墊；於該第一壓合層及第三線路層上形成第一防焊 層：且於第一防焊層中形.成第二開口，以顯露該導體層及 打線塾ϋ形成複數第一開孔，以對應顯露各該第一 1»’友塾’以及於該第二壓合層及第四線路層上形成第二防 焊層，並於第二防焊層中形成複數第二開孔，以對應顯露 110643 8 200941680 各該焊球墊。 ， 依上述之製法’該核心板係為具有内層線路之線路板 或絕緣板。 一依上述之製法’復包括形成貫穿該核心板第一及第 二屋合層之通孔，於該通孔形成導電通孔，以電性連接該 第一、第二、第三及第四線路層。 依上述製法，復包括於該第一打線墊、第二打線墊、 導體層及焊球墊上形成金屬保護層。 ❹纟發s之间散熱封裝基板及其製法，係將半導體晶片 置於該封裝基板之第二開口及第一開口中，以降低封裝厚 度’並縮短導線長度以增加傳輸速度，且該封裝基板係以 晶片置放區之導體層接置半導體晶片，故可增加散熱效 果又該第一開口之孔壁所設導體層復可供遮蔽外界電磁 波干擾，並電性連接該第二打線墊，以供接地（Gr_ding) 之用’可減少導電通孔之數目，進而可提升整體基板之 0佈線密度° 【實施方式】 、以下係藉由特定的具體實例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 請參閱第2A至21圖，係顯示本發明高散熱封裝基板 及其製法之剖面示意圖。 如第以圖所*，首先，提供一具有第一表面2〇&及 相對應之第二表面2〇b之核心板20,並於該第一表面2〇a 110643 9 200941680 及第二表面20b分別形成第一及第二線路層21a 21b，且 ，該第一線路層21a具有一晶片置放區211a，該核心板2〇 例如為具有内層線路之線路板或絕緣板。 如第2B圖所示，於該核心板2〇之第一表面2〇a及第 一線路層21a上形成第一壓合層22a，又於該核心板2〇 之第二表面20b及第二線路層21b上形成第二壓合層 22b，該第一及第二壓合層22a22b上係可先形成薄金屬 層221a，221b，而為樹脂壓合銅箔（RCC)。 ® 如第2C圖所示，該第一壓合層22a及其上之薄金屬 層221a形成一第一開口 22〇a以顯露該晶片置放區 211a ;又於該核心板2〇、第一壓合層22a與其上之薄金 屬層221a、及第二壓合層22b與其上之薄金屬層221b中 以機械鑽孔形成至少一通孔2〇〇。 如第2D圖所示，於該薄金屬層221a，221b、通孔2〇〇 及第一開口 220a之孔壁、及晶片置放區2Ua上形成一導 ❾電種層23,該導電晶種層23主要作為後述電鑛金屬材 料所需之電流傳導路徑’其可由金屬或沉積數層金屬層所 構成，如選自銅、錫、鎳、鉻、鈦、銅_鉻等單層或多層 結構，或可使用例如聚乙炔、聚苯胺或有機硫聚合物等導 電高分子材料。 如第2E圖/斤示，於該導電晶種層23上利用印刷、旋 塗或貼合等方式形成光阻層24，該光阻層24係為乾膜戋 液態光阻等，且該光阻層24係經圖案化以形成複數光阻 層開口區240 ’以顯露該通孔2〇〇之孔壁、第一開口 110643 10 200941680 之孔壁、及部份第一及第二壓合層22a，22b上之導電晶種 層23。 如第2F圖所示，藉由該導電晶種層23作為電鍍之電 流傳導路徑，以於該光阻層開口區24〇中之導電晶種層 23上電鍍形成金屬層25,該金屬層25之材料可為諸如 鉛、錫、銀、銅 '金、鉍、銻、鋅、鎳、锆、鎂、銦、碲 以及鎵等金屬之其中H，依實際操作之經驗，銅為 成熟之電鑛材料且成本較低，但非以此為限。 〇110643 Wire 后续 后续 Wire Wire Wire Wire Wire Wire Wire Wire Wire Wire Wire Wire Wire 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 Know the open window. 'White 夭* type ball grid array type (Window == sectional view of package structure; conventional window type ball grid array structure, including substrate 1 〇 and semiconductor wafer η, body! has at least one through opening 1 The semiconductor wafer 1 has a plurality of electrode pads 1 and the active surface 11a is placed on the substrate 10, and the semiconductor wafer 1 is disposed on the substrate 10 One surface, and sealing the end of the ::::: port 100, to connect the semiconductor wire 11 through the opening σ(10)' by wire bonding (wire b°nding) The electrical contact of the surface (4), and the encapsulation material 15 is formed on the semiconductor and the wire 12, wherein the electrical contact 3 is formed with a metal (four) 14 which is a recording/gold layer, so that the wire a = the electrical contact of the substrate 10. The pads 13 all have the same material and have a σ 丨, and a conductive element 16 is additionally disposed on the metal protective layer 14 of the remaining electrical contact pads 13 on the substrate 10. However, the foregoing structure The semiconductor wafer u is electrically connected to the base by the wire 12 passing through the opening 100. The electrical contact pad 13' on the other surface of the board 10 increases the length of the wire 12 to affect the signal transmission speed disk and the semiconductor chip u is placed at the opening 1 end of the substrate 1 and is provided with the encapsulation material 15 Covering the wire 12 and the semiconductor wafer u, the overall package size is high, and heat dissipation is not easy. Therefore, how to provide a high heat dissipation package substrate and a manufacturing method thereof to overcome the conventional windowed ball grid array type semiconductor package structure The whole seal 6 110643 200941680 The size of the package is relatively the same, it is not easy to dissipate heat, etc. It has become a problem. (1) The vegetable world is to be solved. [Invention content] The main purpose of the invention is the lack of the above-mentioned conventional technology. In the case of the supply-type heat-dissipating package substrate and its manufacturing method, it has the ability to improve the heat dissipation efficiency, and then into the pile of I μ ψ 煎 煎 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功 功The purpose is to provide a method for reducing the overall thickness of the package substrate. The armor substrate and the other purpose of the method are to provide a high heat dissipation package substrate and a clothing method thereof, thereby reducing signal loss. And increasing the speed of the signal transmission. For the purpose of the present invention, the present invention provides a high heat dissipation package base. The core plate has a first surface and a corresponding second surface on the first surface. And the first circuit layer and the first circuit layer are respectively disposed on the second surface, and the first circuit layer has a wafer placement area; the first pressing layer is disposed on the first surface and the first circuit layer And having a first opening 显 to expose the wafer placement area ′ and providing a conductor layer on the hole wall and the wafer placement area of the first opening; the second pressing layer is disposed on the second surface and a second circuit layer is disposed on the first pressing layer, and has a plurality of first wire mats and a plurality of second wire pads located around the first opening, and the second wire pad a conductor layer connected to the wall of the first opening; the fourth circuit layer is disposed on the second pressing layer and has a plurality of solder ball pads; the first solder resist layer is disposed on the first pressure And a second opening on the layer and the third circuit layer to expose the conductor layer and the second wire pad, And having a plurality of first openings for correspondingly exposing each of the first wire pads; and 110643 7 200941680, the second solder resist layer is disposed on the second pressing layer and the fourth circuit layer, and has a plurality of second openings Holes are used to correspondingly expose each of the solder balls. According to the above structure, the core board is a circuit board or an insulating board having an inner layer wiring. According to the above structure, the conductive via hole extends through the core board, the first and second pressing layers, and is electrically connected to the first, second, third, and fourth circuit layers; and the metal protective layer is further included , is disposed on the first wire; the second wire pad, the conductor layer and the solder ball pad. The present invention provides a method for manufacturing a high heat dissipation package substrate, and the package provides a core board having a corresponding first surface and a first surface and a second surface, on the first surface and the second surface Forming a first circuit layer and a second circuit layer on the surface, and the first circuit layer has a wafer placement area; forming a first bonding layer on the first surface and the first circuit layer, and in the second Forming a second pressing layer on the surface and the second circuit layer; forming a first opening in the first pressing layer to expose the wafer placement area; forming a third circuit layer on the first bonding layer, the first The three-layer layer has a plurality of first wire pads and a plurality of second wire ridges around the first opening, and a conductor layer is formed on the hole wall and the wafer placement area of the first opening, and the conductor layer is connected to the first layer a second wire pad, and a fourth circuit layer formed on the second bonding layer, the fourth circuit layer having a plurality of solder ball pads; forming a first solder resist layer on the first bonding layer and the third circuit layer: And forming a second opening in the first solder resist layer to expose the conductor layer and Forming a plurality of first openings to correspondingly expose each of the first 1»' friends and forming a second solder resist layer on the second press layer and the fourth circuit layer, and forming a second solder resist layer on the second solder resist layer A plurality of second openings are formed in the layer to correspondingly expose 110643 8 200941680 each of the solder ball pads. According to the above method, the core board is a circuit board or an insulating board having an inner layer. The method according to the above method comprises: forming a through hole penetrating through the first and second roof layers of the core board, forming a conductive via hole in the through hole to electrically connect the first, second, third and fourth Line layer. According to the above manufacturing method, a metal protective layer is formed on the first bonding pad, the second bonding pad, the conductor layer and the solder ball pad. The heat dissipation package substrate between the hair s and the manufacturing method thereof, the semiconductor wafer is placed in the second opening and the first opening of the package substrate to reduce the package thickness 'and shorten the wire length to increase the transmission speed, and the package substrate The semiconductor wafer is connected to the conductor layer of the wafer placement area, so that the heat dissipation effect can be increased, and the conductor layer provided on the hole wall of the first opening can be shielded from external electromagnetic wave interference, and electrically connected to the second wire pad to The use of grounding (Gr_ding) can reduce the number of conductive vias, thereby increasing the wiring density of the entire substrate. [Embodiment] Hereinafter, embodiments of the present invention will be described by way of specific specific examples, which are familiar with the art. Other advantages and effects of the present invention will be readily apparent to those skilled in the art from this disclosure. Referring to Figures 2A through 21, there are shown schematic cross-sectional views of a high heat dissipation package substrate of the present invention and a method of fabricating the same. As shown in the first figure, first, a core plate 20 having a first surface 2〇& and a corresponding second surface 2〇b is provided, and on the first surface 2〇a 110643 9 200941680 and the second surface The first and second wiring layers 21a to 21b are formed, respectively, and the first wiring layer 21a has a wafer placement area 211a, which is, for example, a wiring board or an insulating board having an inner wiring. As shown in FIG. 2B, a first pressing layer 22a is formed on the first surface 2〇a and the first circuit layer 21a of the core board 2, and a second surface 20b and a second surface of the core board 2〇 are formed. A second pressing layer 22b is formed on the circuit layer 21b. The first and second pressing layers 22a22b are formed with a thin metal layer 221a, 221b and a resin laminated copper foil (RCC). As shown in FIG. 2C, the first bonding layer 22a and the thin metal layer 221a thereon form a first opening 22〇a to expose the wafer placement area 211a; and the core board 2〇, first The press-bonding layer 22a and the thin metal layer 221a thereon, and the second press-bonding layer 22b and the thin metal layer 221b thereon are mechanically drilled to form at least one through hole 2〇〇. As shown in FIG. 2D, a thin conductive layer 23 is formed on the thin metal layers 221a and 221b, the via hole 2 and the hole wall of the first opening 220a, and the wafer placement area 2Ua. The layer 23 is mainly used as a current conduction path required for the electro-mineral metal material described later. It may be composed of a metal or a plurality of deposited metal layers, such as a single layer or a multilayer structure selected from the group consisting of copper, tin, nickel, chromium, titanium, and copper-chromium. Or, a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer may be used. As shown in FIG. 2E, the photoresist layer 24 is formed on the conductive seed layer 23 by printing, spin coating or lamination, and the photoresist layer 24 is a dry film, a liquid photoresist, etc., and the light is The resist layer 24 is patterned to form a plurality of photoresist layer open regions 240' to expose the via walls of the vias 2, the first opening 110643 10 200941680, and a portion of the first and second bonding layers Conductive seed layer 23 on 22a, 22b. As shown in FIG. 2F, the conductive seed layer 23 is used as a current conduction path for electroplating to form a metal layer 25 on the conductive seed layer 23 in the open region 24 of the photoresist layer. The metal layer 25 is formed. The material may be such as lead, tin, silver, copper 'gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, antimony and gallium. Among the metals, according to the experience of actual operation, copper is a mature electric mine. Material and low cost, but not limited to this. 〇
如第2G圖所示，接著，移除該光阻層24及其所覆蓋 之導電晶種層23及薄金屬層221a，221b，以於該第一及 第二表面20a，20b上的第一及第二壓合層22a22b上分別 形成第三及第四線路層21C，21d，且於該通孔2〇〇中形成 導電通孔21e，以電性連接該第一、第二、第三及第四線 路層 21a，21b，21c，21d;其中， 第一及第二打線墊211c，212c， 該第二線路層2.1 c並具有 且於該第一開口 220a之 孔壁及晶片置放區211a上形成導體層213c，該導體層 213c係連接該第二打線墊2i2c;該第四線路層21d並具 有複數焊球墊211d。 如第2H圖所示，於該第一壓合層22a與該第三線路 層21c上形成第一防焊層26a，該第一防焊層26&中並形 成第二開口 260a ’以顯露該第二打線墊212c及導體層 213c，且形成複數第一開孔261a，以對應顯露各該第一 打線墊211c ’·並於該第二壓合層22b與第四線路層2ld 上形成第二防谭層26b，該第二防焊層26b並形成複數第 11 110643 200941680 二開孔261b’以對應顯露各該焊球墊211(1之部分表面， •，且及第二防焊層26a，26b並填人該導電通孔W 之工隙中，復於該導體層213c、焊球塾2Ud、第一及第 二打線f 2UC，212C上形成金屬保護層27,以完成本發 明之尚散熱封裝基板，其中該金屬保護層27之材料係選 自銅、錫、鉛、銀、鎳、金、翻之組合及上述成份之合金。 如第21圖所示，係本發明之高散熱封裝基板之應用 貫列’"係於該第一開口 22〇a中之導體層2Uc上接 ❹導體晶片28,該半導體晶片28具有—作用面咖及與其 相對應之非作用面28b，該作用面28a具複數電極塾如 且該半導體晶片28係以其非作用面28|3接置於該第一開 口 22〇a中之導體層213c上，並於該第一打線墊21lc之 金屬保護層27及半導體晶片28之電極墊281之間、以及 第二打線墊212c之金屬保護層27及半導體晶片^之電 極墊281之間以複數導線282(如金屬導線）電性連接俾 ❹使該半導體晶月28藉由該些導線282電性連接該第一打 線墊211c，及使該半導體晶片28電性連接該第二打線墊 212c，以進行接地（Gr〇unding)，並以該導體層sue進行 散熱及遮蔽外界電磁波之干擾，以保護該半導體晶片M。 β又於該焊球墊211d之金屬保護層27上形成係為錫球 之焊接元件29，以供電性連接一印刷電路板；於該半導 體晶片28、導線282、第一及第二打線墊211c 2l2J上包 覆有封裝材料30，以形成置有半導體元件之高散熱封^ 結構。 、 110643 12 200941680 本發明復提供一種高散熱封裝基板，如第2H圖所 不，係包括：核心板20，係具有第一表面2〇a及相對應 之第二表面20b，於該第一表面2〇a及第二表面2〇b上分 別s又有第一線路層21 a及第二線路層21 b，且該第一線路 層21a具有一晶片置放區2lia ;第一壓合層22a，係設於 該第一表面20a及第一線路層21a上，並具有第一開口 220a以顯露§亥晶片置放區21la，且於該第一開口 220a 之孔壁及晶片置放區211a上設有一導體層213c;第二壓 ❹合層22b，係設於該第二表面2〇b及第二線路層21b上； 第二線路層21c，係設於該第一壓合層22a上，並具有複 數第一打線墊211c及位於該第一開口 22〇a周圍之複數第 一打線墊212c，且該第二打線墊212c係連接該第一開口 220a之孔壁上之導體層213c;第四線路層21d，係設於 該第二壓合層22b上’並具有複數焊球墊21 id ;第一防 焊層26a，係設於該第一壓合層22a及第三線路層21c ❹上，並具有第二開口 260a，以顯露該導體層213c及第二 打線塾212 c ’且具有複數第一開孔2 61 a以對應顯露各該 第一打線墊211c;以及第二防焊層26b，係形成於該第二 壓合層22b及第四線路層21d上，並具有複數第二開孔 261b ’以對應顯露各該焊球墊21 Id。 依上述結構’該核心板20係為具有内層線路之線路 板或絕緣板。 又依上述結構，復包括導電通孔21e，係貫穿該核心 板20、第一及第二壓合層22 a，22b ’並電性連接該第一、 110643 13 200941680 第二、第三及第四線路層21a，21b，21c, 21d ;復包括金屬 保護層27’係設於該第一打線墊21ic、第二打線墊2i2c、 導體層213c及焊球塾211d上。 本發明之南散熱封裝基板及其製法，係可將一半導體 晶片置於該封裝基板之第二開口及第一開口中，以降低封 裝厚度，並縮短導線長度以增加傳輸速度，且該封裝基板 係以晶片置放區之導體層接置半導體晶片’故可增加散熱 效果，又該第一開口之孔壁所設導體層復可供遮蔽外界電 Ο磁波干擾，並電性連接該第二打線墊，以供接地 (Grounding)之用，可減少導電通孔之數目，進而可提 整體基板之佈線密度。 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在不 ^本發明之精神及範訂，對上..述實施例進行修飾與改 變。因此，本發明之權利保護範圍，應如後 範圍所列。 τ印專利 【圖式簡單說明】 圖；係為習用底穴置晶型球㈣型式封褒結構 高散熱封裝基板及其製法 第2A至21圖係為本發明之 之剖面示意圖。 【主要元件符號說明】 10 基板 100 開口 110643 14 200941680 11，28 半導體晶片 11a, 28a 作用面 lib, 28b 非作用面 111,281 電極墊 12, 282 導線 13 電性接觸墊 14, 27 金屬保護層 15, 30 封裝材料 ❹16 導電元件 20 > 核心板 200 通孔 20a 第一表面 20b 第二表面 21a 第一線路層 211a 晶片置放區 21b Q 21c 第二線路層 第三線路層 211c 第一打線塾 212c 第二打線墊 213c 導體層 21d 第四線路層 211d 焊球墊 21e 導電通孔 22a 第一壓合層 200941680 221a,221b 薄金屬層 220a 第一開口 22b 第二壓合層 23 導電晶種層 24 光阻層 240 光阻層開口區 25 金屬層 26a 第一防悍層 © 260a 第二開口 261a 第一開孔 26b 第二防焊層 261b 第二開孔 29 焊接元件 ❿ 16 110643As shown in FIG. 2G, the photoresist layer 24 and the conductive seed layer 23 and the thin metal layers 221a, 221b covered thereon are removed to be first on the first and second surfaces 20a, 20b. And forming a third and fourth circuit layer 21C, 21d on the second pressing layer 22a22b, and forming a conductive via 21e in the through hole 2〇〇 to electrically connect the first, second, and third The fourth circuit layer 21a, 21b, 21c, 21d; wherein, the first and second wire bonding pads 211c, 212c, the second circuit layer 2.1c has a hole wall and a wafer placement area 211a of the first opening 220a A conductor layer 213c is formed thereon, and the conductor layer 213c is connected to the second wire pad 2i2c; the fourth circuit layer 21d has a plurality of solder ball pads 211d. As shown in FIG. 2H, a first solder resist layer 26a is formed on the first bonding layer 22a and the third wiring layer 21c, and a second opening 260a' is formed in the first solder resist layer 26& a second wire pad 212c and a conductor layer 213c, and a plurality of first openings 261a are formed to correspondingly expose the first wire pads 211c'· and form a second on the second bonding layer 22b and the fourth circuit layer 2ld. The second solder resist layer 26b forms a plurality of 11110643 200941680 two openings 261b' to correspondingly expose portions of the solder ball pads 211 (1, and the second solder resist layer 26a, 26b is filled in the working gap of the conductive via W, and a metal protective layer 27 is formed on the conductive layer 213c, the solder ball 2Ud, and the first and second bonding wires f 2UC, 212C to complete the heat dissipation of the present invention. a package substrate, wherein the material of the metal protection layer 27 is selected from the group consisting of copper, tin, lead, silver, nickel, gold, a combination of turns, and an alloy of the above components. As shown in FIG. 21, the high heat dissipation package substrate of the present invention Applying a tandem '" to the conductor layer 2Uc in the first opening 22〇a, which is connected to the conductor wafer 28, The conductor wafer 28 has an active surface and a corresponding non-active surface 28b. The active surface 28a has a plurality of electrodes, for example, and the semiconductor wafer 28 is placed at the first opening 22 with its non-active surface 28|3. The conductive layer 213c in a, between the metal protective layer 27 of the first bonding pad 21lc and the electrode pad 281 of the semiconductor wafer 28, and the metal protective layer 27 of the second bonding pad 212c and the electrode pad of the semiconductor wafer The plurality of wires 282 (such as metal wires) are electrically connected between the 281, so that the semiconductor crystal 28 is electrically connected to the first wire pad 211c by the wires 282, and the semiconductor wafer 28 is electrically connected to the first The second wire pad 212c is grounded (Gr〇unding), and the conductor layer sue is used for heat dissipation and shielding external electromagnetic waves to protect the semiconductor wafer M. The β is further on the metal protection layer 27 of the solder ball pad 211d. Forming a solder ball 29 as a solder ball to electrically connect a printed circuit board; the semiconductor wafer 28, the wire 282, and the first and second wire pads 211c 211J are coated with a sealing material 30 to form a semiconductor. High component The present invention provides a high heat dissipation package substrate, as shown in FIG. 2H, comprising: a core plate 20 having a first surface 2〇a and a corresponding second surface 20b, And the first circuit layer 21 a and the second circuit layer 21 b respectively on the first surface 2 〇 a and the second surface 2 〇 b, and the first circuit layer 21 a has a wafer placement area 2 lia; A pressing layer 22a is disposed on the first surface 20a and the first circuit layer 21a, and has a first opening 220a for exposing the DD cell placement area 21la, and the hole wall and the wafer of the first opening 220a A conductive layer 213c is disposed on the placement area 211a; the second pressure bonding layer 22b is disposed on the second surface 2b and the second circuit layer 21b; and the second circuit layer 21c is disposed on the first pressure The first layer bonding pad 211c and the plurality of first bonding pads 212c located around the first opening 22〇a, and the second bonding pad 212c is connected to the hole wall of the first opening 220a. a conductor layer 213c; a fourth circuit layer 21d is disposed on the second pressing layer 22b' and has a plurality of solder ball pads 21 id; The solder resist layer 26a is disposed on the first bonding layer 22a and the third wiring layer 21c, and has a second opening 260a to expose the conductor layer 213c and the second wiring layer 212c' and has a plurality of first The opening 2 61 a is correspondingly exposed to each of the first bonding pads 211c; and the second solder resist 26b is formed on the second pressing layer 22b and the fourth wiring layer 21d, and has a plurality of second openings 261b 'To correspondingly expose each of the solder ball pads 21 Id. According to the above structure, the core board 20 is a wiring board or an insulating board having an inner layer wiring. According to the above structure, the conductive via 21e is further included through the core board 20, the first and second pressing layers 22a, 22b' and electrically connected to the first, 110643 13 200941680 second, third and third The four circuit layers 21a, 21b, 21c, 21d are provided on the first wire pad 21ic, the second wire pad 2i2c, the conductor layer 213c, and the solder ball 211d. The south heat dissipating package substrate of the present invention can be formed by placing a semiconductor wafer in the second opening and the first opening of the package substrate to reduce the package thickness and shorten the wire length to increase the transmission speed, and the package substrate The semiconductor wafer is connected to the conductor layer of the wafer placement area, so that the heat dissipation effect can be increased, and the conductor layer provided on the hole wall of the first opening is shielded from shielding the external electromagnetic wave and electrically connected to the second wire. The pad is used for grounding to reduce the number of conductive vias and thereby increase the wiring density of the entire substrate. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Any person skilled in the art can modify and change the above described embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as listed in the following range. τ印专利 [Simple diagram of the drawing] Fig. 2 is a conventional bottom hole crystal ball (four) type sealing structure High heat dissipation package substrate and its preparation method 2A to 21 are schematic cross-sectional views of the present invention. [Main component symbol description] 10 substrate 100 opening 110643 14 200941680 11,28 semiconductor wafer 11a, 28a active surface lib, 28b non-active surface 111, 281 electrode pad 12, 282 wire 13 electrical contact pad 14, 27 metal protective layer 15, 30 Packaging material ❹16 conductive element 20 > core board 200 through hole 20a first surface 20b second surface 21a first line layer 211a wafer placement area 21b Q 21c second line layer third line layer 211c first line 塾 212c second Wire pad 213c conductor layer 21d fourth circuit layer 211d solder ball pad 21e conductive via 22a first bonding layer 200941680 221a, 221b thin metal layer 220a first opening 22b second bonding layer 23 conductive seed layer 24 photoresist layer 240 photoresist layer open area 25 metal layer 26a first anti-corrugated layer © 260a second opening 261a first opening 26b second solder resist layer 261b second opening 29 soldering element ❿ 16 110643