TW201227908A - Embedded electronic device package structure - Google Patents

Abstract

An embedded electronic device package structure is provided with a metal film covering the top surface and/or side surfaces of the embedded electronic device. The metal film enveloping the embedded electronic device functions as electromagnetic interference shield.

Description

201227908

P51990051TW 35306twf.doc/I VI. Description of the Invention: [Technical Field of the Invention] Structure and in particular The present invention relates to an electronic component sealing pen. A buried electronic component packaging structure. [Prior Art] For the current electromagnetic (four) gamma (10) of electronic products, the net causes the electronic device '==〇nyetiC to decrease'. The common means is set on the substrate; =; = cover is used as electromagnetic interference prevention = 3 = = In the case of the overall thickness of the package, it is necessary to investigate the buried electricity. [Invention] The present invention provides an electronic component package having: a member, a first-shielding layer, and a first-west, a west-on-substrate and a power supply. Sexual link to. 】 〖Electronic reading on the substrate, and at least package ~ flute one: board _ 1 shielding layer, placed on the side of the 盥 柘 柘 柘 柘 之上 之上 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 之上 之上 。 。 。 。 。 。 。 4 a dielectric structure overlying the substrate and covering the first electronic component. Shielding layer Electronic _ _ buried electronic components dragon body, with at least - raw: ΐ; layer and a colloid. The electronic component is disposed on the second stack and is transferred to 4 layers, and the layer has at least - dielectric junction 201227908

P51990051TW 35306twf.doc/I and a metal pattern structure are disposed under the dielectric structure. The masking layer is disposed on the stack to cover at least the upper surface of the electronic component and the metal pattern structure of the surface and a portion of the laminate. The encapsulant is disposed on the laminate and encapsulates the electronic component and the shielding layer. Based on the above, in the method of fabricating the electronic component package of the present invention, θ covers at least one shielding layer between the upper and lower layers of the electronic component before or during lamination. Above or in order to make the above features of the present invention more comprehensible, the following detailed description will be described in detail with reference to the accompanying drawings. [Embodiment] The present invention realizes an EMI shielding structure in a buried electronic component packaging process. The main reason is that the illuminable electronic component company should cover at least the metal film, = the electronic component is covered by the metal film and is free from electromagnetic interference, and the electric tree material is strengthened. The compound (4) can also be electroplated, or attached with a film or laminated with a metal film to the embedded type, and the film can be designed to improve the pattern. Anti-mite effect: and the possibility of bubble generation during the process of attaching the film. 1A to 1 are schematic cross-sectional views showing a manufacturing process of a package structure according to an embodiment of the present invention. Here, the sub-piece can be a semiconductor wafer or a semiconductor component, and examples thereof include a transistor such as a transistor, a diode, and a light-emitting diode aEn.

201227908 P51990051TW 35306twf.doc/I Dynamic components such as resistors, capacitors or inductors. Referring first to FIG. 1A, first, a substrate 1 is provided, wherein the substrate 100 has a laminate 101 of at least one dielectric film 1〇2 and an adhesive layer 1〇4. The material of the dielectric film 1〇2 is, for example, polyimide or benzocycene butene (BCB), or ABF, and the material of the adhesive layer 104 is, for example, a thermosetting adhesive or a thermoplastic adhesive. Next, the electronic components 10a/106b/106c are sequentially disposed on the adhesive layer 104 face-down. In this embodiment, the electronic component 106a is, for example, a 1C chip, the electronic component 106b is, for example, a passive component, and the electronic component 106c is, for example, a radio frequency (RF) chip. By "face down" is meant contacting the contact end 105 of the electronic component with the upper surface of the adhesive layer 104. However, the types, relative positions, or numbers of actual electronic components are not limited to those described in this case, and may be adjusted or changed depending on the actual needs of the product. Next, referring to FIG. 1B, a shielding layer 110 is formed on the upper surface of the adhesive layer 104 to cover the electronic components 10a/106b/106c. The material of the shielding layer 110 is, for example, a metal or a copper metal. The method of forming the masking layer 110 is, for example, electroless plating or subtraction: a sputter type electroplating or copper or other metal such as a silver (Ag) nickel (Ni) film, or a plurality of metal films onto the surface of an electronic component' or A copper tape or a non-metallic conductive carbon tape is attached to the surface of the electronic component. The masking layer 110 may further include an adhesive layer (not shown) to help flatten the attachment to the surface of the electronic component. The masking layer 110 covers at least the upper surface and the partial side surface of the electronic component 106a/106b/106c and the partial laminate 101. Although the shielding layer 110 is represented by a "layer", it may actually be a discontinuous, discrete metal pattern 201227908

P51990051TW 35306twf.doc/I Block, not a continuous film layer. Generally speaking, corresponding to the member, the shielding layer 110 includes different pattern blocks, but the figures include at least the electronic components corresponding to the corresponding covering, so as to cover the upper surface and the partial side of the electronic component. Surface ( = layer surface). In other words, the masking layer 110 is preferably fully packaged; the H-clamping member 106 provides the effect of electromagnetic interference shielding, or the effect of the corresponding electronic component just over the entire upper surface and at least obscuring it. In addition, in other embodiments, the mask may have a design that depends on the frequency of the desired mask.

2A-2E are schematic diagrams of a pattern block included in a portion of the mask layer to display different patterns of different electronic components corresponding to the mask layer: X: a cross-shaped metal pattern 21〇 shown in FIG. 2A, a dotted line region The size of the upper surface of the electronic component is indicated, and the shielding layer (the cross-shaped metal pattern 21〇) can completely cover the upper surface and the four side surfaces of the electronic component. With respect to Fig. 2A', it can be seen that the metal pattern 21 of Fig. 2B is designed such that the shape, size and distribution density of the holes 21a' having the uniform distribution of the holes can be changed by the frequency of the desired shielding. The metal pattern 21〇 of FIGS. 2C-2D is designed to have an equidistantly distributed, staggered grid-like gap 21b/21c′ but the grid-like gap design arrangement is different. The T-shaped metal pattern 21 shown in FIG. 2E is Consisting of equidistantly distributed, staggered mesh metal strips 21d (also considered to have checkerboard spaces) 'the dotted line area indicates the surface size of the electronic component, and the τ-shaped disc pattern 210 can completely cover the electronic component Surface and three solid side surfaces. The ratio of the width d of the metal strip 21d to the interval D of the metal stripe 21d can be more dynamically designed depending on the frequency of the desired shading. Figure 2A and Figure 2E 201227908

P51990051TW 35306twf.doc/I can be viewed as a set of holes of two different shapes and sizes. Here, since the shielding layer completely covers the upper surface of the electronic component and at least one of the side surfaces, the electronic component is provided with good electromagnetic interference shielding, and the electromagnetic interference of the electronic component is reduced. At the same time, the metal material of the shielding layer: also has a good heat dissipation effect, and is used as a heat sink. Next, please refer to FIG. 1C, and a glue process is formed to form a sealant 120 disposed on the laminate 1〇1 and the substrate 100, and the coated electrons φ pieces l〇6 (106aM〇6b/l〇6c) ), the shielding layer 11 〇 and covering at least the j portion = the adhesive layer 104. In the encapsulation process, the model is generally used to facilitate the injection of the encapsulant at a specific location, and after the encapsulant is solidified to form the encapsulant 12, the model is removed. The sealant is, for example, a thermosetting polymer, an epoxy resin, a polyimide or a benzocyclobutene (BCB). Next, please refer to FIG. 1D 'Removing the substrate 1 〇〇 and then performing all the steps of the trimming layer 101 so that the sides thereof are aligned with the encapsulant 120, and the whole structure is inverted upside down, that is, the encapsulant 12 〇 is located below , and the dielectric film 1〇1 _ is located at the top. < Referring to FIG. 1E', the patterned dielectric film 1〇2 and the adhesive layer 1〇4 are formed to form a patterned laminate 101a including openings V, and the wire openings v expose the contact ends 1电子5 of the electronic components 106. . Thereafter, the patterned dielectric film 1〇2 & rises into the conductive pattern 130 and covers the opening V to be in contact with the contact end 105 of the electronic component; therefore, the different electronic components can be electrically connected to each other through the conductive pattern . Here, the patterned laminate 10a and the conductive pattern 13A may be regarded as one of a laminate of a built-up substrate. Stacked reed or

201227908 i-3iyyuuilTW 35306twf.doc/I The laminated substrate 'is, for example, a printed circuit board substrate of two laminated layers, four layers or eight layers. Referring to Fig. 1F, another patterned laminate 140 and conductive pattern 150 are formed on the patterned stack i ia and conductive pattern 13 , as another stack of built-up substrates. The encapsulant 12A constitutes the electronic component package 10 together with the electronic component coated thereon and the laminated structure 10^/^0/140/150 thereon. Here, only two laminated substrates are formed on the sealant 12'. However, the scope of the present invention is not limited thereto, and the above steps may be repeated several times to form a multilayer laminated substrate. 3A-3E are cross-sectional views showing the fabrication process of an electronic component package structure in accordance with another embodiment of the present invention. Referring to Fig. 3A, a substrate 3 is provided. The substrate 3 can be a laminated substrate. For example, it is a two-layer laminated printed circuit board substrate. The substrate 3 is actually regarded as a so-called first laminate, which is formed by the first dielectric layer 3〇4, the lower first metal layer 302 and the upper second metal layer 3〇6, and is transparently A plurality of first vias 3〇8 electrically connect the upper and lower metal layers 306 and 302. Next, the electronic component 31 is sequentially disposed on the substrate 300 with the face down (faCe-d〇wn). The electronic component 31 can be electrically connected to the substrate 3 through a flip chip bonding technique. The first and second metal layers 302 306 include different line patterns ... 丨 丨 pattern) with contact 塾 or 塾. A press layer 311 having a third metal layer 312 and a second dielectric layer 314 is provided with reference to FIG. 3B'. Wherein the third metal layer 312 may comprise a continuous or discrete metal pattern block' whose position corresponds to the electronic component 31 underneath

201227908 P51990051TW 35306twf.d〇c/I set. Next, as shown in FIG. 3C, the press-bonding layer 3ii is pressed onto the first laminate 300 by a thermocompression bonding technique, and the metal pattern block position of the first layer 312 corresponds to the electrons during the pressing process. The element 31〇: the three metal layers 3丨2 will cover the upper surface and the side surface of the electronic component 310, and even cover a portion of the second metal layer 3〇6 of the first laminate 300 to reach electricity. Connected to the first stack 300 (ground). In this embodiment, the third metal layer 312 can be regarded as the electronic component 7, completely covering the upper surface of the electronic component and at least one side surface, and providing a good electrical insulation shielding effect of the electronic component. The electronic component is disturbed, and the third metal layer 312 covers a portion of the substrate. However, this embodiment shows that the third metal layer is coated on the substrate, which is also a visual process or an electronic component functional configuration, and only covers certain Specific electronic components. Eight® cases are embedded in the electronic components of the embedded electronic components, and are pressed and attached to, so that the embedded components are covered with a metal film to provide multiple protection functions. -Tomb: </ RTI> </ RTI> Referring to FIG. 3D, a plurality of mth philosophies 316 are formed in the second dielectric layer 314 and a fourth metal layer 316318 and a second metal layer 3 (6) are formed on the second dielectric layer 314. Passing through the second via hole. The second dielectric layer 314, the fourth metal layer 318 and the so-called second laminate 320 are formed. The material of the metal layer including copper, _; and ^ can be phased or different, and the material of the second metal layer is, for example, aluminum or copper metal. 1; 1 electrical layer material can be the same or different, can include organic

201227908 rDiyyuuDlTW 35306twf.doc/I, such as polyimide benzo (but benzocyclobutene, BCB), polyarylene (parylene) and other polymers. Referring to FIG. 3E, a plurality of solder balls 330 are formed directly on the fresh pad 302a of the first metal layer 302. 4 is a cross-sectional view showing an electronic component package structure according to still another embodiment of the present invention. Referring to FIG. 4 , in the embodiment, the electronic component package 40 includes a substrate 400 , a plurality of electronic components 410 , a first shielding layer 412 , a dielectric structure 414 , a metal wiring structure 410 , and a second The shielding layer 418, a top dielectric structure 420, and a plurality of vias 422. The substrate 400 can be a laminate substrate, such as a two-layer laminated printed circuit board substrate. The electronic component 410 is, for example, a high power wafer and is connected to the substrate 400 in a flip chip manner. The electronic component 41 is disposed on the upper surface of the substrate 4A or on the upper surface of the intermediate dielectric structure 414. The first shielding layer 412 is disposed on and covers the upper surface of the substrate 400 and covers part or all of the four or at least one side wall of the electronic component 41 and/or part or all of the upper surface. The material of the first shielding layer 412 and the second shielding layer 418 may be, for example, copper, copper or copper alloy, and the materials of the first shielding layer 412 and the second shielding layer 418 may be the same or different. The second masking layer 418 is disposed on the intermediate dielectric structure 414 and the metal wiring structure 416, covering part or all of the four or at least one side wall and/or the upper surface of the electronic component and covering the via structure 416. Wherein, the first and first masking structures 416 can be insulated to obtain a connection function. In addition, the via 422 is electrically connected to the metal wiring structure 416 and the substrate 4 形成 in the inter-dielectric structure 414. The first or second shielding layer can be grounded depending on the product design. In addition, the electronic component package 40 of the present embodiment includes a plurality of solder balls 424 on the back surface of the substrate 4, which can serve as contacts for electrical connection with the outside. In the electronic component package of the embodiment, the first or second shielding layer can be regarded as an EMI shidd, and the tiltable electronic component is protected from electromagnetic interference light from an external or internal light source. Therefore, compared with the conventional package, the electronic component package of the present embodiment does not need to be "not only" but also provides a thinner domain i-th structure, which can enhance the electronic design. The component package has a "dry" performance. In particular, the 'masking layer can selectively cover a specific electronic component, or the lining layer (10) covers the electronic components of different layers, and enhances the electromagnetic interference shielding effectiveness of the electronic component. Stomach &amp; (4) In this embodiment, the electronic component package (10) may be a package structure or a partial system-level package (system_in_pa ^ _ in summary, due to the surface of the good component and the side edges effectively shielded External electromagnetic interference radiation, thus improving the invention:: The effectiveness of the electromagnetic interference of the two packages. The present invention: The method 'is before the upper mold sealing or should be combined:: piece: capacity. attached to the electronic components The surface is so covered with the existing packaging process phase. The design of the embodiment above is covered above or/and around the electronic component 11

201227908 35306twf.d〇c/I ^ is a thin film that makes the surface of the electronic component thin and thin. The effect of magnetic interference shielding can also have good heat dissipation and heat dissipation effect. This is to implement the above-mentioned _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Within, when a little change and refinement can be made, the scope of protection of the invention shall be subject to the definition of the appended article. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are schematic cross-sectional views showing a manufacturing process of an electronic component package in accordance with an embodiment of the present invention. 2A-2E are top schematic illustrations of the pattern blocks included in a portion of the masking layer. 3A to 3e are cross-sectional views showing the manufacturing process of an electronic component package structure according to another embodiment of the present invention. 4 is a cross-sectional view showing an electronic component package structure according to still another embodiment of the present invention. [Description of main component symbols] 10, 40: Electronic component package 100, 300, 400: Substrate 101, 140, 320: Stack 102: Dielectric film 104: Adhesive layer £ 12

201227908 P51990051TW 35306twf.doc/I 105 : contact terminals 106, 106a, 106b, 106c, 310, 410: electronic component 110: shielding layer 120: encapsulant 130, 150: conductive pattern 210: metal pattern 21a: holes 21b, 21c: Mesh void 21d · mesh metal strip 302: first metal layer 302a: pad 304 first dielectric layer 306 second metal layer 308 first via hole 311 press layer 312 third metal layer 314 second dielectric Layer 316 second via 318 fourth metal layer 412 first shielding layer 414 dielectric structure 416 metal wiring structure 418 second shielding layer 420 top dielectric structure 13 201227908

lyyuuD 1TW 35306twf.docA 422 : via hole 330, 424 : solder ball V : opening

Claims (1)

201227908 rsiyyuuDlTW 35306twf.doc/I VII. Patent application scope: 1. An electronic component package comprising: a substrate; at least one first electronic component 'disposed on the substrate and electrically connected to the substrate; a layer disposed on the substrate and covering at least part or all of the upper surface of the first electronic component with at least a portion and a portion of the substrate; and a file and a structure on which the structure is disposed Part or all of the first electronic component is overlapped with the substrate. 2. The good component package 2 as described in the application of the patent item i is disposed on the first dielectric structure, and the base-base 1: wealth is more conductive, the connection, the _ metal circuit and the Applying for the electronic component package described in item 2 of the patent scope, further components, and ί;::: on the substrate, the second electron, with: === less of the ΐ all and part of the metal The line structure; and the seven-knife or electrical structure of the j-face is on the second shielding layer and the part-to-four is as part or all of the disciple element. The application of the fourth part of the application - the electronic components of the item 15 201227908 rji ^ ^ wJlTW 35306twf.doc / I package, including a plurality of solder balls arranged under the substrate. 5. For the application of the special _3 item - the electronic component crystal package of the above, the t-the electronic component is - Lai Jing high power sheet. 6. The electronic component package of claim 3, wherein the second electronic component is a passive component. 〃 7. The electronic component package of claim 3, wherein the second element is a semiconductor crystal. The electronic component _ &quot;, wherein the material of the first shielding layer comprises copper or aluminum or other metal" is a non-metallic conductive material such as carbon tape. And the first shielding layer = the same hole or the same or has a grid-like gap. ^ Medium: The electronic component package according to item 3 of the HI benefit range, the material of the first layer includes copper or H other The metal may be non-Ϊ=: two and the second shielding layer has a plurality of holes 10. The embedded electronic component package comprises: at least one dielectric structure and one metal pattern structure layer At least an electronic component disposed on the stack and electrically connected to the stacked shielding layer, disposed on the stack, and at least part or all of at least one side of the surface and the at least one side portion The metal pattern structure of the layer; and, £16 201227908 oiyyuu^ilTW 35306 tw£doc/I sealant It ge* is placed on the layer and encapsulates part or all of the electronic component and part or all of the mask layer Such as the patent application (4) 1G item of the electric shirt package It also includes a solder ball disposed under the stack. 1^2^ Please specify (4) the good component package described in 1G, ^ the electronic component is - RF chip, - high power ^ or "passive" The material of the obscuring layer includes a material of a Natchezzi sub-packaged limb, such as a (10) tape, and the shielding layer covers the second of the electronic component. At least part or all of the four sides of the face-to-face and the concealer layer are designed to have a plurality of holes. M. The electronic component body of claim 4, wherein the material of the shielding layer comprises copper. Or, and the shielding layer covers at least one or all of the four surfaces of the upper surface of the electron 2 and the four sides, and the shielding layer is designed to have a grid-like gap. The substrate 15 · the electronic component package (4) The method includes: providing a base-to-f-sub-element, flanking the substrate and bonding to the providing-first shielding layer, disposed on the substrate, and up to a portion of the upper surface of the sub-element Or all with at least one side or all and part of the base And a &lt;knife providing-first-dielectric structure, disposed on the first shielding layer and the base 201227908 1TW 35306twf, doc/I board, and covering part or all of the first electronic component. The method for fabricating the electronic component package of claim 15 further includes providing a metal line structure disposed on the first dielectric structure and having a plurality of via holes in the first dielectric structure. The metal circuit and the substrate are connected to the substrate. The paste 16 provides a minimum of the second electronic component, is disposed on the substrate, and electrically connects the first electronic component to the metal circuit structure; a second shielding layer disposed on the substrate and covering at least a portion of the upper surface of the second electronic component or a portion of the metal wiring structure; and, a portion of the side surface of the crucible And a part of the second electronic component is disposed on the second shielding layer. Providing a H sub-component county-making branch, comprising: a fork layer having at least one dielectric 垆槿. = a metal pattern structure disposed under the dielectric structure. The stack-less electronic component is disposed on the stack The layer is electrically connected to the component sub-==layer' and covers at least the electron portion of the lamination of the metallographic coherent two / (four) or all of the electronic component