TWI576979B - Package substrate and method for manufacturing the same - Google Patents

Description

Package substrate and method of manufacturing same

The present invention relates to a substrate for a semiconductor package structure, and more particularly to a package substrate and a method of fabricating the same.

As the time history evolves, electronic devices become thinner and smaller. Semiconductor package components have also become smaller in size and higher in density, and are suitable for miniaturization of electronic devices. In particular, in the multi-chip package construction, the primary problem of poor heat dissipation efficiency is faced.

Early multi-wafer package constructions were the stacking of multiple wafers on a substrate whose package size and package thickness were limited by the height of the wafer stack. The invention relates to a wafer stack structure, a buried wafer structure and a method for fabricating the same, and teaches a package structure in which a wafer is embedded in a substrate, and a buried wafer structure including a substrate, a semiconductor structure, a layer of sealing material, and a plurality of vias. The substrate includes at least one dielectric layer and at least one patterned circuit layer disposed on the dielectric layer. The semiconductor structure is disposed on the substrate, the semiconductor structure having a plurality of electrical pads, and the electrical pads are in contact with the dielectric layer. The layer of sealing material is disposed on the substrate surrounding the semiconductor structure. In addition, a plurality of via holes are disposed in the substrate such that the patterned circuit layer is electrically connected to the electrical pads. A preferred state of the prior art structure is that a wafer is embedded in the substrate, and the active surface of the wafer is covered with a dielectric layer having a poor heat dissipation. When the number of embedded wafers is two or more, the heat dissipation efficiency will be lowered.

In order to solve the above problems, the main object of the present invention is to provide a package substrate and a method of fabricating the same, which are used to reduce the overall size of the multi-chip package structure and maintain good heat conduction efficiency.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a package substrate comprising a core layer, a wafer stack, a first metal layer, a second metal layer and a plurality of via holes. The core layer has a lower surface and an upper surface. The wafer stacking system is embedded in the core layer for defining a thickness of the core layer. The wafer stacking system includes a lower wafer and an upper wafer, the lower wafer and the upper wafer are back-to-back bonded so that the lower wafer has Exposed on one of the first active surfaces of the lower surface, the upper wafer has a second active surface exposed on the upper surface, and a plurality of turns are penetrated through the wafer stack and electrically connected to the lower wafer and the upper wafer. The first metal layer is formed on the lower surface of the core layer and attached to the first active surface of the lower wafer, and the first metal layer is attached to at least the first active surface of the lower wafer. For more than fifty areas, the first metal layer is connected to a plurality of first pads exposed on the lower surface. The second metal layer is formed on the upper surface of the core layer and attached to the second active surface of the upper wafer, and the second metal layer is connected to a plurality of second pads exposed on the upper surface. The via holes extend through the core layer and electrically connect the first pads and the second pads. The present invention further discloses a method of manufacturing the above package substrate.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the package substrate, the second metal layer is preferably at least 50% of the area of the second active surface of the upper wafer.

In the foregoing package substrate, the first metal layer is more specifically attached to at least 80% of the area of the first active surface of the lower wafer.

In the package substrate, the two ends of the via holes may be exposed to the first metal layer and the second metal layer, and the germanium vias may not be exposed to the first metal layer and the second metal layer.

In the package substrate, a solder resist layer and an upper solder resist layer may be further included to cover the first metal layer and the second metal layer, respectively.

In the package substrate, an external chip may be further disposed on the upper surface and electrically connected to the first pads.

In the foregoing package substrate, a plurality of external terminals may be further disposed on the lower surface and electrically connected to the second pads.

By the above technical means, the present invention can achieve the following effects:

1. By embedding the wafer stacking system in the core layer and defining the thickness of the core layer by the number of embedded wafers, the number of external wafers disposed on the package substrate can be reduced to reduce the package size of the multi-chip package structure. At the same time, the active surface of the wafer stack is exposed to the core layer, and more than half of the area is covered by the metal layer, and the perforation and via holes are matched to achieve good heat conduction efficiency.

Second, the package substrate can replace the POP stackable package, and can integrate a memory chip (such as DRAM) and a logic IC chip in the core layer of a substrate.

Third, the double-sided metal layer of the core layer of the substrate can cover the active surface of the wafer, and does not need to be away from the wafer, so that the wiring design of the metal layer can be more convenient and free.

4. The core layer of the package substrate may be a multi-layer structure to form a multi-layer circuit structure and embed a multi-wafer circuit substrate.

100‧‧‧Package substrate

110‧‧‧ core layer

111‧‧‧lower surface

112‧‧‧ upper surface

120‧‧‧ wafer stack

121‧‧‧lower wafer

122‧‧‧Upper wafer

123‧‧‧First active surface

124‧‧‧Second active surface

125‧‧‧矽 piercing

130‧‧‧First metal layer

131‧‧‧First mat

140‧‧‧Second metal layer

141‧‧‧second mat

150‧‧‧through hole

160‧‧‧Under the solder mask

170‧‧‧Upd welding layer

180‧‧‧Outer wafer

190‧‧‧External terminals

210‧‧‧ Temporary carrier board

211‧‧‧Adhesive layer

FIG. 1 is a perspective view of a package substrate according to an embodiment of the invention Schematic diagram of the section.

2 is a cross-sectional view showing a multi-chip package structure using the package substrate in accordance with an embodiment of the present invention.

3A to 3G are schematic cross-sectional views showing components of the package substrate during fabrication in accordance with an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to an embodiment of the present invention, a package substrate and a method of manufacturing the same are illustrated in a cross-sectional view of FIG. 1 and a cross-sectional view of FIG. 2 applied to a multi-chip package structure. An example of a method for manufacturing a package substrate is described. 3A to 3G diagram of the cross-section of the components in the production process. A package substrate 100 includes a core layer 110, a wafer stack 120, a first metal layer 130, a second metal layer 140, and a plurality of vias 150.

The core layer 110 has a lower surface 111 and an upper surface 112. The core layer 110 is a non-conductive dielectric material such as polyamine (PI) as the main structure of the package substrate 100. The wafer stack 120 is embedded in the core layer 110 for defining the thickness of the core layer 110. The wafer stack 120 includes a lower wafer 121 and an upper wafer 122. The lower wafer 121 and the upper wafer 122 are semiconductor elements having integrated circuits. The lower wafer 121 and the upper wafer 122 are back-to-back The lower wafer 121 has a first active surface 123 exposed on the lower surface 111, and the upper wafer 122 has a second active surface 124 exposed on the upper surface 112. The integrated circuit is formed on the first active surface 123 and the second active surface 124 as an operational heat source of the wafer stack 120. The size of the lower wafer 121 and the upper wafer 122 may be the same or different; in this embodiment, the size of the lower wafer 121 is larger than the size of the upper wafer 122, and the lower wafer 121 may be a DRAM memory. The upper wafer 122 can be a logic controlled wafer. A plurality of turns of the vias 125 extend through the wafer stack 120 and are electrically connected to the lower wafer 121 and the upper wafer 122. The conductive perforations 125 are filled with a conductive material such as copper.

The first metal layer 130 is formed on the lower surface 111 of the core layer 110 and attached to the first active surface 123 of the lower wafer 121. The first metal layer 130 is attached to at least the lower wafer 121. More than 50% of the area of the active surface 123. The first metal layer 130 can include a connection line on the lower surface 111 and a heat dissipation island block on the first active surface 123. Preferably, the first metal layer 130 is more specifically attached to at least 80% of the area of the first active surface 123 of the lower wafer 121. The first metal layer 130 is connected to a plurality of first pads 131 exposed on the lower surface 111. The first pads 131 may be arranged in a matrix, and some of the first pads 131 may be located below the first active surface 123 of the lower wafer 121. The first metal layer 130 can be formed by PVD deposition and electroplating. An adhesive layer is not required between the first metal layer 130 and the first active surface 123, so that the first metal layer 130 is directly attached to the first metal layer 130. The first active surface 123.

The second metal layer 140 is formed on the upper surface 112 of the core layer 110 and attached to the second active surface 124 of the upper wafer 122. The second metal layer 140 is connected to the plurality of exposed surfaces. The second pad 141 of 112. Preferably, the second metal layer 140 is preferably at least More than fifty percent of the area of the second active surface 124 of the upper wafer 122 is attached. Similarly, the second metal layer 140 can include a connection line on the upper surface 112 and a heat dissipation island block on the second active surface 124. The second pads 141 may be arranged in a peripheral manner, and the second pads 141 may not be located above the second active surface 124 of the upper wafer 122.

The via holes 150 are connected to the core layer 110 and electrically connected to the first pads 131 and the second pads 141 . The two ends of the via holes 150 may be exposed to the first metal layer 130 and the second metal layer 140, and the germanium vias 125 may not be exposed to the first metal layer 130 and the second metal layer 140.

The package substrate 100 may further include a solder resist layer 160 and an upper solder resist layer 170 respectively covering the first metal layer 130 and the second metal layer 140, but the lower solder resist layer 160 is provided with an opening. The first solder pads 131 are not covered; the upper solder resist layer 170 is provided with openings to not cover the second pads 141.

As shown in FIG. 2, the package substrate 100 can further include an outer wafer 180 disposed on the upper surface 112 and electrically connected to the first pads 131 by bumps or bonding wires. Alternatively, the outer wafer 180 can be sealed with a gel. In addition, the package substrate 100 can further include a plurality of external terminals 190 disposed on the lower surface 111 and electrically connected to the second pads 141 . The external terminals 190 can be solder balls.

The method of manufacturing the package substrate 100 described above is exemplified in FIGS. 3A to 3G. As shown in FIG. 3A, a temporary carrier 210 is provided, and an adhesive layer 211 is formed on one surface of the temporary carrier 210 to lose viscosity under heat or exposure. The temporary carrier 210 can be a wafer dicing tape or a light transmissive sheet having a UV adhesive layer.

As shown in FIG. 3B, a wafer stack 120 is adhered to the temporary carrier 210 by the adhesive layer 211, and the wafer stack 120 is attached. A wafer 121 and an upper wafer 122 are included. The lower wafer 121 and the upper wafer 122 are back-to-back. The plurality of turns 125 are through the wafer stack 120 and electrically connected to the lower wafer 121 and the upper wafer. 122.

As shown in FIG. 3C, a core layer 110 is formed on the temporary carrier 210 by liquid coating. The core layer 110 has a lower surface 111 and an upper surface 112, and the wafer stack 120 is embedded in the wafer stack 120. The core layer 110 is used to define the thickness of the core layer 110, and the lower wafer 121 has a first active surface 123 exposed on the lower surface 111. The upper wafer 122 has one of the upper surfaces 112 exposed. The second active surface 124. After the core layer 110 is formed, it is cured into a sheet by baking. Thereafter, the adhesive layer 211 is first rendered viscous, and the temporary carrier 210 is removed as shown in FIG. 3D.

As shown in FIG. 3E, a first metal layer 130 is formed on the lower surface 111 of the core layer 110 by physical vapor deposition, electroplating, or/and etching, and is attached to the first wafer 121. The active surface 123, the first metal layer 130 is attached to at least 50% of the area of the first active surface 123 of the lower wafer 121. As shown in FIG. 3E, a second metal layer 140 is formed on the upper surface 112 of the core layer 110 and attached to the second active surface 124 of the upper wafer 122.

As shown in FIG. 3F, a plurality of via holes 150 are formed through the hole and hole plating techniques, and the via holes 150 are penetrated through the core layer 110. As shown in FIG. 3G, a solder resist layer 160 and an upper solder resist layer 170 are formed on the lower surface 111 and the upper surface 112, respectively, and the lower solder resist layer 160 and the upper solder resist layer 170 respectively cover the first surface. A metal layer 130 and the second metal layer 140.

Finally, as shown in FIG. 1, a plurality of first pads 131 and a plurality of first holes are disposed in the lower solder resist layer 160 and the opening of the upper solder resist layer 170. Two pads 141 are connected to the first metal layer 130 and exposed to the lower surface 111. The second pads 141 are connected to the second metal layer 140 and exposed on the upper surface. The conductive vias 150 are electrically connected to the first pads 131 and the second pads 141 .

Therefore, the package substrate 100 and the manufacturing method thereof provided by the present invention can be used to reduce the overall size of the multi-chip package structure and maintain good heat conduction efficiency.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100‧‧‧Package substrate

110‧‧‧ core layer

111‧‧‧lower surface

112‧‧‧ upper surface

120‧‧‧ wafer stack

121‧‧‧lower wafer

122‧‧‧Upper wafer

123‧‧‧First active surface

124‧‧‧Second active surface

125‧‧‧矽 piercing

130‧‧‧First metal layer

131‧‧‧First mat

140‧‧‧Second metal layer

141‧‧‧second mat

150‧‧‧through hole

160‧‧‧Under the solder mask

170‧‧‧Upd welding layer

Claims (3)

A method for manufacturing a package substrate, comprising: providing a temporary carrier; attaching a wafer stack to the temporary carrier, the wafer stacking system comprising a lower wafer and an upper wafer, the lower wafer and the upper wafer being back-to-back And a plurality of cymbal perforations extending through the wafer stack and electrically connecting the lower wafer and the upper wafer; forming a core layer on the temporary carrier, the core layer having a lower surface and an upper surface, and The wafer stacking system is embedded in the core layer to define a thickness of the core layer, and the lower wafer has a first active surface exposed on the lower surface, the upper wafer having one of the exposed upper surfaces a second active surface; removing the temporary carrier; forming a first metal layer formed on the lower surface of the core layer and attached to the first active surface of the lower wafer, the first metal layer being attached at least Forming a second metal layer on the upper surface of the core layer and attaching to the second active surface of the upper wafer; forming a plurality of via holes , The plurality of first pads and the plurality of second pads are connected to the first metal layer and exposed to the lower surface, the second connection The pad is connected to the second metal layer and exposed to the upper surface, and the via holes are electrically connected to the first pads and the second pads. According to the manufacturing method of the package substrate according to claim 1, the method further comprises the steps of: forming a solder resist layer and an upper guard separately The solder layer is on the lower surface and the upper surface, and the lower solder resist layer and the upper solder resist layer cover the first metal layer and the second metal layer, respectively. The method of manufacturing a package substrate according to claim 1 or 2, wherein the first metal layer is attached to at least 80% of an area of the first active surface of the lower wafer.