TWI485815B - Semiconductor package and method of fabricating the same - Google Patents

Description

Semiconductor package and its manufacturing method

The present invention relates to a packaging technology, and more particularly to a semiconductor package and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of semiconductor package miniaturization, the thickness of the package substrate carrying the wafer is reduced.

In the manufacturing method of the early semiconductor package, the rigidity of the overall structure is improved by the package substrate 1 having the core layer 10, as shown in FIG. 1, to facilitate subsequent crystallizing and packaging processes. The package substrate 1 further includes: a plurality of dielectric layers 11 formed on opposite sides of the core layer 10, a circuit layer 12 formed on the dielectric layer 11, and formed in the dielectric layer 11 and electrically connected a plurality of conductive vias 13 of the circuit layer 12, a plurality of electrical contact pads 14 formed on the outermost dielectric layer 11, a plurality of conductive vias formed in the core layer 10 and electrically connected to the circuit layer 12. And a solder resist layer 15 formed on the outermost dielectric layer 11 , and the solder resist layer 15 exposes the electrical contact pads 14 . In the subsequent crystallizing and packaging process, a wafer is placed on the solder resist layer 15, and the wafer is electrically connected to the electrical contact pads 14 by a plurality of bonding wires, and the wafer is coated with the encapsulant. Welding wire.

However, since the package substrate 1 has the core layer 10, the thickness of the package substrate 1 is increased, resulting in an increase in the overall thickness of the semiconductor package, which is difficult to meet the demand for thinning. Furthermore, the guide is required to use the core layer 10. The electrical via 100 causes the conductive path to grow, resulting in slow signal transmission, so it is difficult to meet the functional requirements of the electronic product.

Therefore, the coreless package substrate has been developed to shorten the conductive path and reduce the overall structure thickness, thereby achieving the demand for miniaturization and high frequency.

2A to 2F are schematic cross-sectional views showing a manufacturing method of a conventional coreless semiconductor package 2.

As shown in FIG. 2A, a carrier structure 20 is provided. The carrier structure 20 has a first side 20a and a second side 20b. The first side 20a is sequentially formed with a first metal layer 21 and a second layer. The metal layer 22 has a third metal layer 23 on the second side 20b. The second metal layer 22 is formed on the first metal layer 21 by electroplating.

As shown in FIG. 2B, a plurality of electrical connection pads 24 are formed on the second metal layer 22.

As shown in FIG. 2C, a line build-up structure 25 is formed on the second metal layer 22 and the electrical connection pads 24. The circuit build-up structure 25 has at least one dielectric layer 250, a circuit layer 251 formed on the dielectric layer 250, and a plurality of conductive vias 252 formed in the dielectric layer 250, and the conductive vias 252 The circuit layer 251 and the electrical connection pad 24 are electrically connected, and the circuit layer 251 has a plurality of electrical contact pads 253.

Then, an insulating protective layer 26 is formed on the line build-up structure 25, and the electrical contact pads 253 are exposed on the surface of the insulating protective layer 26.

As shown in FIG. 2D, a semiconductor device 27 is disposed on the line build-up structure 25, and the semiconductor device 27 is electrically connected by a bonding wire 270. The electrical contact pads 253. Next, an encapsulant 28 is formed on the insulating protective layer 26 to encapsulate the semiconductor element 27.

As shown in FIG. 2E, the carrier structure 20, the first metal layer 21 and the third metal layer 23 are removed by a lift-off method.

As shown in FIG. 2F, the second metal layer 22 is removed by etching, and the electrical connection pads 24 are exposed for subsequent ball implantation processes. In fact, during the etching removal process, a portion of the surface of the electrical connection pad 24 is etched such that a portion of the surface of the electrical connection pad 24 forms an irregular micro-recessed surface.

However, in the conventional method, the adhesion force of the second metal layer 22 and the electrical connection pad 24 to the dielectric layer 250 is greater than the adhesion between the second metal layer 22 and the first metal layer 21, so After the removal of the carrier structure 20, the first metal layer 21 and the third metal layer 23, the second metal layer 22 is still left on the dielectric layer 250, and then the second layer is removed by etching. The metal layer 22 causes a long process time and requires the use of equipment and chemical liquids required for the etching process, thereby greatly increasing the manufacturing cost.

Therefore, how to overcome the above-mentioned problems of the prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package comprising: a line build-up structure having opposite first and second surfaces, and the line build-up structure comprising a surface as the first At least one dielectric layer with the second surface, a circuit layer formed on the dielectric layer, and a plurality of conductive layers formed in the dielectric layer and electrically connected to the wiring layer a plurality of electrical contact pads electrically connected to the conductive blind vias; the plurality of electrical connection pads are embedded on the second surface of the line build-up structure and electrically connected to the conductive a blind hole, and the electrical connection pads are formed with a step difference; and at least one semiconductor component is disposed on the first surface of the circuit build-up structure, and the semiconductor component is electrically connected to the electrical Contact pad.

The present invention provides a method for fabricating a semiconductor package, comprising: providing a load-bearing structure having a first metal layer and a second metal layer in sequence; forming a plurality of electrical connection pads on the second metal layer; The second metal layer is not covered by the electrical connection pad to retain the second metal layer under the electrical connection pads and expose the first metal layer; forming a line build-up structure on the first metal And the plurality of electrical contact pads are disposed on the circuit, and the at least one semiconductor component is disposed on the circuit build-up structure, and the semiconductor component is electrically connected to the electrical contact pads; And removing the carrier structure, the first metal layer and the second metal layer under the electrical connection pad by a stripping method.

The invention further provides a method for fabricating a semiconductor package, comprising: providing a load-bearing structure having a first metal layer and a second metal layer in sequence; and patterning the second metal layer to form a plurality of electrical connection pads, And exposing the first metal layer; forming a line build-up structure on the first metal layer and the electrical connection pads, and the circuit build-up structure has a plurality of electrical contact pads; and at least one semiconductor component is disposed on the line And the semiconductor device is electrically connected to the electrical contact pads; and the carrier structure and the first metal layer are removed by a stripping method.

In the above method, the electrical connection pads are formed by etching.

In the foregoing two methods, the carrying structure has opposite first and second sides, and the first side has the first and second metal layers, and the second side has a third metal layer. The first and third metal layers are copper foil.

In the above two methods, the second metal layer is formed on the first metal layer by electroplating.

In the above two methods, the line build-up structure has at least one dielectric layer, a circuit layer formed on the dielectric layer, and a plurality of conductive blind vias formed in the dielectric layer, and the conductive blind via The circuit layer and the electrical connection pad are electrically connected, and the electrical contact pads are part of the circuit layer of the outermost layer.

In the foregoing semiconductor package and the two methods, the method further comprises forming an insulating protective layer on the first surface of the line build-up structure, and exposing the electrical contact pads to the insulating protective layer. The method further includes forming an encapsulant on the insulating protective layer to encapsulate the semiconductor device.

In addition, in the foregoing semiconductor package and the two methods, the method further comprises forming an encapsulant on the first surface of the line build-up structure to encapsulate the semiconductor element.

It can be seen from the above that in the semiconductor package of the present invention and the method for fabricating the same, the second metal layer is removed from the dielectric layer by the second metal layer. The surface is less active and the bonding force is extremely small, so when the bearing structure and the first metal layer are peeled off, the second metal layer can be removed.

Furthermore, it is only necessary to remove the load-bearing structure, the first and second gold by peeling. The genus layer does not need to be subjected to an etching process as in the prior art, so that not only the process time can be saved, but also the equipment and chemical liquid required for the etching process can be omitted, thereby greatly reducing the manufacturing cost.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

3A to 3E are schematic cross-sectional views showing the manufacturing method of the semiconductor package 3 of the present invention.

As shown in FIG. 3A, a carrier structure 30 is provided. The carrier structure 30 has a first side 30a and a second side 30b. The first side 30a is sequentially formed with a first metal layer 31 and a second layer. The metal layer 32 has a third metal layer 33 on the second side 30b.

In this embodiment, the material of the bearing structure 30 is made of glass fiber material (such as FR4), and the first and third metal layers 31, 33 are made of copper foil, so that the bearing structure 30 is used as a copper foil substrate (Copper clad) Laminate, CCL). There are many types of copper foil substrates, and they are well known in the industry, so they will not be described again.

Furthermore, the second metal layer 32 is formed on the first metal layer 31 by electroplating.

As shown in FIG. 3B, a patterned circuit process is performed to form a plurality of electrical connection pads 34 on the second metal layer 32. There are no restrictions on the variety of line processes.

Then, the portion of the second metal layer 32 that is not covered by the electrical connection pad 34 is removed to retain the second metal layer 32' under the electrical connection pads 34, and the first metal layer 31 is exposed.

As shown in FIG. 3C, a line build-up structure 35 is formed on the first metal layer 31 and the electrical connection pads 34, and the circuit build-up structure 35 has a plurality of electrical contact pads 353 thereon.

In the present embodiment, the line build-up structure 35 has a dielectric layer 350, a circuit layer 351 formed on the dielectric layer 350, and a plurality of conductive vias 352 formed in the dielectric layer 350, and The conductive via 352 is electrically connected to the circuit layer 351 and the electrical connection pad 34, and the electrical contact pads 353 are part of the outermost circuit layer 351. The material of the dielectric layer 350 can be, for example, Prepreg (PP).

Furthermore, the line build-up structure 35 has opposite first and second surfaces 35a, 35b, and the first surface 35a and the second surface 35b are the surface of the dielectric layer 350, and the electrical contact pads 353 is formed in the On the first surface 35a, the line build-up structure 35 and the first metal layer 31 are bonded by the second surface 35b.

In the present invention, the second metal layer 32 in the region other than the underside of the electrical connection pads 34 is removed by an etching process to reduce the contact area between the second metal layer 32' and the dielectric layer 350 (only the first The side of the two metal layers 32' is such that the bonding force between the two is extremely small, and the adhesion between the dielectric layer 350 and the electrical connection pad 34 can be increased.

Moreover, in the embodiment, the line build-up structure 35 is a single-layer line structure, so the upper surface and the lower surface of the dielectric layer 350 serve as the first surface 35a and the second surface 35b. In other embodiments, the line build-up structure may also be a multi-layer line structure, and the upper and lower outermost dielectric layer surfaces serve as the first and second surfaces.

Then, an insulating protective layer 36 is formed on the first surface 35a of the circuit build-up structure 35, and the electrical contact pads 353 are exposed on the surface of the insulating protective layer 36.

In the present embodiment, the electrical contact pads 353 are flush with the surface of the insulating protective layer 36 to expose the electrical contact pads 353 to the surface of the insulating protective layer 36. In other embodiments, a plurality of openings (not shown) may be formed on the insulating protective layer 36 so that the electrical contact pads 353 are correspondingly exposed to the openings.

As shown in FIG. 3D, a semiconductor device 37 is disposed on the first surface 35a of the line build-up structure 35 (ie, the insulating protective layer 36), and the semiconductor device 37 is electrically connected to the electrical contact pads 353. . Next, an encapsulant 38 is formed on the insulating protective layer 36 to encapsulate the semiconductor element. Item 37.

In the embodiment, the semiconductor component 37 is electrically connected to the electrical contact pads 353 by a plurality of bonding wires 370. In other embodiments, the semiconductor device 37 can be electrically connected to the electrical contact pads 353 by flip chip (ie, conductive bumps).

As shown in FIG. 3E, the carrier structure 30, the first metal layer 31, the third metal layer 33, and the second metal layer 32' under the electrical connection pad 34 are removed by a stripping method. The exposed surface 34a of the electrical connection pads 34 forms a flat step with the second surface 35b of the line build-up structure 35, as shown by the step height h.

In the method of the present invention, the adhesion force of the supporting structure 30 (such as glass fiber material) to the first metal layer 31 is greater than the adhesion force of the first metal layer 31 to the dielectric layer 350, so when removed by peeling When the structure 30 is placed, the first metal layer 31 can be easily peeled off.

Furthermore, when the electrical connection pad 34 is fabricated, the second metal layer 32 in the region other than the electrical connection pad 34 is removed, and the second metal layer 32' is bonded to the dielectric layer 350. The force is extremely small, so when the first metal layer 31 is peeled off, the second metal layer 32' can be peeled off.

Moreover, in the manufacturing method of the present invention, only the supporting structure 30 and the structure thereon are removed by peeling, and the etching process is not required, so that not only the processing time can be saved, but also the equipment and chemical liquid required for the etching process can be omitted. The cost can thus significantly reduce manufacturing costs.

In addition, as shown in FIG. 3E', in the process of FIG. 3B, the second metal layer 32 may be directly patterned, that is, the second metal layer 32 is etched to form The plurality of electrical connection pads 34' are exposed and the first metal layer 31 is exposed. When the supporting structure 30, the first metal layer 31 and the third metal layer 33 are subsequently removed, the supporting structure 30 and the first metal layer 31 need to be peeled off to avoid peeling off the electrical connecting pads 34'. .

The present invention further provides a semiconductor package 3 comprising: a line build-up structure 35, a plurality of electrical connection pads 34, a semiconductor component 37, and an encapsulant 38.

The circuit build-up structure 35 has opposite first and second surfaces 35a, 35b, and the circuit build-up structure 35 includes a surface as a dielectric layer 350 of the first and second surfaces 35a, 35b. a circuit layer 351 on the dielectric layer 350, and a plurality of conductive vias 352 formed in the dielectric layer 350 to electrically connect the circuit layer 351, and the first surface 35a is electrically connected to the conductive blind A plurality of electrical contact pads 353 of holes 352.

The electrical connection pads 34 are embedded on the second surface 35b of the line build-up structure 35, and the electrical connection pads 34 are formed with a step difference from the second surface 35b, and electrically connected to the conductive blind Hole 352.

The semiconductor device 37 is disposed on the first surface 35a of the circuit build-up structure 35, and electrically connected to the electrical contact pads 353 by a plurality of bonding wires 370.

The encapsulant 38 is formed on the first surface 35a of the line build-up structure 35 to encapsulate the semiconductor component 37.

The semiconductor package 3 includes an insulating protective layer 36 formed on the first surface 35a of the line build-up structure 35, and the electrical contact pads 353 are exposed on the surface of the insulating protective layer 36. Encapsulant 38 The insulating protective layer 36 is formed to cover the semiconductor element 37.

In summary, in the semiconductor package of the present invention and the method of manufacturing the same, the carrier structure, the first and second metal layers are directly removed by stripping, and the etching removal process is not required after the stripping process, so not only It saves process time and can significantly reduce production costs.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1‧‧‧Package substrate

10‧‧‧ core layer

100‧‧‧ conductive vias

11,250,350‧‧‧ dielectric layer

12,251,351‧‧‧ circuit layer

13,252,352‧‧‧ conductive blind holes

14,253,353‧‧‧Electrical contact pads

15‧‧‧ solder mask

2,3‧‧‧Semiconductor package

20,30‧‧‧bearing structure

20a, 30a‧‧‧ first side

20b, 30b‧‧‧ second side

21,31‧‧‧First metal layer

22,32,32’‧‧‧second metal layer

23,33‧‧‧ Third metal layer

24,34,34’‧‧‧Electrical connection pads

25,35‧‧‧Line layering structure

26,36‧‧‧Insulating protective layer

27,37‧‧‧Semiconductor components

270,370‧‧‧welding line

28,38‧‧‧Package colloid

34a‧‧‧Exposed surface

35a‧‧‧ first surface

35b‧‧‧second surface

H‧‧‧ step height

1 is a schematic cross-sectional view of a conventional package substrate having a core layer; FIGS. 2A to 2F are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package without a core layer; and FIGS. 3A to 3E are diagrams A cross-sectional view of a method of fabricating a semiconductor package of the invention; wherein the 3E' is a schematic cross-sectional view of another embodiment of the 3E'.

3‧‧‧Semiconductor package

34‧‧‧Electrical connection pads

34a‧‧‧Exposed surface

35‧‧‧Line layering structure

35a‧‧‧ first surface

35b‧‧‧second surface

350‧‧‧ dielectric layer

351‧‧‧Line layer

352‧‧‧conductive blind holes

353‧‧‧Electrical contact pads

36‧‧‧Insulating protective layer

37‧‧‧Semiconductor components

370‧‧‧welding line

38‧‧‧Package colloid

H‧‧‧ step height

Claims (21)

A semiconductor package without a core layer, comprising: a line build-up structure having opposite first and second surfaces, and the line build-up structure includes a surface as at least one dielectric of the first and second surfaces a layer, a circuit layer formed on the dielectric layer, and a plurality of conductive vias formed in the dielectric layer and electrically connected to the circuit layer, and the first surface has a plurality of electrically connected conductive vias An electrical contact pad; the plurality of electrical connection pads are embedded on the second surface of the line build-up structure and electrically connected to the conductive blind hole, and the surface of the electrical connection pads is lower than the second surface, Forming a difference between the electrical connection pads and the second surface; and at least one semiconductor component is disposed on the first surface of the circuit build-up structure, and the semiconductor component is electrically connected to the electrical contact pads. The semiconductor package of claim 1, further comprising an insulating protective layer formed on the first surface of the line build-up structure, and exposing the electrical contact pads to the insulating protective layer. The semiconductor package of claim 2, further comprising an encapsulant formed on the insulating protective layer to encapsulate the semiconductor component. The semiconductor package of claim 1, further comprising an encapsulant formed on the first surface of the line build-up structure to encapsulate the semiconductor component. A method for fabricating a semiconductor package without a core layer includes: Providing a load-bearing structure, the surface of which has a first metal layer and a second metal layer; forming a plurality of electrical connection pads on the second metal layer; removing the second metal layer is not covered by the electrical connection pad a portion for retaining the second metal layer under the electrical connection pads and exposing the first metal layer; forming a line build-up structure on the first metal layer and the electrical connection pads, and adding the layer Structurally having a plurality of electrical contact pads; at least one semiconductor component is disposed on the circuit build-up structure, and the semiconductor component is electrically connected to the electrical contact pads; and the support structure is removed simultaneously by a stripping method A metal layer and the second metal layer under the electrical connection pad. The method of manufacturing the semiconductor package of claim 5, wherein the carrier structure has opposite first and second sides, and the first side has the first and second metal layers, and the first and second metal layers are There is a third metal layer on the second side. The method of fabricating a semiconductor package according to claim 6, wherein the first and third metal layers are copper foil. The method of fabricating a semiconductor package according to claim 5, wherein the second metal layer is formed on the first metal layer by electroplating. The method of fabricating a semiconductor package according to claim 5, wherein the circuit build-up structure has at least one dielectric layer, a circuit layer formed on the dielectric layer, and a dielectric layer formed in the dielectric layer. Complex guide The electrically conductive blind via is electrically connected to the circuit layer and the electrical connection pad, and the electrical contact pads are part of the outermost circuit layer. The method of fabricating a semiconductor package according to claim 5, further comprising forming an insulating protective layer on the line build-up structure, and exposing the electrical contact pads to the insulating protective layer. The method of fabricating a semiconductor package according to claim 10, further comprising forming an encapsulant on the insulating protective layer to encapsulate the semiconductor device. The method of fabricating a semiconductor package according to claim 5, further comprising forming an encapsulant on the circuit build-up structure to encapsulate the semiconductor device. A method for fabricating a semiconductor package without a core layer includes: providing a load-bearing structure having a first metal layer and a second metal layer in sequence; and patterning the second metal layer to form a plurality of electrical connection pads, And exposing the first metal layer; forming a line build-up structure on the first metal layer and the electrical connection pads, and the circuit build-up structure has a plurality of electrical contact pads; and at least one semiconductor component is disposed on the line And the semiconductor device is electrically connected to the electrical contact pads; and the carrier structure and the first metal layer are removed by a stripping method. The method of manufacturing a package substrate according to claim 13 , wherein the carrier structure has a first side and a second side opposite to the first side, and the first The first and second metal layers are on one side and the third metal layer is on the second side. The method of manufacturing a package substrate according to claim 14, wherein the first and third metal layers are copper foil. The method of manufacturing a package substrate according to claim 13, wherein the second metal layer is formed on the first metal layer by electroplating. The method of manufacturing a package substrate according to claim 13, wherein the electrical connection pads are formed by etching. The method for manufacturing a package substrate according to claim 13, wherein the circuit build-up structure has at least one dielectric layer, a circuit layer formed on the dielectric layer, and a dielectric layer formed in the dielectric layer. The plurality of conductive blind vias are electrically connected to the circuit layer and the electrical connection pads, and the electrical contact pads are part of the outermost circuit layer. The method for manufacturing a package substrate according to claim 13 further comprises forming an insulating protective layer on the line build-up structure, and exposing the electrical contact pads to the insulating protective layer. The method of fabricating a semiconductor package according to claim 19, further comprising forming an encapsulant on the insulating protective layer to encapsulate the semiconductor device. The method of fabricating a semiconductor package according to claim 13 further comprising forming an encapsulant on the line build-up structure to encapsulate the semiconductor device.