TWI604542B - Package substrate and the manufacture thereof - Google Patents
Package substrate and the manufacture thereof Download PDFInfo
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- TWI604542B TWI604542B TW106100992A TW106100992A TWI604542B TW I604542 B TWI604542 B TW I604542B TW 106100992 A TW106100992 A TW 106100992A TW 106100992 A TW106100992 A TW 106100992A TW I604542 B TWI604542 B TW I604542B
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- package substrate
- circuit layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
本發明係有關一種封裝基板之製法，尤指一種單層線路之封裝基板及其製法。 The invention relates to a method for manufacturing a package substrate, in particular to a package substrate with a single layer circuit and a method for manufacturing the same.
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態，而針對不同之封裝結構，亦發展出各種封裝用之封裝基板，以供接置半導體晶片，其中，為滿足半導體封裝件薄型化的封裝需求，遂而研發出一種無核心(coreless)之封裝基板之技術。 With the development of the electronics industry, today's electronic products have been designed in a light, short, and versatile manner. Semiconductor packaging technology has also developed different packaging types, and various packaging structures have been developed for various packaging structures. The package substrate is used to connect semiconductor wafers. In order to meet the packaging requirements for thinning semiconductor packages, a coreless package substrate technology has been developed.
第1圖係為習知半導體封裝件3之剖視示意圖，該半導體封裝件3之製法係將半導體元件30藉由黏著層33結合於一具有第一線路層11及第二線路層12之封裝基板1上，再以複數銲線31電性連接該半導體元件30與該第一線路層11，之後以封裝材32包覆該些銲線31與該半導體元件30。 1 is a schematic cross-sectional view of a conventional semiconductor package 3, which is formed by bonding a semiconductor device 30 to a package having a first wiring layer 11 and a second wiring layer 12 by an adhesive layer 33. The semiconductor element 30 and the first wiring layer 11 are electrically connected to the substrate 1 by a plurality of bonding wires 31, and then the bonding wires 31 and the semiconductor device 30 are covered with a sealing material 32.
再者，該封裝基板1之製法係先提供一金屬板，再以多次蝕刻方式形成該第一線路層11及第二線路層12，並以防銲層10包覆該第一線路層11及第二線路層12。 Furthermore, the method of manufacturing the package substrate 1 is to first provide a metal plate, and then form the first circuit layer 11 and the second circuit layer 12 by multiple etching, and cover the first circuit layer 11 with the solder resist layer 10. And the second circuit layer 12.
惟，於習知該封裝基板之製法中，須經過多次蝕刻製程以形成所需的線路層，然而受限於蝕刻製程之能力，致使該線路層之線寬/線距之細化程度有限，因而難以降低該線路層的厚度，進而難以降低該封裝基板之厚度，故在該封裝基板之厚度難以降低的情況下，半導體封裝件之整體厚度亦難以降低。 However, in the conventional method of manufacturing the package substrate, a plurality of etching processes are required to form a desired wiring layer, but limited by the etching process capability, the line width/line distance of the circuit layer is limited. Therefore, it is difficult to reduce the thickness of the wiring layer, and it is difficult to reduce the thickness of the package substrate. Therefore, when the thickness of the package substrate is difficult to be reduced, the overall thickness of the semiconductor package is also difficult to be reduced.
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。 Therefore, how to overcome the above problems of the prior art has become a difficult problem to be overcome in the industry.
鑑於上述習知技術之種種缺失，本發明係提供一種封裝基板之製法，係包括：以電鍍方式形成線路層於一第一承載件上，其中，該線路層具有相對之第一表面與第二表面，並以該第二表面結合該第一承載件；形成一具有複數第一開孔之第一絕緣保護層於該第一承載件上，以令該線路層之第一表面外露於該第一開孔，其中，該第一絕緣保護層具有相對之第一側與第二側，並以該第二側結合該第一承載件；移除該第一承載件，以外露該線路層之第二表面與該第一絕緣保護層之第二側；以及形成一具有複數第二開孔之第二絕緣保護層於該第一絕緣保護層之第二側與該線路層之第二表面上，以令該線路層之第二表面外露於該些第二開孔。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a method for fabricating a package substrate, comprising: forming a circuit layer on a first carrier by electroplating, wherein the circuit layer has a first surface and a second surface opposite to each other Forming a first carrier with the second surface; forming a first insulating protective layer having a plurality of first openings on the first carrier to expose the first surface of the circuit layer to the first surface An opening, wherein the first insulating protective layer has opposite first and second sides, and the first carrier is coupled with the second side; the first carrier is removed, and the circuit layer is exposed a second surface and a second side of the first insulating protective layer; and a second insulating protective layer having a plurality of second openings on the second side of the first insulating protective layer and the second surface of the wiring layer So that the second surface of the circuit layer is exposed to the second openings.
本發明復提供一種封裝基板，係包括：第一絕緣保護層，係具有相對之第一側及第二側；線路層，係設於該第一絕緣保護層中且具有相對之第一表面及第二表面，其 中，該線路層之第一表面與該第一絕緣保護層之第一側間形成有段差，該線路層之第二表面與該第一絕緣保護層之第二側齊平，且第一絕緣保護層形成有複數第一開孔以外露出該線路層之第一表面；以及第二絕緣保護層，係設於該第一絕緣保護層之第二側與該線路層之第二表面上，且第二絕緣保護層形成有複數第二開孔以外露出該線路層之第二表面。 The present invention further provides a package substrate, comprising: a first insulating protective layer having opposite first and second sides; and a circuit layer disposed in the first insulating protective layer and having a first surface opposite thereto Second surface Forming a step between the first surface of the circuit layer and the first side of the first insulating protective layer, the second surface of the circuit layer being flush with the second side of the first insulating protective layer, and the first insulating The protective layer is formed with a plurality of first openings to expose the first surface of the circuit layer; and a second insulating protective layer is disposed on the second side of the first insulating protective layer and the second surface of the circuit layer, and The second insulating protective layer is formed with a plurality of second openings to expose the second surface of the circuit layer.
前述之封裝基板與製法中，該線路層之線寬係為35um以下。 In the above package substrate and manufacturing method, the line width of the wiring layer is 35 μm or less.
前述之製法中，該線路層之製程係包括：於該第一承載件上形成阻層，且該阻層形成有複數開口區，以令該第一承載件之部分表面外露於該些開口區；以電鍍方式形成該線路層於該些開口區中；以及移除該阻層。 In the above method, the process of the circuit layer includes: forming a resist layer on the first carrier, and forming a plurality of open regions in the resist layer to expose a portion of the surface of the first carrier to the open regions Forming the wiring layer in the open regions by electroplating; and removing the resist layer.
前述之封裝基板與製法中，該線路層之第一表面係具有複數銲墊，令該些銲墊外露於該些第一開孔。 In the above package substrate and manufacturing method, the first surface of the circuit layer has a plurality of pads, and the pads are exposed to the first openings.
前述之封裝基板與製法中，該線路層之第二表面係具有複數電性接觸墊，令該些電性接觸墊外露於該些第二開孔。 In the above package substrate and manufacturing method, the second surface of the circuit layer has a plurality of electrical contact pads, and the electrical contact pads are exposed to the second openings.
前述之封裝基板與製法中，該第一絕緣保護層之第一側相對該線路層之第一表面的厚度係等於該第二絕緣保護層的厚度。 In the above package substrate and manufacturing method, the thickness of the first side of the first insulating protective layer relative to the first surface of the wiring layer is equal to the thickness of the second insulating protective layer.
前述之封裝基板與製法中，該第一絕緣保護層之第一側相對該線路層之第一表面的厚度、該線路層之厚度與該第二絕緣保護層的厚度係均等。 In the above package substrate and manufacturing method, the thickness of the first side of the first insulating protective layer relative to the first surface of the wiring layer, the thickness of the wiring layer, and the thickness of the second insulating protective layer are equal.
前述之封裝基板與製法中，該第一絕緣保護層係為防銲層，且該第二絕緣保護層係為防銲層。 In the above package substrate and manufacturing method, the first insulating protective layer is a solder resist layer, and the second insulating protective layer is a solder resist layer.
前述之製法中，復包括於移除該第一承載件之前，設置一第二承載件於該第一絕緣保護層之第一側與該線路層之第一表面上。例如，該線路層之第一表面與該第二承載件之間具有間隙，且該第一絕緣保護層之第一側與該第二承載件係直接相接觸。 In the above method, before the removal of the first carrier, a second carrier is disposed on the first side of the first insulating protective layer and the first surface of the circuit layer. For example, there is a gap between the first surface of the circuit layer and the second carrier, and the first side of the first insulating protection layer is in direct contact with the second carrier.
另外，前述之封裝基板與製法中，復包括形成表面處理層於該些第二開孔中之該線路層之第二表面上。 In addition, in the foregoing package substrate and manufacturing method, the surface treatment layer is formed on the second surface of the circuit layer in the second openings.
由上可知，本發明之封裝基板及其製法，係以電鍍方式形成該線路層，因而可得到較小的線寬/線距(如線寬35um以下及/或線距35um以下)，故本發明有利於該封裝基板之薄型化，並使該封裝基板有較佳的佈線能力。 It can be seen from the above that the package substrate of the present invention and the method for manufacturing the same are formed by electroplating, so that a small line width/line spacing (for example, a line width of 35 μm or less and/or a line spacing of 35 μm or less) can be obtained. The invention facilitates the thinning of the package substrate and enables the package substrate to have better wiring capability.
1,2‧‧‧封裝基板 1,2‧‧‧Package substrate
11‧‧‧第一線路層 11‧‧‧First line layer
12‧‧‧第二線路層 12‧‧‧Second circuit layer
200‧‧‧銲墊 200‧‧‧ solder pads
201‧‧‧電性接觸墊 201‧‧‧Electrical contact pads
10‧‧‧防銲層 10‧‧‧ solder mask
20‧‧‧線路層 20‧‧‧Line layer
20a‧‧‧第一表面 20a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
21‧‧‧第一絕緣保護層 21‧‧‧First insulation protection layer
21a‧‧‧第一側 21a‧‧‧ first side
21b‧‧‧第二側 21b‧‧‧ second side
210‧‧‧第一開孔 210‧‧‧First opening
22‧‧‧第二絕緣保護層 22‧‧‧Second insulation protection layer
220‧‧‧第二開孔 220‧‧‧Second opening
23‧‧‧表面處理層 23‧‧‧Surface treatment layer
3‧‧‧半導體封裝件 3‧‧‧Semiconductor package
30‧‧‧半導體元件 30‧‧‧Semiconductor components
31‧‧‧銲線 31‧‧‧welding line
32‧‧‧封裝材 32‧‧‧Package
33‧‧‧黏著層 33‧‧‧Adhesive layer
4‧‧‧承載件 4‧‧‧ Carrier
7‧‧‧阻層 7‧‧‧resist layer
70‧‧‧開口區 70‧‧‧Open area
8‧‧‧第一承載件 8‧‧‧First carrier
80‧‧‧金屬層 80‧‧‧metal layer
9‧‧‧第二承載件 9‧‧‧Second carrier
t‧‧‧段差 T‧‧‧
r,h,d‧‧‧厚度 r,h,d‧‧‧thickness
第1圖係為習知半導體封裝件之剖視示意圖；以及第2A至2G圖係為本發明之封裝基板之製法之剖視示意圖。 1 is a schematic cross-sectional view of a conventional semiconductor package; and 2A to 2G are schematic cross-sectional views showing a method of fabricating the package substrate of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定 條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. Limited The conditions are not technically meaningful, and any modification of the structure, change of the proportional relationship or adjustment of the size should remain in the present invention without affecting the effects and the achievable objectives of the present invention. The technical content revealed can be covered. In the meantime, the terms "upper", "first", "second", "one" and "the" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes.
請參閱第2A至2G圖，係為本發明之單層線路之封裝基板2之製法之剖視示意圖。 Please refer to FIGS. 2A to 2G, which are cross-sectional views showing the manufacturing method of the package substrate 2 of the single-layer circuit of the present invention.
如第2A至2C圖所示，係於一表面具有金屬層80之第一承載件8上以電鍍方式形成一線路層20。 As shown in FIGS. 2A to 2C, a wiring layer 20 is formed by electroplating on a first carrier 8 having a metal layer 80 on its surface.
例如，先於該第一承載件8之金屬層80上形成一如光阻之阻層7，該阻層7經曝光顯影製程後形成有複數開口區70，以外露該金屬層80之部分表面，再於該些開口區70中電鍍如銅之金屬材以形成該線路層20，之後移除該阻層7。 For example, a resistive layer 7 such as a photoresist is formed on the metal layer 80 of the first carrier 8. The resist layer 7 is formed with a plurality of open regions 70 after exposure and development processes to expose portions of the surface of the metal layer 80. Then, a metal material such as copper is plated in the opening regions 70 to form the wiring layer 20, and then the resist layer 7 is removed.
於本實施例中，該第一承載件8係為銅箔基板，即該金屬層80係為銅箔且佈設於該第一承載件8之相對兩側上，且該線路層20可同時形成於承載板8相對兩側之金屬層80上或僅形成於單側之金屬層80上。 In this embodiment, the first carrier 8 is a copper foil substrate, that is, the metal layer 80 is a copper foil and is disposed on opposite sides of the first carrier 8 , and the circuit layer 20 can be simultaneously formed. On the metal layer 80 on opposite sides of the carrier board 8, or only on the metal layer 80 on one side.
再者，該線路層20之線寬及/或線距係為35um以下，且該線路層20係具有相對之第一表面20a與第二表面20b，並以其第二表面20b係結合該金屬層80。 Furthermore, the line layer 20 has a line width and/or a line spacing of 35 um or less, and the circuit layer 20 has a first surface 20a and a second surface 20b opposite thereto, and the second surface 20b is bonded to the metal. Layer 80.
如第2D圖所示，形成一第一絕緣保護層21於該第一承載件8之金屬層80上，且該第一絕緣保護層21形成有複數第一開孔210，使該線路層20之第一表面20a外露於該第一開孔210，俾供作為銲墊200。 As shown in FIG. 2D, a first insulating protective layer 21 is formed on the metal layer 80 of the first carrier 8, and the first insulating protective layer 21 is formed with a plurality of first openings 210, so that the circuit layer 20 is formed. The first surface 20a is exposed to the first opening 210, and is used as the bonding pad 200.
於本實施例中，該第一絕緣保護層21係為防銲層，且其具有相對之第一側21a及第二側21b，並以該第二側21b結合該金屬層80。 In the embodiment, the first insulating protective layer 21 is a solder resist layer, and has a first side 21a and a second side 21b opposite to each other, and the metal layer 80 is bonded by the second side 21b.
如第2E圖所示，設置一第二承載件9於該第一絕緣保護層21之第一側21a與該線路層20之第一表面20a上，以遮蓋該線路層20之第一表面20a。接著，移除該第一承載件8，以外露該線路層20之第二表面20b與該第一絕緣保護層21之第二側21b。另外，移除該第一承載件8更包括移除該金屬層80以外露該線路層20之第二表面20b，且使該線路層20之第二表面20b與第一絕緣保護層21之第二側21b齊平。 As shown in FIG. 2E, a second carrier member 9 is disposed on the first side 21a of the first insulating protective layer 21 and the first surface 20a of the circuit layer 20 to cover the first surface 20a of the circuit layer 20. . Next, the first carrier 8 is removed, and the second surface 20b of the circuit layer 20 and the second side 21b of the first insulating protection layer 21 are exposed. In addition, removing the first carrier 8 further includes removing the second surface 20b of the circuit layer 20 from the metal layer 80, and making the second surface 20b of the circuit layer 20 and the first insulating protective layer 21 The two sides 21b are flush.
於本實施例中，該線路層20之第一表面20a與該第二承載件9之間具有間隙，且該第一絕緣保護層21之第一側21a與該第二承載件9係直接相接觸，亦即該線路層20之第一表面20a與該第一絕緣保護層21之第一側21a形成有段差t，另該線路層20之第二表面20b與該第一絕緣保護層21之第二側21b齊平。 In this embodiment, the first surface 20a of the circuit layer 20 and the second carrier 9 have a gap therebetween, and the first side 21a of the first insulating protection layer 21 and the second carrier 9 are directly related to each other. Contact, that is, the first surface 20a of the circuit layer 20 and the first side 21a of the first insulating protective layer 21 are formed with a step t, and the second surface 20b of the circuit layer 20 and the first insulating protective layer 21 The second side 21b is flush.
如第2F圖所示，形成一第二絕緣保護層22於該第一絕緣保護層21與該線路層20之第二表面20b上，且該第二絕緣保護層22形成有複數第二開孔220，以令該些線路 層20之第二表面20b外露於該些第二開孔220，俾供作為電性接觸墊201。 As shown in FIG. 2F, a second insulating protective layer 22 is formed on the first insulating protective layer 21 and the second surface 20b of the wiring layer 20, and the second insulating protective layer 22 is formed with a plurality of second openings. 220 to make the lines The second surface 20b of the layer 20 is exposed to the second openings 220 and serves as the electrical contact pads 201.
於本實施例中，該第二絕緣保護層22係為防銲層。 In the embodiment, the second insulating protective layer 22 is a solder resist layer.
再者，該第一絕緣保護層21之第一側21a相對該線路層20之第一表面20a的厚度r係等於該第二絕緣保護層22的厚度h(即r=h)。或者，該第一絕緣保護層21之第一側21a相對該線路層20之第一表面20a的厚度r、該線路層20之厚度d與該第二絕緣保護層22的厚度h係均等(即r=h=d)。 Moreover, the thickness r of the first side 21a of the first insulating protective layer 21 relative to the first surface 20a of the wiring layer 20 is equal to the thickness h of the second insulating protective layer 22 (ie, r=h). Alternatively, the thickness r of the first side 21a of the first insulating protective layer 21 relative to the first surface 20a of the wiring layer 20, the thickness d of the wiring layer 20, and the thickness h of the second insulating protective layer 22 are equal (ie, r=h=d).
如第2G圖所示，復可形成一表面處理層23於該些第二開孔220中之線路層20之第二表面20b(即電性接觸墊201)上。 As shown in FIG. 2G, a surface treatment layer 23 is formed on the second surface 20b of the circuit layer 20 (ie, the electrical contact pads 201) in the second openings 220.
於本實施例中，形成該表面處理層23之材料係包含電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)或有機保焊劑(Organic Solderability Preservative，簡稱OSP)。 In the present embodiment, the material forming the surface treatment layer 23 comprises electroplated nickel/gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), and electroless tin plating (Immersion Tin). Or Organic Solderability Preservative (OSP).
另外，於後續製程中，可移除該第二承載件9。 In addition, the second carrier 9 can be removed in a subsequent process.
透過前述製法，本發明復揭示一種封裝基板2，該封裝基板2係包括一第一絕緣保護層21、設於該第一絕緣保護層21中之線路層20以及設於該第一絕緣保護層21上之第二絕緣保護層22。 The present invention discloses a package substrate 2 including a first insulating protective layer 21, a wiring layer 20 disposed in the first insulating protective layer 21, and a first insulating protective layer. A second insulating protective layer 22 on the 21st.
該第一絕緣保護層21具有相對之第一側21a及第二側21b。 The first insulating protective layer 21 has a first side 21a and a second side 21b opposite to each other.
該線路層20係設於該第一絕緣保護層21中且具有相 對之第一表面20a及第二表面20b，其中，第一絕緣保護層21形成有複數第一開孔210以外露出該線路層20之第一表面20a，該線路層20之第一表面20a與該第一絕緣保護層21之第一側21a間形成有段差t，且該線路層20之第二表面20b與該第一絕緣保護層21之第二側21b齊平。 The circuit layer 20 is disposed in the first insulating protective layer 21 and has a phase The first surface 20a and the second surface 20b are formed, wherein the first insulating protective layer 21 is formed with a plurality of first openings 210 exposing the first surface 20a of the circuit layer 20, and the first surface 20a of the circuit layer 20 is A step t is formed between the first side 21a of the first insulating protective layer 21, and the second surface 20b of the wiring layer 20 is flush with the second side 21b of the first insulating protective layer 21.
該第二絕緣保護層22係設於該第一絕緣保護層21之第二側21b與該線路層20之第二表面20b上，且形成有複數第二開孔220以外露出該線路層20之第二表面20b。 The second insulating protective layer 22 is disposed on the second side 21b of the first insulating protective layer 21 and the second surface 20b of the circuit layer 20, and is formed with a plurality of second openings 220 to expose the circuit layer 20. Second surface 20b.
綜上所述，本發明之封裝基板2及其製法，主要藉由電鍍形成該線路層20，因而能得到較小的線寬/線距(如線寬35um以下及/或線距35um以下)，以利於該封裝基板2之薄型化，且使該封裝基板2有較佳的佈線能力。 In summary, the package substrate 2 of the present invention and the method of manufacturing the same, the wiring layer 20 is mainly formed by electroplating, so that a smaller line width/line spacing (for example, a line width of 35 μm or less and/or a line spacing of 35 μm or less) can be obtained. In order to facilitate the thinning of the package substrate 2, the package substrate 2 has a better wiring capability.
再者，相較於習知技術之蝕刻製程，本發明之電鍍製程因可減少曝光、顯影等製程之次數而可節省成本。 Moreover, the electroplating process of the present invention can save cost by reducing the number of processes such as exposure and development, compared to the etching process of the prior art.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧封裝基板 2‧‧‧Package substrate
20‧‧‧線路層 20‧‧‧Line layer
20a‧‧‧第一表面 20a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
201‧‧‧電性接觸墊 201‧‧‧Electrical contact pads
21‧‧‧第一絕緣保護層 21‧‧‧First insulation protection layer
21a‧‧‧第一側 21a‧‧‧ first side
21b‧‧‧第二側 21b‧‧‧ second side
22‧‧‧第二絕緣保護層 22‧‧‧Second insulation protection layer
220‧‧‧第二開孔 220‧‧‧Second opening
23‧‧‧表面處理層 23‧‧‧Surface treatment layer
9‧‧‧第二承載件 9‧‧‧Second carrier
Claims (17)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106100992A TWI604542B (en) | 2017-01-12 | 2017-01-12 | Package substrate and the manufacture thereof |
| CN201710043165.0A CN108305836B (en) | 2017-01-12 | 2017-01-19 | Package substrate and method for fabricating the same |
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| Application Number | Priority Date | Filing Date | Title |
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| TW106100992A TWI604542B (en) | 2017-01-12 | 2017-01-12 | Package substrate and the manufacture thereof |
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| TWI604542B true TWI604542B (en) | 2017-11-01 |
| TW201826415A TW201826415A (en) | 2018-07-16 |
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| TW (1) | TWI604542B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200836606A (en) * | 2007-02-16 | 2008-09-01 | Unimicron Technology Corp | Circuit board process |
| TW201530725A (en) * | 2014-01-29 | 2015-08-01 | 矽品精密工業股份有限公司 | Stacked group as well as manufacturing method thereof and substrate structure |
| TW201620087A (en) * | 2014-11-17 | 2016-06-01 | 矽品精密工業股份有限公司 | Package structure and method of manufacture |
| TW201701419A (en) * | 2015-06-29 | 2017-01-01 | 矽品精密工業股份有限公司 | Package structure and the manufacture thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI419278B (en) * | 2010-10-26 | 2013-12-11 | Unimicron Technology Corp | Package substrate and fabrication method thereof |
| TWI496258B (en) * | 2010-10-26 | 2015-08-11 | Unimicron Technology Corp | Fabrication method of package substrate |
| TWI487444B (en) * | 2013-05-07 | 2015-06-01 | Unimicron Technology Corp | Carrier substrate and manufacturing method thereof |
| TWI525769B (en) * | 2013-11-27 | 2016-03-11 | 矽品精密工業股份有限公司 | Package substrate and manufacturing method thereof |
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2017
- 2017-01-12 TW TW106100992A patent/TWI604542B/en active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200836606A (en) * | 2007-02-16 | 2008-09-01 | Unimicron Technology Corp | Circuit board process |
| TW201530725A (en) * | 2014-01-29 | 2015-08-01 | 矽品精密工業股份有限公司 | Stacked group as well as manufacturing method thereof and substrate structure |
| TW201620087A (en) * | 2014-11-17 | 2016-06-01 | 矽品精密工業股份有限公司 | Package structure and method of manufacture |
| TW201701419A (en) * | 2015-06-29 | 2017-01-01 | 矽品精密工業股份有限公司 | Package structure and the manufacture thereof |
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| CN108305836B (en) | 2020-09-01 |
| CN108305836A (en) | 2018-07-20 |
| TW201826415A (en) | 2018-07-16 |
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