TWI435427B - Semiconductor carrier, package and method of forming same - Google Patents

Description

Semiconductor carrier and package and its manufacturing method

The invention relates to a carrier and a package and a manufacturing method thereof, in particular to a semiconductor carrier and a package and a manufacturing method thereof.

A Quad Flat Non-Leaded (QFN) semiconductor package is a package unit that exposes the wafer holder and the bottom surface of the pin to the bottom surface of the package layer. Generally, surface mount technology (SMT) is used. A quadrilateral planar leadless semiconductor package is attached to the printed circuit board to form a circuit module having a specific function.

Please refer to FIGS. 1A to 1H for a cross-sectional view of a conventional quadrilateral planar leadless semiconductor package and a method of fabricating the same.

As shown in Fig. 1A, a copper substrate 10 having a first surface 10a and a second surface 10b opposite thereto is provided.

As shown in FIG. 1B, a plurality of first recesses 101 are formed on the second surface 10b of the copper substrate 10.

As shown in FIG. 1C, the resin material 11 is filled in each of the first recesses 101.

As shown in FIG. 1D, a resist layer 12 is formed on the first surface 10a of the copper substrate 10, and the resist layer 12 has a plurality of resistive opening 120 of the first surface 10a.

As shown in FIG. 1E, the first circuit layer 13 and the second circuit layer 14 are respectively plated on the exposed first surface 10a and the second surface 10b of the copper substrate 10, and the first circuit layer 13 has a space. The crystal pad 131 and the plurality of electrical connection pads 132.

As shown in FIG. 1F, the resist layer 12 is removed, and the first surface 10a is exposed.

As shown in FIG. 1G, the exposed copper substrate 10 is etched to form a second recess 102 connecting the resin material 11 and having a narrow top and bottom, so that the remaining copper substrate 10 is defined as corresponding respectively. The crystal pad 131 and a spacer 151 of the electrical connection pad 132 and the plurality of conductive pillars 152.

As shown in FIG. 1H, a semiconductor wafer 16 is disposed on the crystal pad 131, and the semiconductor wafer 16 and the electrical connection pad 132 are electrically connected to the plurality of bonding wires 17, and a cladding is formed on the first surface 10a side. The semiconductor wafer 16, the bonding wire 17 and the encapsulant 18 of the first wiring layer 13 are provided.

However, the conventional process is to etch the copper substrate 10 not covered by the first circuit layer 13 after electroplating to form the first wiring layer 13, but if the etching time is too long, the copper under the first wiring layer 13 The substrate 10 is over-etched and undercut, so that the first circuit layer 13 protrudes from the copper substrate 10, thereby easily causing the first circuit layer 13 to peel or break; further, in order to avoid Electrical interference, there must be sufficient spacing between adjacent two lines, for example 40 micrometers (μm), so the bottom width of the second recess 102 having a narrow top and bottom width must be at least 40 micrometers, which makes the top width larger than 40 micrometers, for example 80 micrometers, results in a pitch of the first wiring layer 13 of more than 40 μm, which cannot meet the requirements of fine pitch.

Therefore, how to avoid the various problems in the above-mentioned prior art, and to solve the problem that the wiring layer of the tetragonal planar leadless semiconductor package is easily peeled off and the line pitch is too large has become a problem to be solved at present.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor carrier comprising: a dielectric layer formed with at least one crystal pillar and a plurality of conductive pillars penetrating the dielectric layer, and the at least one crystal pillar And a plurality of conductive pillars having a first surface and a second surface; the first circuit layer is formed on the first surface side of the dielectric layer, the crystal pillar and the end of the conductive pillar, and has electrical properties respectively a pad and a first electrical connection pad connecting the spacer and the conductive pillar; and a second circuit layer formed on the end of the dielectric layer, the crystal pillar and the conductive pillar on the second surface side, And having a thermal pad and a second electrical connection pad respectively corresponding to the crystal column and the conductive column.

The present invention further provides a semiconductor package comprising: a dielectric layer formed with at least one crystal pillar and a plurality of conductive pillars penetrating the dielectric layer, wherein the at least one crystal pillar and the plurality of conductive pillars are opposite to each other a first surface and a second surface; the first circuit layer is formed on the first surface side of the dielectric layer, the crystal column and the end of the conductive column, and has a connection between the crystal column and the conductive column And a first circuit layer formed on the second surface side of the dielectric layer, the crystal column and the end of the conductive column, and has a corresponding crystal column and a thermal pad of the conductive post and a second electrical connection pad; a semiconductor wafer is disposed on the crystal pad; a plurality of bonding wires electrically connecting the semiconductor chip and the first electrical connection pad; and an encapsulant formed on the The first surface side covers the semiconductor wafer, the bonding wire and the first wiring layer.

The invention provides a method for fabricating a semiconductor carrier, comprising: forming a plurality of recesses on a first surface of a carrier having opposite first and second surfaces; filling a dielectric layer in each of the recesses; The second surface side removes a portion of the thickness of the carrier plate, exposing the dielectric layer, and the remaining carrier plate is defined as at least one crystal column and a plurality of conductive columns; and the bearing on the first surface side Forming a first circuit layer on the board, and forming a second circuit layer on the carrier plate on the second surface side, wherein the first circuit layer has a pad and a pad electrically connected to the crystal column and the conductive column respectively An electrical connection pad, and the second circuit layer has a thermal pad and a second electrical connection pad respectively corresponding to the crystal column and the conductive column.

The present invention provides a method of fabricating a semiconductor package, comprising: providing a semiconductor carrier, comprising: a dielectric layer formed with at least one crystal pillar and a plurality of conductive pillars penetrating the dielectric layer, and the at least The first crystal layer and the plurality of conductive pillars have opposite first and second surfaces; the first circuit layer is formed on the end of the dielectric layer, the crystal pillar and the conductive pillar on the first surface side, and And a first electrical connection pad, wherein the second circuit layer is formed on the second surface side of the dielectric layer, the crystal column and the conductive column And a thermal pad and a second electrical connection pad respectively corresponding to the crystal column and the conductive column; a semiconductor wafer is disposed on the crystal pad, and the semiconductor wafer is electrically connected to the first electrical device by a plurality of bonding wires Connecting a pad; and forming an encapsulant covering the semiconductor wafer, the bonding wire and the first wiring layer on the first surface side.

As can be seen from the above, since the present invention completes the substrate including the dielectric layer, the crystal pillar and the conductive pillar, and then forms a wiring layer on the dielectric layer, the crystal pillar and the conductive pillar, it is possible to avoid forming the circuit first. Over-etching and undercutting of the layer, re-etching the substrate, thereby avoiding the problem of peeling and cracking of the wiring layer; further, since the wiring layer can be formed on the dielectric layer without being subjected to the post-etching of the crystalline pillar and the conductive pillar The spacing is limited, so the effect of fine pitch can be achieved.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "side", "top", "bottom" and "one" are used in this description for convenience of description and are not intended to limit the invention. The scope, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.

First embodiment

2A to 2M are cross-sectional views showing a first embodiment of a semiconductor carrier, a semiconductor package, and a method of fabricating the same according to the present invention, wherein the second L' is a partial plan view of the 2L.

First, as shown in FIG. 2A, a carrier 20 having an opposite first surface 20a and a second surface 20b is provided, and a first resist layer 21a and a second surface are formed on the first surface 20a and the second surface 20b, respectively. The first resistive layer 21b is formed with a plurality of first resistive layer openings 210 exposing the first surface 20a. The material of the carrier 20 is copper.

As shown in FIG. 2B, a portion of the carrier layer 20 in each of the first barrier layer openings 210 is removed by etching, for example, to form a plurality of recesses 200, and the recesses 200 are oriented in a width from the first surface 20a. The shape of the second surface 20b is tapered; then, the first resist layer 21a and the second resist layer 21b are removed.

As shown in FIG. 2C, a dielectric layer 22 is formed on each of the recesses 200 and the first surface 20a.

As shown in FIG. 2D, the dielectric layer 22 is removed from the first surface 20a by, for example, grinding.

As shown in FIG. 2E, a third resist layer 23 is formed on the first surface 20a and the dielectric layer 22.

As shown in FIG. 2F, a portion of the carrier 20 is removed from the second surface 20b side, and the dielectric layer 22 is exposed, so that the remaining carrier 20 is defined as at least one crystal pillar 201 and a plurality Conductive column 202.

As shown in FIG. 2G, the third resist layer 23 is removed, and, for example, copper is formed on the first surface 20a side and the second surface 20b side of the dielectric layer 22 and the carrier 20, for example, by sputtering. The first conductive layer 24a and the second conductive layer 24b of the material.

As shown in FIG. 2H, a first patterned resist layer 25a and a second patterned resist layer 25b are formed on the first conductive layer 24a and the second conductive layer 24b, respectively, and the first patterned resist layer 25a and the first patterned resist layer 25a The two patterned resistive layers 25b respectively have first patterned openings 250a and second patterned openings 250b corresponding to the exposed portions of the first conductive layer 24a and the second conductive layer 24b.

As shown in FIG. 2I, the first wiring layer 26a and the second wiring layer 26b are respectively plated in the first patterned opening 250a and the second patterned opening 250b, and the first patterned resist layer is removed. And a second patterned layer 25b, wherein the first circuit layer 26a is formed on the dielectric layer 22 and the carrier 20 on the first surface 20a side, and has a connection between the crystal pillar 201 and the respectively The pad 261a of the conductive post 202 is connected to the first electrical connection pad 262a, and the second circuit layer 26b is formed on the dielectric layer 22 and the carrier 20 on the second surface 20b side, and has corresponding crystals respectively. The pillar 201 and the thermal pad 261b of the conductive post 202 and the second electrical connection pad 262b, and the material of the first circuit layer 26a and the second wiring layer 26b are silver, nickel/palladium/gold, or nickel/gold. As shown in FIG. 2J, the exposed first conductive layer 24a and the second conductive layer 24b are removed.

As shown in FIG. 2K, an insulating protective layer 27 is formed on the dielectric layer 22 and the second wiring layer 26b on the second surface 20b side, and the insulating protective layer 27 has a plurality of corresponding thermal conductive pads 261b and second. The insulating protective layer opening 270 of the electrical connection pad 262b thus constitutes the semiconductor carrier 2 of the present invention.

Next, the semiconductor carrier 2 is turned upside down. As shown in FIG. 2L, a semiconductor wafer 28 is disposed on the crystal pad 261a, and the semiconductor wafer 28 and the first electrical connection pad are electrically connected by a plurality of bonding wires 29. 262a, and forming an encapsulant 30 covering the semiconductor wafer 28, the bonding wire 29 and the first wiring layer 26a on the side of the first surface 20a, and forming a conductive component such as a solder ball in each of the insulating protective layer openings 270 31.

It is to be noted that, in other embodiments, as shown in FIG. 2L′, which is a partial top view of FIG. 2L (only the encapsulant 30 is omitted), the first circuit layer 26a of the semiconductor wafer 28 is placed in addition to the first In addition to the electrical connection pad 262a, a trace 263a is also included, which shortens the length of the bonding wire 29 and reduces the cost. Similarly, the second circuit layer 26b may also include a trace (not shown). .

As shown in FIG. 2M, a singulation step is performed to constitute the complex semiconductor package 3.

Second embodiment

Please refer to FIG. 3, which is a cross-sectional view showing a second embodiment of the semiconductor package of the present invention.

The present embodiment is substantially the same as the first embodiment, and the main difference is that the semiconductor package 3 of the embodiment is disposed on the second circuit layer 26b, and the specific method of the embodiment is Those of ordinary skill in the art to which the present invention pertains can be easily understood from the first embodiment, and thus will not be described again.

The present invention further provides a semiconductor carrier 2 comprising: a dielectric layer 22; at least one crystal pillar 201 and a plurality of conductive pillars 202 extending through the dielectric layer 22 and having opposite first and second surfaces 20a and The first circuit layer 26a is formed on the first surface 20a side of the dielectric layer 22, the crystal pillar 201 and the conductive pillar 202. The first circuit layer 26a is electrically connected to the crystal pillar 201 and The pad 261a of the conductive post 202 and the first electrical connection pad 262a; and the second circuit layer 26b are formed on the dielectric layer 22, the crystal pillar 201 and the conductive pillar 202 on the second surface 20b side. The second circuit layer 26b has a thermal pad 261b and a second electrical connection pad 262b respectively corresponding to the crystal pillar 201 and the conductive pillar 202.

The present invention further provides a semiconductor package 3 comprising: a dielectric layer 22; at least one crystal pillar 201 and a plurality of conductive pillars 202 extending through the dielectric layer 22 and having opposite first and second surfaces 20a and 20 The first circuit layer 26a is formed on the first surface 20a side of the dielectric layer 22, the crystal pillar 201 and the conductive pillar 202. The first circuit layer 26a is electrically connected to the crystal pillar 201 and The pad 261a of the conductive post 202 and the first electrical connection pad 262a; the second circuit layer 26b is formed on the dielectric layer 22, the crystal pillar 201 and the conductive pillar 202 on the second surface 20b side. The second circuit layer 26b has a thermal pad 261b and a second electrical connection pad 262b respectively corresponding to the crystal pillar 201 and the conductive pillar 202; the semiconductor wafer 28 is disposed on the crystal pad 261a; the plurality of bonding wires 29 are electrically The semiconductor wafer 28 and the first electrical connection pad 262a are connected to each other; and the encapsulant 30 is formed on the first surface 20a side and covers the semiconductor wafer 28, the bonding wire 29 and the first wiring layer 26a.

In the foregoing semiconductor carrier 2 and the semiconductor package 3, an insulating protective layer 27 is formed on the dielectric layer 22 and the second wiring layer 26b on the second surface 20b side, and the insulating protective layer 27 has The plurality of insulating protective layer openings 270 are exposed to the respective thermal pad 261b and the second electrical connection pad 262b.

In the semiconductor carrier 2 and the semiconductor package 3 of the present invention, the column diameter of the crystal pillar 201 and the conductive pillar 202 is increased from the end of the first surface 20a toward the end of the second surface 20b, or The end of the second surface 20b is increased toward the end of the first surface 20a (not shown), and the first circuit layer 26a and the second circuit layer 26b are made of silver, nickel/palladium/gold. Or, nickel/gold, the first circuit layer 26a (or the second circuit layer 26b) includes traces 263a.

The semiconductor package 3 includes a conductive element 31 formed in each of the insulating protective layer openings 270.

In summary, compared with the prior art, the present invention first completes a substrate including a dielectric layer, a crystal column and a conductive pillar, and then forms a line on the dielectric layer, the crystal pillar and the conductive pillar. Layer, thus avoiding the problem of excessive etching and undercutting of the circuit layer and re-etching of the substrate, thereby avoiding the problem of peeling and cracking of the wiring layer; further, since the wiring layer can be formed on the dielectric layer without being etched The spacing between the crystal column and the conductive column is limited, so that the fine pitch effect can be achieved.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10. . . Copper substrate

10a, 20a. . . First surface

10b, 20b. . . Second surface

101. . . First recess

102. . . Second recess

11. . . Resin material

12. . . Resistance layer

120. . . Resistive opening

13,26a. . . First circuit layer

131,261a. . . Crystal pad

132. . . Electrical connection pad

14,26b. . . Second circuit layer

151,201. . . Crystal column

152,202. . . Conductive column

16,28. . . Semiconductor wafer

17,29. . . Welding wire

18,30. . . Encapsulant

20. . . Carrier board

200. . . Concave

21a. . . First resistive layer

21b. . . Second resistive layer

210. . . First barrier opening

twenty two. . . Dielectric layer

twenty three. . . Third resistive layer

24a. . . First conductive layer

24b. . . Second conductive layer

25a. . . First patterned resist layer

25b. . . Second patterned resist layer

250a. . . First patterned opening

250b. . . Second patterned opening

262a. . . First electrical connection pad

263a. . . Trace

261b. . . Thermal pad

262b. . . Second electrical connection pad

27. . . Insulating protective layer

270. . . Insulating protective layer opening

31. . . Conductive component

2. . . Semiconductor carrier

3. . . Semiconductor package

1A to 1H are cross-sectional views of a conventional quad flat unguided semiconductor package and a method of manufacturing the same;

2A to 2M are cross-sectional views showing a first embodiment of a semiconductor carrier, a semiconductor package, and a method of fabricating the same according to the present invention, wherein a second top view of the second L' is a partial plan view;

Figure 3 is a cross-sectional view showing a second embodiment of the semiconductor package of the present invention.

2. . . Semiconductor carrier

20. . . Carrier board

20a. . . First surface

20b. . . Second surface

201. . . Crystal column

202. . . Conductive column

twenty two. . . Dielectric layer

24a. . . First conductive layer

24b. . . Second conductive layer

26a. . . First circuit layer

26b. . . Second circuit layer

261a. . . Crystal pad

261b. . . Thermal pad

262a. . . First electrical connection pad

262b. . . Second electrical connection pad

27. . . Insulating protective layer

270. . . Insulating protective layer opening

Claims (27)

A semiconductor carrier includes a dielectric layer formed with at least one crystal pillar and a plurality of conductive pillars penetrating the dielectric layer, and the at least one crystal pillar and the plurality of conductive pillars have a first surface opposite to a second surface; a first circuit layer formed on the first surface side of the dielectric layer, the crystal pillar and the end of the conductive pillar, and having a crystal pad electrically connected to the crystal pillar and the conductive pillar respectively And the first electrical connection pad; and the second circuit layer is formed on the second surface side of the dielectric layer, the crystal column and the end of the conductive column, and has a corresponding column and a conductive column respectively The thermal pad and the second electrical connection pad. The semiconductor carrier of claim 1, further comprising an insulating protective layer formed on the dielectric layer and the second wiring layer on the second surface side, and having a plurality of corresponding thermal conductive pads and The insulating protective layer of the two electrical connection pads is opened. The semiconductor carrier of claim 1, wherein the column of the crystal column and the conductive column is increased from an end of the first surface toward an end of the second surface. The semiconductor carrier of claim 1, wherein the first circuit layer comprises a trace. The semiconductor carrier of claim 1, wherein the second circuit layer comprises a trace. A semiconductor package includes a dielectric layer formed with at least one crystal pillar and a plurality of conductive pillars penetrating the dielectric layer, and the at least one crystal pillar and the plurality of conductive pillars have a first surface opposite to a second surface; the first circuit layer is formed on the first surface side of the dielectric layer, the crystal column and the end of the conductive column, and has a crystal pad electrically connected to the crystal column and the conductive column respectively And a first electrical connection pad; the second circuit layer is formed on the second surface side of the dielectric layer, the crystal column and the end of the conductive post, and has heat conduction corresponding to the crystal column and the conductive column respectively a pad and a second electrical connection pad; a semiconductor wafer is disposed on the crystal pad; a plurality of bonding wires electrically connecting the semiconductor wafer and the first electrical connection pad; and an encapsulant formed on the first surface a side to cover the semiconductor wafer, the bonding wire and the first wiring layer. The semiconductor package of claim 6, further comprising an insulating protective layer formed on the dielectric layer and the second wiring layer on the second surface side, and having a plurality of corresponding thermal conductive pads and corresponding The insulating protective layer of the two electrical connection pads is opened. The semiconductor package of claim 7, further comprising a conductive element formed in each of the openings of the insulating protective layer. The semiconductor package of claim 6, wherein the column of the crystal column and the conductive column is increased from an end of the first surface toward an end of the second surface. The semiconductor package of claim 6, wherein the column of the crystal column and the conductive column is increased from an end of the second surface toward an end of the first surface. The semiconductor package of claim 6, wherein the first circuit layer further comprises a trace. The semiconductor package of claim 6, wherein the second circuit layer comprises a trace. A method of fabricating a semiconductor carrier, comprising: forming a plurality of recesses on a first surface of a carrier having opposite first and second surfaces; filling a dielectric layer in each of the recesses; and from the second surface Removing the thickness of the carrier plate from the side, exposing the dielectric layer, and defining the remaining carrier plate as at least one crystal column and a plurality of conductive columns; and forming a first layer on the carrier plate on the first surface side a circuit layer, and a second circuit layer is formed on the carrier plate on the second surface side, wherein the first circuit layer has a pad and a first electrical connection electrically connected to the crystal column and the conductive column respectively a pad, and the second circuit layer has a thermal pad and a second electrical connection pad respectively corresponding to the crystal column and the conductive column. The method of manufacturing the semiconductor carrier of claim 13, wherein the first circuit layer is formed on the dielectric layer on the first surface side, and the second circuit layer is formed on the second surface. On the side of the dielectric layer. The method of manufacturing the semiconductor carrier of claim 13, wherein the step of forming the first circuit layer and the second circuit layer comprises: a dielectric layer on the first surface side and the second surface side Forming a first conductive layer and a second conductive layer on the carrier layer respectively; forming a first patterned resist layer and a second patterned resist layer on the first conductive layer and the second conductive layer, respectively, and the first patterned resist The first patterned opening and the second patterned opening of the first conductive layer and the second conductive layer respectively corresponding to the exposed portion and the second patterned opening layer; and the first patterned opening and the second pattern Forming the first circuit layer and the second circuit layer respectively in the opening; and removing the first patterned resist layer and the second patterned resist layer and the first conductive layer and the second conductive layer covered thereby. The method for manufacturing a semiconductor carrier according to claim 13, wherein the dielectric layer on the second surface side and the second circuit layer form an insulating protective layer, and the insulating protective layer has a plurality of corresponding exposed portions. The thermal pad and the insulating protective layer of the second electrical connection pad are opened. The method of fabricating a semiconductor carrier according to claim 13, wherein the recess has a shape in which the width is tapered from the first surface to the second surface. The method of fabricating a semiconductor carrier according to claim 13, wherein the first circuit layer further comprises a trace. The method of fabricating a semiconductor carrier according to claim 13, wherein the second circuit layer comprises a trace. A method of fabricating a semiconductor package, comprising: providing a semiconductor carrier, comprising: a dielectric layer formed with at least one crystal pillar and a plurality of conductive pillars penetrating the dielectric layer, and the at least one crystal pillar And a plurality of conductive pillars having a first surface and a second surface; the first circuit layer is formed on the first surface side of the dielectric layer, the crystal pillar and the end of the conductive pillar, and has electrical properties respectively a pad and a first electrical connection pad connecting the spacer and the conductive pillar; and a second circuit layer formed on the end of the dielectric layer, the crystal pillar and the conductive pillar on the second surface side, and a thermal pad and a second electrical connection pad respectively corresponding to the crystal column and the conductive column; a semiconductor wafer is disposed on the crystal pad, and the semiconductor wafer and the first electrical connection pad are electrically connected by a plurality of bonding wires; An encapsulant covering the semiconductor wafer, the bonding wire and the first wiring layer is formed on the first surface side. The method for manufacturing a semiconductor package according to claim 20, wherein the dielectric layer on the second surface side and the second circuit layer form an insulating protective layer, and the insulating protective layer has a plurality of corresponding exposed portions. The thermal pad and the insulating protective layer of the second electrical connection pad are opened. The method of fabricating a semiconductor package according to claim 21, comprising forming a conductive element in each of the openings of the insulating protective layer. The method for manufacturing a semiconductor package according to claim 20, further comprising performing a singulation step. The method of fabricating a semiconductor package according to claim 20, wherein a column diameter of the crystal column and the conductive column is increased from an end of the first surface toward an end of the second surface. The method of fabricating a semiconductor package according to claim 20, wherein a column diameter of the crystal column and the conductive column is increased from an end of the second surface toward an end of the first surface. The method of fabricating a semiconductor package according to claim 20, wherein the first circuit layer further comprises a trace. The method of fabricating a semiconductor package according to claim 20, wherein the second circuit layer comprises a trace.