TWI581375B - Electronic package and the manufacture thereof - Google Patents

Description

Electronic package and its manufacturing method

The invention relates to a package structure, in particular to an electronic package and a method of manufacturing the same.

Current semiconductor packaging technologies include wire bonding and Flip Chip semiconductor packaging technologies.

Referring to FIG. 1 , a conventional wire-wound semiconductor package 1 uses a lead frame 10 having a wafer holder 100 and a plurality of lead pins 101 formed around the wafer holder 100 to adhere the semiconductor wafer 11 by silver paste 12 . Connected to the wafer holder 100 and electrically connected to the semiconductor wafer 11 and the lead pins 101 by a plurality of bonding wires 13 , and then the semiconductor wafer 11 , the wafer holder 100 , the bonding wires 13 and the partial guides are covered by an encapsulant 14 Foot 101.

However, the silver paste 12 is formed in a Dispenser manner, so that when the semiconductor wafer 11 is bonded to the silver paste 12, the semiconductor wafer 11 is slightly slipped, and when the encapsulant 14 is formed, the semiconductor The wafer 11 is subjected to the impact force of the encapsulant 14, so that after the occurrence of the above situation, the semiconductor wafer 11 is offset (such as the semiconductor wafer 11 represented by the broken line shown in FIG. 1). The amount of shift often exceeds the line operation The range of the joint of the correctable bonding wire 13 (the operation of the bonding wire 13 from the semiconductor wafer 11 to the guiding pin 101 needs to be very precise), that is, the bonding wire 13 is not correctly mounted on the guiding pin 101. This causes the wire 13 to be easily broken, reduced in bonding force, or broken and peeled off, thereby affecting the yield of the electronic product to which the semiconductor package 1 is applied.

Therefore, how to avoid all kinds of defects in the prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides an electronic package comprising: an insulating layer; an electronic component disposed in the insulating layer; a plurality of stoppers disposed in the insulating layer and surrounding the The periphery of the electronic component; and the wiring structure are disposed in the insulating layer and located around the stoppers, such that the stoppers are located between the electronic component and the wiring structure.

In the foregoing electronic package, a heat sink disposed on the insulating layer and contacting the electronic component is further included.

The invention also provides a method for manufacturing an electronic package, comprising: providing a carrier board, the surface of the carrier board defining an adjacent wiring area and a crystallizing area; forming a line structure on the wiring area of the carrier board, and forming a plurality of Stopping block on the edge of the crystallographic region of the carrier plate; disposing an electronic component on the crystallographic region of the carrier plate; and forming an insulating layer on the carrier plate to cover the electronic component, the stop block and the line structure.

In the foregoing method, after the formation of the insulating layer, part or all of the carrier plate is removed.

In the foregoing electronic package and the method of manufacturing the same, the electronic component is flush (or Exposed) the surface of the insulating layer.

In the foregoing electronic package and method of manufacturing the same, the stopper is flush (or exposed) on the surface of the insulating layer.

In the above electronic package and method of manufacturing the same, the circuit structure has a plurality of conductive lines disposed on the carrier board (or around the stopper) and at least one conductive pillar disposed on the conductive line. For example, the conductive trace is flush (or exposed) to the surface of the insulating layer, and the conductive pillar is a copper pillar or a solder pillar, and the conductive pillar is exposed on the surface of the insulating layer.

In the foregoing electronic package and method of manufacturing the same, before the forming of the insulating layer, the electronic component is electrically connected to the wiring structure by a plurality of bonding wires.

In the foregoing electronic package and method of manufacturing the same, the circuit layer is formed on the insulating layer to electrically connect the circuit layer to the circuit structure.

In the foregoing electronic package and method of manufacturing the same, a plurality of conductive elements electrically connected to the line structure are formed on the insulating layer.

It can be seen from the above that the electronic package of the present invention and the manufacturing method thereof are mainly used to limit the moving range of the electronic component by the design of the stopper, so that when the electronic component is bonded to the carrier board and the insulating layer is formed The electronic component is not excessively offset, that is, the offset does not exceed the range of the joint of the calibratable bonding wire in the wire bonding operation, and the phenomenon that the welding wire is broken or dropped as in the prior art is avoided, thereby effectively improving the The yield of the electronic package; furthermore, the design of the stop block can improve the placement position of the electronic component and the accuracy of electrically connecting the electronic component, thereby avoiding the need for the conventional process to recognize the alignment one by one and affect the output, thereby realizing Large-scale production purpose; in addition, the invention can be completed at the same time Into the electronic component carrier manufacturing and electronic component packaging process, thereby reducing the overall packaging cost and production time.

1‧‧‧Semiconductor package

10‧‧‧ lead frame

100‧‧‧ Wafer holder

101‧‧‧ lead

11‧‧‧Semiconductor wafer

12‧‧‧Silver glue

13,23‧‧‧welding line

14‧‧‧Package colloid

2,2’,3,3’,3”‧‧‧electronic packages

20‧‧‧Loading board

200‧‧‧ Heat sink

21‧‧‧Electronic components

21a‧‧‧Action surface

21b‧‧‧Non-active surface

210‧‧‧electrode pads

22‧‧‧stop block

24‧‧‧Insulation

24a‧‧‧ first surface

24b‧‧‧second surface

25‧‧‧Line structure

25a‧‧‧Electrical circuit

250‧‧‧Line mat

251‧‧‧Electrical contact pads

252,350‧‧‧ conductive traces

26,26’‧‧‧ conductive column

27,37‧‧‧Conductive components

33‧‧‧Line layer

330,331‧‧‧conductive blind holes

A‧‧‧ crystal zone

B‧‧‧ wiring area

1 is a schematic cross-sectional view of a conventional semiconductor package; FIG. 1A is a partial top view of a conventional semiconductor package; and FIGS. 2A to 2E are first embodiment of a method for manufacturing an electronic package of the present invention; FIG. 2A' is a partial top view of FIG. 2A; FIG. 2D' is a partial top view of FIG. 2D; and FIG. 2E' is another embodiment of FIG. 2E FIG. 3A to FIG. 3C are cross-sectional views showing a second embodiment of the manufacturing method of the electronic package of the present invention; and FIGS. 3C' and 3C" are cross-sectional views of other different embodiments of FIG. 3C. schematic diagram.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. Technology disclosed by the invention The content can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2E are schematic cross-sectional views showing the first embodiment of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIGS. 2A and 2B, a carrier board 20 such as a metal plate is provided. The carrier board 20 defines an adjacent wiring area B and a crystal area A, and a wiring structure 25 is formed on the board 20 On the zone B, a plurality of stop blocks 22 are formed on the edge of the crystal zone A of the carrier plate 20.

In the present embodiment, the wiring region B surrounds the periphery of the crystal-shaped region A which is rectangular, and the stoppers 22 surround the edge of the crystal-crystalline region A as shown in Fig. 2A'.

Furthermore, the circuit structure 25 has a plurality of conductive lines 25a and a plurality of conductive posts 26 disposed on a portion of the conductive lines 25a. The conductive lines 25a have a plurality of wire pads 250, a plurality of electrical contact pads 251, and a plurality of electrical properties. The wire pads 250 are connected to the conductive traces 252 of the electrical contact pads 251 (as shown in FIG. 2A'), and each of the conductive pillars 26 is disposed on each of the electrical contact pads 251.

Moreover, by the electroplating patterning process, the stoppers 22 can be fabricated together with the conductive lines 25a, and then the conductive pillars 26 are formed by electroplating, and the conductive pillars 26 are, for example, metal pillars of a copper cylinder.

As shown in FIG. 2C, an electronic component 21 is disposed on the carrier 20 The crystal block A is placed such that the stoppers 22 surround the periphery of the electronic component 21. Then, the wire bonding process is performed. The electronic component 21 is electrically connected to the wire bonding pads 250 by a plurality of bonding wires 23, so that the electronic component 21 is electrically connected to the conductive pillars 26 by the conductive wires 25a.

In this embodiment, the electronic component 21 is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is a semiconductor wafer having an opposite active surface 21a and a non-active surface 21b. The active surface 21a has a plurality of electrode pads 210, and the bonding wire 23 is electrically connected to the bonding pad 250 and the electrode pad. 210, and the electronic component 21 is bonded to the crystallographic region A of the carrier 20 by a non-active surface 21b thereof.

As shown in FIG. 2D, an insulating layer 24 is formed on the carrier 20 to cover the electronic component 21, the stopper 22, the bonding wire 23 and the wiring structure 25, wherein the insulating layer 24 has a bonding The first surface 24a on the carrier 20 and the second surface 24b opposite the first surface 24a.

In the present embodiment, the insulating layer 24 is an encapsulant such as an epoxy resin, which may be formed on the carrier 20 by lamination or molding.

Furthermore, the end surface of the conductive pillar 26 is flushed to the second surface 24b of the insulating layer 24 by a flattening process such as a grinding method, so that the end surface of the conductive pillar 26 is exposed on the second surface of the insulating layer 24. 24b. It should be understood that a plurality of openings may be formed on the second surface 24b of the insulating layer 24 to expose the end faces of the conductive posts 26 to the openings.

Moreover, the first surface 24a of the insulating layer 24 is flush with the non-active surface 21b of the electronic component 21, the surface of the stopper 22, and the surface of the conductive trace 25a.

As shown in FIG. 2E, the entire carrier 20 is removed by etching to expose the first surface 24a of the insulating layer 24, the non-active surface 21b of the electronic component 21, the stopper 22, the bonding pad 250, and the electrical contact pad. 251.

In the present embodiment, a plurality of conductive elements 27, such as solder balls, are formed on the second surface 24b of the insulating layer 24. Specifically, the conductive elements 27 are coupled to the end faces of the conductive pillars 26 to electrically connect the electrical contact pads 251.

Furthermore, in another embodiment, as shown in FIG. 2E', only a portion of the carrier 20 is etched away to retain a portion of the carrier 20 located on the non-active surface 21b of the electronic component 21 (optional) The carrier board 20 is disposed on the non-active surface 21b of the electronic component 21 and the stop block 22, that is, the carrier board 20) is retained on the crystallized area A of the carrier board 20, As the heat sink 200.

Further, as shown in Fig. 2E', in the process of Fig. 2B, the conductive post 26' may be a solder pillar.

3A to 3C are cross-sectional views showing a second embodiment of the manufacturing method of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the electrical connection manner between the electronic component and the circuit structure, and the other processes are substantially the same. Therefore, the differences will be described in detail below, and the same points will not be described again.

As shown in FIG. 3A, the process of FIG. 2B is continued, but the wire bonding operation is not performed, and the insulating layer is directly formed after the electronic component 21 is disposed. twenty four.

In the present embodiment, the conductive line 25a has a plurality of conductive traces 350 electrically connected to the electrical contact pads 251, and no wire pad is formed, and the end faces of the conductive posts 26 of the line structure 25 are exposed to the insulation. Layer 24.

As shown in FIG. 3B, a wiring layer 33 is formed on the second surface 24b of the insulating layer 24, and the wiring layer 33 is electrically connected to the electronic component 21 and the conductive pillars 26 of the wiring structure 25.

In this embodiment, the circuit layer 33 has a plurality of conductive vias 330 extending in the insulating layer 24 to electrically connect the electrode pads 210 of the electronic component 21.

As shown in FIG. 3C, the entire carrier 20 is removed by etching to expose the first surface 24a of the insulating layer 24, the non-active surface 21b of the electronic component 21, the stop block 22, the conductive traces 350, and electrical contacts. Pad 251.

In this embodiment, a plurality of conductive elements such as solder balls are formed on the first surface 24a of the insulating layer 24. Specifically, the conductive elements 37 are coupled to the exposed surfaces of the electrical contact pads 251 to electrically connect the conductive pillars 26.

Furthermore, as shown in FIG. 3C′, if the second surface 24b of the insulating layer 24 is higher than the end surface of the conductive pillar 26 (ie, the insulating layer 24 covers the conductive pillar 26), the process of FIG. 3B is performed. The circuit layer 33 can have a plurality of conductive vias 331 extending in the insulating layer 24 to electrically connect the conductive pillars 26.

Alternatively, as shown in FIG. 3C", if the second surface 24b of the insulating layer 24 is flush with the active surface 21a of the electronic component 21 and the end of the conductive pillar 26 In the process of FIG. 3B, the circuit layer 33 can be directly electrically connected to the electrode pad 210 and the conductive pillar 26 without forming a conductive blind hole.

In addition, in the electronic package 3, 3', 3", it can be understood that a heat dissipating member (not shown) can be attached to the non-active surface 21b of the electronic component 21.

The method of the present invention is to limit the position of the electronic component 21 by the design of the stopper 22, as shown in FIG. 2D', so that the electronic component 21 is bonded to the carrier 20 and the insulating layer 24 is formed. When the electronic component 21 is blocked by the stopper 22 without excessive offset, that is, the offset does not exceed the range of the joint of the correctable bonding wire 23 in the wire bonding operation, or exceeds the circuit layer 33. The positioning range avoids the phenomenon that the bonding wire 23 is broken or dropped and the circuit layer 33 does not contact the electrode pad 210, thereby effectively improving the yield of the electronic package 2, 2', 3, 3', 3".

The present invention provides an electronic package 2, 2', 3, 3', 3", comprising: an insulating layer 24, an electronic component 21 embedded in the insulating layer 24, a plurality of stops 22, and a line Structure 25.

The stopper 22 is embedded in the insulating layer 24 and surrounds the electronic component 21.

The circuit structure 25 is disposed in the insulating layer 24 and located around the stoppers 22 such that the stoppers 22 are located between the electronic component 21 and the wiring structure 25.

In an embodiment, the non-active surface 21b of the electronic component 21 is exposed on the first surface 24a of the insulating layer 24, and the active surface 21a of the electronic component 21 of the electronic package 3" is exposed to the insulating layer 24. The second surface 24b.

In the electronic package 2, 2', 3, 3', 3" of an embodiment, the stopper 22 is exposed on the first surface 24a of the insulating layer 24.

In one embodiment, the circuit structure 25 has a plurality of conductive lines 25a disposed around the stop blocks 22 and a plurality of conductive posts 26, 26' disposed on the conductive lines 25a. For example, the conductive trace 25a is exposed on the first surface 24a of the insulating layer 24, and the conductive pillars 26, 26' are copper pillars or solder pillars exposed to the second surface 24b of the insulating layer 24.

In the electronic package 2, 2' of an embodiment, the electronic component 21 is electrically connected to the wiring structure 25 by a plurality of bonding wires 23.

In one embodiment, the electronic package 3, 3', 3" includes a circuit layer 33 formed on the second surface 24b of the insulating layer 24, and electrically connected to the electronic component 21 and the circuit structure 25. .

In one embodiment, the electronic package 2' includes a heat sink 200 disposed on the first surface 24a of the insulating layer 24 and contacting the electronic component 21.

In one embodiment, the electronic package 3, 3', 3" includes a plurality of conductive elements 37 formed on the first surface 24a of the insulating layer 24. Alternatively, the electronic package 2, 2' includes the formation A plurality of conductive elements 27 on the second surface 24b of the insulating layer 24.

In summary, the package substrate of the present invention and the method for manufacturing the same are designed by the stopper, so that when the insulating layer is formed, the stopper blocks the range of movement of the electronic component, so that the electronic component does not Excessively offset, so that the missing as described in the prior art does not occur; furthermore, the design of the stop block can improve the placement of the electronic component and the electrical connection of the electronic component. To avoid the conventional process, it is necessary to identify the alignment and affect the output one by one, so as to achieve the large-scale mass production; in addition, the invention can simultaneously complete the electronic component carrier manufacturing and electronic component packaging process, thereby reducing the overall packaging cost and production time. .

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Electronic package

21‧‧‧Electronic components

21b‧‧‧Non-active surface

22‧‧‧stop block

23‧‧‧welding line

24‧‧‧Insulation

24a‧‧‧ first surface

24b‧‧‧second surface

25‧‧‧Line structure

25a‧‧‧Electrical circuit

250‧‧‧Line mat

251‧‧‧Electrical contact pads

26‧‧‧conductive column

27‧‧‧Conducting components

Claims (21)

An electronic package includes: an insulating layer; an electronic component is disposed in the insulating layer; a plurality of stoppers are formed in the insulating layer and surround the electronic component, and the stopper is exposed a surface of the insulating layer; and a wiring structure formed in the insulating layer and located around the stoppers such that the stoppers are located between the electronic component and the wiring structure. The electronic package of claim 1, wherein the electronic component is exposed on a surface of the insulating layer. The electronic package of claim 1, wherein the circuit structure has a plurality of conductive lines disposed around the stop block and at least one conductive post disposed on the conductive line. The electronic package of claim 3, wherein the conductive circuit is exposed on a surface of the insulating layer. The electronic package of claim 3, wherein the conductive pillar is a copper cylinder or a solder cylinder. The electronic package of claim 3, wherein the conductive pillar is exposed on a surface of the insulating layer. The electronic package of claim 1, wherein the electronic component is electrically connected to the circuit structure by a plurality of bonding wires. The electronic package of claim 1, further comprising forming on the insulating layer and electrically connecting the electronic component and the circuit structure Line layer. The electronic package of claim 1, further comprising a heat sink disposed on the insulating layer and contacting the electronic component. The electronic package of claim 1, further comprising a plurality of conductive elements formed on the insulating layer and electrically connected to the line structure. The method for manufacturing an electronic package includes: providing a carrier board, wherein the surface of the carrier board defines an adjacent wiring area and a crystallizing area; forming a line structure on the wiring area of the carrier board, and forming a plurality of stop blocks And affixing the electronic component on the edge of the carrier plate; and forming an insulating layer on the carrier plate to cover the electronic component, the stopper and the circuit structure. The method of manufacturing an electronic package according to claim 11, wherein the surface of the electronic component is flush with the surface of the insulating layer. The method of manufacturing an electronic package according to claim 11, wherein the surface of the stopper is flush with the surface of the insulating layer. The method of manufacturing an electronic package according to claim 11, wherein the circuit structure has a plurality of conductive lines disposed on the carrier board and at least one conductive post disposed on the conductive line. The method of manufacturing an electronic package according to claim 14, wherein the surface of the conductive line is flush with the surface of the insulating layer. The method of manufacturing an electronic package according to claim 14, wherein the conductive pillar is a copper pillar or a solder cylinder. The method of manufacturing an electronic package according to claim 14, wherein the conductive pillar is exposed on a surface of the insulating layer. The method for manufacturing an electronic package according to claim 11, wherein the electronic component is electrically connected to the circuit structure by a plurality of bonding wires before forming the insulating layer. The method of manufacturing an electronic package according to claim 11, further comprising forming a circuit layer on the insulating layer to electrically connect the circuit layer to the circuit component. The method for manufacturing an electronic package according to claim 11, further comprising removing part or all of the carrier after forming the insulating layer. The method for manufacturing an electronic package according to claim 11, further comprising forming on the insulating layer a plurality of conductive elements electrically connected to the circuit structure.