TW201810545A - Electronic package and the manufacture thereof - Google Patents

Abstract

Provided is an electronic package, comprising an insulating layer, an electronic element embedded in the insulating layer, a plurality of stopping blocks surrounding the electronic element, and a circuit structure disposed at the periphery of the stopping blocks, wherein the stopping blocks are disposed at a position between the electronic element and the circuit structure to thereby restrict the movement of the electronic element. The invention further provides a method for manufacturing the electronic package as described above.

Description

Electronic package and manufacturing method thereof

The invention relates to a packaging structure, in particular to an electronic package and a manufacturing method thereof.

Current semiconductor packaging technologies include wire bonding and flip chip semiconductor packaging technologies.

Referring to FIG. 1, the conventional wire-bonded semiconductor package 1 uses a lead frame 10 having a wafer base 100 and a plurality of guide pins 101 formed around the wafer base 100 to adhere the semiconductor wafer 11 to the silver glue 12. Connected to the wafer holder 100 and electrically connecting the semiconductor wafer 11 and the guide pins 101 with a plurality of bonding wires 13, and then encapsulating the semiconductor wafer 11, the wafer holder 100, the bonding wires 13 and the partial guides through a packaging gel 14 Feet 101.

However, the silver glue 12 is formed by a Dispenser method. Therefore, when the semiconductor wafer 11 is bonded to the silver glue 12, the semiconductor wafer 11 may slip slightly, and when the packaging glue 14 is formed, the semiconductor The wafer 11 is subject to the impact force of the encapsulating gel 14, so after the above situation occurs, the semiconductor wafer 11 will be offset (such as the semiconductor wafer 11 represented by the dashed line shown in FIG. 1), and this bias The amount of shift often exceeds the line operation The range of contacts that can be corrected for the bonding wire 13 (the operation of bonding the bonding wire 13 from the semiconductor wafer 11 to the guide pin 101 needs to be very accurate), that is, the bonding wire 13 cannot be correctly set on the guide pin 101 This causes the bonding wire 13 to be easily broken, reduced in bonding force, or broken and peeled off, and then affects the yield of electronic products to which the semiconductor package 1 is applied.

Therefore, how to avoid all the shortcomings in the conventional technology has become an urgent problem to be solved.

In view of the various shortcomings of the above-mentioned conventional technologies, the present invention provides an electronic package including: an insulating layer; an electronic component provided in the insulating layer; a plurality of stoppers provided in the insulating layer and surrounding the The periphery of the electronic component and the circuit structure are arranged in the insulation layer and located around the stoppers, so that the stoppers are located between the electronic component and the circuit structure.

The aforementioned electronic package further includes a heat sink disposed on the insulating layer and contacting the electronic component.

The invention also provides a method for manufacturing an electronic package, comprising: providing a carrier board, the carrier board surface defining adjacent wiring areas and crystal placement areas; forming a circuit structure on the wiring area of the carrier board, and forming a plurality of The stopper is located on the edge of the crystallizing area of the carrier board; the electronic component is disposed on the crystallizing area of the carrier board; and an insulating layer is formed on the carrier board to cover the electronic component, the stopper and the circuit. structure.

In the foregoing manufacturing method, after forming the insulating layer, removing part or all of the carrier board.

In the aforementioned electronic package and its manufacturing method, the electronic component is flush (or Exposed) the surface of the insulating layer.

In the aforementioned electronic package and its manufacturing method, the stopper is flush (or exposed) on the surface of the insulating layer.

In the aforementioned electronic package and its manufacturing method, the circuit structure has a plurality of conductive circuits arranged on the carrier board (or around the stop block) and at least one conductive post arranged on the conductive circuit. For example, the conductive line is flush (or exposed) on the surface of the insulating layer, and the conductive pillar is a copper pillar or a solder pillar, and the conductive pillar is exposed on the surface of the insulating layer.

In the aforementioned electronic package and its manufacturing method, before the formation of the insulating layer, the electronic component is electrically connected to the circuit structure through a plurality of bonding wires.

In the foregoing electronic package and manufacturing method, the method further includes forming a circuit layer on the insulating layer, so that the circuit layer electrically connects the electronic component and the circuit structure.

In the foregoing electronic package and manufacturing method, the method further includes forming a plurality of conductive elements electrically connected to the circuit structure on the insulating layer.

As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly rely on the design of the stopper to limit the movement range of the electronic component, so when the electronic component is bonded to the carrier board and the insulation layer is formed , The electronic component will not be excessively shifted, that is, the amount of shift will not exceed the range of the correctable welding wire contact in the wire bonding operation, to avoid the occurrence of phenomena such as breakage or peeling of the welding wire of the conventional technology, thereby effectively improving the Yield of the electronic package; further, the design of the stopper can improve the placement of the electronic component and the accuracy of the electrical connection to the electronic component, avoiding the need to identify the alignment one by one in the conventional manufacturing process and affect the output, thereby achieving The purpose of large-scale production; in addition, the present invention can be completed at the same time It becomes an electronic component carrier manufacturing and electronic component packaging process, thereby reducing the overall packaging cost and production time.

1‧‧‧ semiconductor package

10‧‧‧ lead frame

100‧‧‧ Chip holder

101‧‧‧Guide

11‧‧‧Semiconductor wafer

12‧‧‧Silver glue

13,23‧‧‧Welding wire

14‧‧‧ encapsulated colloid

2,2 ’, 3,3’, 3 ”‧‧‧electronic package

20‧‧‧carrying plate

200‧‧‧ heat sink

21‧‧‧Electronic components

21a‧‧‧active surface

21b‧‧‧ non-active surface

210‧‧‧ electrode pad

22‧‧‧ Stop

24‧‧‧ Insulation

24a‧‧‧first surface

24b‧‧‧Second surface

25‧‧‧Line Structure

25a‧‧‧ conductive line

250‧‧‧Wired pad

251‧‧‧electric contact pad

252,350‧‧‧ conductive traces

26,26’‧‧‧ conductive post

27, 37‧‧‧ conductive elements

33‧‧‧Line layer

330,331‧‧‧Conductive blind hole

A‧‧‧Set crystal area

B‧‧‧ wiring area

Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package; Fig. 1 'is a schematic top-view schematic view of a conventional semiconductor package; Figs. 2A to 2E are the first implementation of the manufacturing method of the electronic package of the present invention; Figure 2A 'is a partial top view of Figure 2A; Figure 2D' is a partial top view of Figure 2D; Figure 2E 'is another embodiment of Figure 2E Figures 3A to 3C are schematic sectional views of the second embodiment of the method for manufacturing an electronic package of the present invention; and Figures 3C 'and 3C "are sectional views of other different embodiments of Figure 3C schematic diagram.

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The limited conditions are not technically significant. Any modification of the structure, change of the proportional relationship, or adjustment of the size should still fall within the scope of this invention without affecting the effects and goals that can be achieved by the present invention. Disclosed Technology The content must be within the scope. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not intended to limit the scope of the present invention. Changes or adjustments in their relative relationships shall be considered to be the scope of the present invention without substantial changes in the technical content.

Figures 2A to 2E are schematic cross-sectional views of the first embodiment of the manufacturing method of the electronic package 2 of the present invention.

As shown in Figures 2A and 2B, a carrier plate 20 is provided, such as a metal plate. The carrier plate 20 defines adjacent wiring areas B and crystal placement areas A, and forms a wiring structure 25 on the wiring of the carrier plate 20. On the area B, a plurality of stop blocks 22 are formed on the edge of the crystal plate area A of the carrier plate 20.

In this embodiment, the wiring area B surrounds the periphery of the crystal placement area A in a rectangular shape, and the stoppers 22 surround the edges of the crystal placement area A, as shown in FIG. 2A '.

Furthermore, the circuit structure 25 has a plurality of conductive lines 25a and a plurality of conductive posts 26 provided on part of the conductive lines 25a. Among them, the conductive line 25a has a plurality of wiring pads 250, a plurality of electrical contact pads 251, and a plurality of electrical properties. The conductive traces 252 (as shown in FIG. 2A ′) connecting the wire bonding pad 250 and the electrical contact pad 251, and each of the conductive posts 26 are correspondingly disposed on each of the electrical contact pads 251.

In addition, through the electroplating patterning process, the stoppers 22 and the conductive lines 25a can be fabricated together, and then the conductive pillar 26 is fabricated by electroplating. The conductive pillar 26 is a metal pillar such as a copper pillar.

As shown in FIG. 2C, an electronic component 21 is disposed on the carrier plate 20. It is placed on the crystal region A so that the stop blocks 22 surround the periphery of the electronic component 21. Next, a wire bonding process is performed. The electronic component 21 is electrically connected to the wire bonding pads 250 through a plurality of bonding wires 23, so that the electronic component 21 is electrically connected to the conductive pillar 26 through the conductive line 25a.

In this embodiment, the electronic component 21 is an active component, a passive component, or a combination of both, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is a semiconductor wafer, which has opposite active surfaces 21a and non-active surfaces 21b, the active surface 21a has a plurality of electrode pads 210, and the bonding wires 23 are electrically connected to the wire bonding pads 250 and the electrode pads. 210, and the electronic component 21 is bonded to the crystal-receiving area A of the carrier plate 20 by using a non-active surface 21b by an adhesive material (not shown).

As shown in FIG. 2D, an insulating layer 24 is formed on the carrier board 20 to cover the electronic component 21, the stopper 22, the bonding wire 23, and the circuit structure 25, wherein the insulating layer 24 is bonded to the A first surface 24a on the carrier plate 20 and a second surface 24b opposite to the first surface 24a.

In this embodiment, the insulating layer 24 is an encapsulating gel such as epoxy resin, which can be formed on the carrier plate 20 by lamination or molding.

Furthermore, the end surface of the conductive pillar 26 is made flush with the second surface 24b of the insulating layer 24 by a leveling process such as grinding, so that the end surface of the conductive pillar 26 is exposed on the second surface of the insulating layer 24 24b. It should be understood that a plurality of openings may be formed on the second surface 24b of the insulating layer 24 so that the end surfaces of the conductive pillars 26 are exposed to the openings.

In addition, the first surface 24a of the insulating layer 24 is flush with the non-active surface 21b of the electronic component 21, the surface of the stopper 22, and the surface of the conductive circuit 25a.

As shown in FIG. 2E, all the carrier plates 20 are removed by etching to expose the first surface 24a of the insulating layer 24, the non-active surface 21b of the electronic component 21, the stopper 22, the wire bonding pad 250, and the electrical contact pad. 251.

In this embodiment, a plurality of conductive elements 27 such as solder balls are formed on the second surface 24 b of the insulating layer 24. Specifically, the conductive elements 27 are coupled to the end surfaces of the conductive pillars 26 to electrically connect the electrical contact pads 251.

Furthermore, in another embodiment, as shown in FIG. 2E ′, only a part of the carrier board 20 is removed by etching to retain a part of the carrier board 20 on the non-active surface 21 b of the electronic component 21 (optional) To retain part of the carrier plate 20 on the non-active surface 21b of the electronic component 21 and the stopper block 22, that is, to retain part of the carrier plate 20 on the crystal placement area A of the carrier plate 20) As a heat sink 200.

In addition, as shown in FIG. 2E ', in the process of FIG. 2B, the conductive pillar 26' may be a solder pillar.

3A to 3C are schematic sectional views of the second embodiment of the manufacturing method of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the electrical connection method of the electronic components and the circuit structure, and other processes are substantially the same, so the detailed descriptions below are different, and the same points are not described again.

As shown in FIG. 3A, the process is continued from FIG. 2B, but no wire bonding is performed. After the electronic component 21 is provided, the insulation layer is directly formed. twenty four.

In this embodiment, the conductive line 25a has a plurality of conductive traces 350 electrically connected to the electrical contact pad 251 without a wire bonding pad, and the end of the conductive post 26 of the line structure 25 is exposed to the insulation. Layer 24.

As shown in FIG. 3B, a circuit layer 33 is formed on the second surface 24 b of the insulation layer 24, and the circuit layer 33 is electrically connected to the electronic component 21 and the conductive pillar 26 of the circuit structure 25.

In this embodiment, the circuit layer 33 has a plurality of conductive blind holes 330 extending in the insulating layer 24 to electrically connect the electrode pads 210 of the electronic component 21.

As shown in FIG. 3C, all the carrier plates 20 are removed by etching to expose the first surface 24a of the insulating layer 24, the non-active surface 21b of the electronic component 21, the stopper 22, the conductive trace 350, and electrical contact. Pad 251.

In this embodiment, a plurality of conductive elements 37 such as solder balls are formed on the first surface 24 a of the insulating layer 24. Specifically, the conductive elements 37 are coupled to the exposed surfaces of the electrical contact pads 251 to electrically connect the conductive pillars 26.

Furthermore, as shown in FIG. 3C ′, if the second surface 24 b of the insulating layer 24 is higher than the end surface of the conductive pillar 26 (that is, the insulating layer 24 covers the conductive pillar 26), then the process in FIG. 3B The circuit layer 33 may have another conductive blind hole 331 extending in the insulating layer 24 to electrically connect the conductive pillar 26.

Alternatively, as shown in FIG. 3C ”, if the second surface 24b of the insulating layer 24 is flush with the active surface 21a of the electronic component 21 and the end of the conductive pillar 26 In the process of FIG. 3B, the circuit layer 33 can directly and electrically connect the electrode pad 210 and the conductive pillar 26 without forming a conductive blind hole.

In addition, in the electronic package 3, 3 ', 3 ", it should be understood that a non-active surface 21b of the electronic component 21 can be connected with a heat sink (not shown).

In the manufacturing method of the present invention, the position of the electronic component 21 is restricted by the design of the stopper 22, as shown in FIG. 2D ′. Therefore, the electronic component 21 is adhered to the carrier plate 20 and the insulating layer 24 is formed. At this time, the electronic component 21 will be blocked by the stopper 22 without being excessively shifted, that is, the shift amount will not exceed the range of the contact of the correctable bonding wire 23 during the wire bonding operation, or exceed the range of the wiring layer 33. The positioning range avoids the occurrence of breakage or peeling of the bonding wire 23 and the non-contact of the circuit layer 33 with the electrode pad 210, thereby effectively improving the yield of the electronic package 2,2 ', 3,3', 3 ".

The present invention provides an electronic package 2,2 ', 3,3', 3 ", which includes: an insulating layer 24, an electronic component 21 embedded in the insulating layer 24, a plurality of stoppers 22, and a circuit. Structure 25.

The stopper 22 is embedded in the insulation layer 24 and surrounds the electronic component 21.

The circuit structure 25 is disposed in the insulation layer 24 and located around the stop blocks 22, so that the stop blocks 22 are located between the electronic component 21 and the circuit structure 25.

In one embodiment, the non-active surface 21b of the electronic component 21 is exposed from the first surface 24a of the insulating layer 24, and the active surface 21a of the electronic component 21 of the electronic package 3 "is exposed from the insulating layer 24. Of the second surface 24b.

In the electronic package 2, 2 ′, 3, 3 ′, 3 ″ of an embodiment, the stopper 22 is exposed on the first surface 24 a of the insulating layer 24.

In one embodiment, the circuit structure 25 has a plurality of conductive lines 25a arranged around the stoppers 22 and a plurality of conductive posts 26, 26 'arranged on the conductive lines 25a. For example, the conductive line 25a is exposed on the first surface 24a of the insulating layer 24, and the conductive pillars 26, 26 'are copper pillars or solder pillars, which are exposed on the second surface 24b of the insulating layer 24.

In the electronic package 2, 2 ′ of an embodiment, the electronic component 21 is electrically connected to the circuit structure 25 through a plurality of bonding wires 23.

In one embodiment, the electronic package 3, 3 ', 3 "includes a circuit layer 33 formed on the second surface 24b of the insulating layer 24, and is electrically connected to the electronic component 21 and the circuit structure 25. .

In one embodiment, the electronic package 2 'includes a heat sink 200 disposed on the first surface 24a of the insulating layer 24 and contacting the electronic component 21.

In one embodiment, the electronic package 3, 3 ', 3 "includes a plurality of conductive elements 37 formed on the first surface 24a of the insulating layer 24. Alternatively, the electronic package 2, 2' includes a formation A plurality of conductive elements 27 on the second surface 24 b of the insulating layer 24.

In summary, the package substrate and the manufacturing method thereof of the present invention are designed by the stopper, so that when the insulating layer is formed, the stopper will limit the moving range of the electronic component, so that the electronic component does not It will be excessively shifted, so that it will not be missing as described in the conventional technology; further, the design of the stopper can improve the placement of the electronic component and the precision of the electrical connection to the electronic component. It can avoid the need to recognize the alignment one by one in the conventional manufacturing process to affect the output, thereby achieving the goal of mass production. In addition, the invention can simultaneously complete the manufacturing process of electronic component carriers and the packaging process of electronic components, thereby reducing the overall packaging cost and production time. .

The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2‧‧‧electronic package

21‧‧‧Electronic components

21b‧‧‧ non-active surface

22‧‧‧ Stop

23‧‧‧ Welding Wire

24‧‧‧ Insulation

24a‧‧‧first surface

24b‧‧‧Second surface

25‧‧‧Line Structure

25a‧‧‧ conductive line

250‧‧‧Wired pad

251‧‧‧electric contact pad

26‧‧‧ conductive post

27‧‧‧ conductive element

Claims (22)

An electronic package includes: an insulating layer; an electronic component provided in the insulating layer; a plurality of stoppers formed in the insulating layer and surrounding the electronic component; and a circuit structure formed in the insulation The layer is located in the layer and around the stop blocks, so that the stop blocks are located between the electronic component and the circuit structure. The electronic package according to item 1 of the scope of patent application, wherein the electronic component is exposed on the surface of the insulating layer. The electronic package according to item 1 of the scope of patent application, wherein the stopper is exposed on the surface of the insulating layer. The electronic package according to item 1 of the scope of patent application, wherein the circuit structure has a plurality of conductive lines arranged around the stopper and at least one conductive post arranged on the conductive lines. The electronic package according to item 4 of the scope of patent application, wherein the conductive circuit is exposed on the surface of the insulating layer. The electronic package according to item 4 of the scope of patent application, wherein the conductive pillar is a copper pillar or a solder pillar. The electronic package according to item 4 of the scope of patent application, wherein the conductive pillar is exposed on the surface of the insulating layer. The electronic package according to item 1 of the scope of patent application, wherein the electronic component is electrically connected to the circuit structure by a plurality of bonding wires. The electronic package described in item 1 of the scope of the patent application, includes a circuit layer formed on the insulation layer and electrically connecting the electronic component and the circuit structure. The electronic package described in item 1 of the scope of the patent application, further includes a heat sink provided on the insulation layer and contacting the electronic component. The electronic package described in item 1 of the scope of the patent application includes a plurality of conductive elements formed on the insulating layer and electrically connected to the circuit structure. An electronic package manufacturing method includes: providing a carrier board, wherein the carrier board surface defines adjacent wiring areas and crystal placement areas; forming a circuit structure on the wiring area of the carrier board, and forming a plurality of stop blocks On the edge of the crystal-receiving region of the carrier board; placing electronic components on the crystal-receiving region of the carrier board; and forming an insulating layer on the carrier board to cover the electronic element, the stopper and the circuit structure. According to the manufacturing method of the electronic package described in item 12 of the patent application scope, wherein the surface of the electronic component is flush with the surface of the insulating layer. According to the manufacturing method of the electronic package described in item 12 of the patent application scope, wherein the surface of the stopper is flush with the surface of the insulating layer. According to the manufacturing method of the electronic package described in item 12 of the patent application scope, wherein the circuit structure has a plurality of conductive lines arranged on the carrier board and at least one conductive post arranged on the conductive lines. According to the manufacturing method of the electronic package described in item 15 of the scope of patent application, wherein the surface of the conductive circuit is flush with the surface of the insulating layer. According to the method for manufacturing an electronic package described in item 15 of the scope of the patent application, wherein the conductive pillar is a copper pillar or a solder pillar. According to the manufacturing method of the electronic package described in item 15 of the scope of the patent application, wherein the conductive pillar is exposed on the surface of the insulating layer. According to the manufacturing method of the electronic package described in item 12 of the scope of the patent application, before the formation of the insulating layer, the electronic component is electrically connected to the circuit structure through a plurality of bonding wires. According to the manufacturing method of the electronic package described in item 12 of the scope of the patent application, the method further includes forming a circuit layer on the insulating layer, so that the circuit layer electrically connects the electronic component and the circuit structure. According to the manufacturing method of the electronic package described in item 12 of the scope of the patent application, the method further includes removing part or all of the carrier board after forming the insulating layer. According to the manufacturing method of the electronic package described in item 12 of the scope of patent application, the method further includes forming a plurality of conductive elements electrically connected to the circuit structure on the insulating layer.