TWI447872B - Package structure, substrate structure and a method of forming same - Google Patents

Description

Package structure, substrate structure and preparation method thereof

The invention relates to a package structure, a substrate structure and a preparation method thereof, in particular to a package structure without a core layer, a substrate structure and a preparation method thereof.

In order to meet the trend of the current thin and light electronic products, and to effectively reduce the size of the semiconductor package structure, the industry has developed a ball grid array semiconductor package structure, characterized in that the substrate used is provided with at least one through slot. The semiconductor wafer is attached to the substrate in such a manner as to cover the slot, and the semiconductor wafer is electrically connected to the substrate by a plurality of bonding wires passing through the slot. The package structure can be applied to a central-pad type semiconductor wafer, such as a dynamic random access memory (DRAM), and can shorten the length of the bonding wire and increase the electrical quality. And can reduce the overall thickness of the package structure.

Please refer to FIGS. 1A to 1I for a cross-sectional view of a conventional package structure and a method of manufacturing the same.

As shown in FIG. 1A, a core board 10 is provided, and a copper layer 11 is formed on one surface of the core board 10.

As shown in FIG. 1B, a resist layer 12 is formed on the copper layer 11, and the resist layer 12 has a plurality of barrier opening regions 120 exposing the copper layer 11.

As shown in FIG. 1C, the copper layer 11 in the resist opening region 120 is removed to define a copper line 111.

The resist layer 12 is removed as shown in FIG. 1D.

As shown in FIG. 1E, the solder resist layer 13 is covered on the core board 10 and the copper line 111.

As shown in FIG. 1F, a plurality of first openings 131 and second openings 132 of the exposed portion of the copper line 111 are formed in the solder resist layer 13, wherein the first opening 131 and the second opening 132 are The copper lines 111 are respectively used as a finger pad 111a and a ball pad 111b.

As shown in Fig. 1G, a metal layer 14 of, for example, nickel/palladium/gold is formed on the finger pad 111a and the solder ball pad 111b.

As shown in FIG. 1H, a slot 100 penetrating the core plate 10 and the solder resist layer 13 is formed by punching.

As shown in FIG. 1I, a semiconductor wafer 15 covering the slot 100 is attached to the other surface of the core board 10. The pad 151 of the semiconductor wafer 15 is located in the slot 100 and is soldered by a plurality of solders. The wire 16 is electrically connected to the pad 151 and the finger pad 111a, and then the encapsulant 17 covering the slot 100, the finger pad 111a, the pad 151 and the bonding wire 16 is formed, and is connected to the solder ball pad 111b. Solder ball 18.

However, the manufacturing method of the prior art, such as U.S. Patent Nos. 7,786,591 and 6,551,361, is relatively expensive to manufacture, and the trace pitch cannot be less than 70 micrometers (μm), and cannot meet the trend of light and thin package structures.

Therefore, how to avoid various problems in the above-mentioned prior art, and to make the line pitch of the package structure smaller, thereby reducing the size of the overall package structure and reducing the manufacturing cost, has become a problem to be solved at present.

In view of the above-mentioned shortcomings of the prior art, the present invention provides a package structure, comprising: a semiconductor wafer having opposite active and non-active surfaces, and the active surface has a plurality of connection pads; the first package colloid is set On the active surface, and having opposite first and second surfaces and a slot extending through the first surface and the second surface and exposing the connection pad, the first surface is connected to the active surface; On the second surface of the first encapsulant, and having a plurality of first pads and second pads exposed on the second surface; the first conductive element is electrically connected to the first pad and the connection pad; And a second encapsulant covering the first conductive element, the connection pad and the first pad.

The present invention provides a substrate structure, comprising: a substrate having a plurality of substrate units, each of the substrate units comprising: an encapsulant having a first surface and a second surface opposite to each other and a slot extending through the first surface and the second surface And a circuit formed on the second surface of the encapsulant and having a plurality of first pads and second pads exposed on the second surface; and a frame disposed around the periphery of the substrate.

The invention provides a method for fabricating a substrate structure, comprising: providing a patterned metal layer having a first metal block and a line; forming a second metal block on the first metal block; forming the pattern Forming a metal layer and the second metal block and exposing the encapsulant of the second metal block; and removing the first metal block and the second metal block to define a slot.

The present invention provides a method for fabricating a package structure, comprising: providing a substrate structure, the substrate structure comprising: a first encapsulant having opposite first and second surfaces and through the first surface and the second surface a slot, and a circuit formed on the second surface of the first encapsulant and having a plurality of first pads and second pads exposed on the second surface; having opposite active and inactive surfaces The semiconductor wafer is disposed on the first surface of the first encapsulant with its active surface, and the active surface has a plurality of connection pads corresponding to the exposed holes; forming an electrical connection between the first pad and the connection pad a first conductive element; and a second encapsulant covering the first conductive element, the connection pad and the first pad.

The present invention provides a method for fabricating another package structure, comprising: providing a substrate and a frame disposed around a periphery of the substrate, the substrate having a plurality of substrate units, each of the substrate units comprising: a first encapsulant having a relative a first surface and a second surface and a slot extending through the first surface and the second surface; and a line formed on the second surface of the first encapsulant and having a plurality first exposed to the second surface a solder pad and a second pad; a semiconductor wafer having a plurality of semiconductor wafers on the first surface of the first encapsulant, each of the semiconductor wafers having an opposite active surface and a non-active surface, and each of the active surfaces Forming a plurality of connection pads corresponding to the respective holes; forming a first conductive element electrically connecting the connection pad and the first pad; and forming a first layer covering the first conductive element, the connection pad and the first pad Two encapsulant colloids.

As can be seen from the above, since the present invention forms a circuit by, for example, electroplating or electroless plating, instead of using an etch removal method to form a line, the present invention can achieve the requirements of a fine line; further, the package structure of the present invention ultimately It only has a package colloid and does not have a core plate or the like, so that material cost can be effectively saved.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms used in the specification, such as "upper", "top", "bottom" and "a", are used for convenience of description and are not intended to limit the scope of the invention. Changes or adjustments to a relationship are considered to be within the scope of the invention, without departing from the scope of the invention.

2A to 2O are cross-sectional views showing a package structure, a substrate structure, and a method of fabricating the same according to the present invention, wherein the second N-1, 2N-1', 2N-2, and 2N-3 patterns are different from the 2N map. In the aspect, the second embodiment of the 2O-1, 2O-1', 2O-2, and 2O-3 diagrams is shown in Fig. 2O.

First, as shown in FIG. 2A, a carrier board 20 is prepared, on which a plurality of carrier board blocks 201 are defined.

As shown in FIG. 2B, a first resist layer 21 is formed on one surface of the carrier board 20.

As shown in FIG. 2C, a first resistive opening 211 and a patterned resistive opening 212 for exposing the carrier 20 are formed in the first resist layer 21 of each of the carrier blocks 201.

As shown in FIG. 2D, a patterned metal layer having a first metal block 221 and a line 222 is formed in the first resistive opening 211 and the patterned resist opening 212, respectively, and the wiring 222 has a plurality of, for example, soldering. The first pad 222a of the finger pad and the second pad 222b, such as a solder ball pad.

As shown in FIG. 2E, a second resist layer 23 is formed on the first resist layer 21, the first metal block 221, and the line 222.

As shown in FIG. 2F, a second resistive opening 230 corresponding to each of the first metal blocks 221 is formed in the second resist layer 23.

As shown in FIG. 2G, a second metal block 24 is formed on the first metal block 221 in the second resistive layer opening 230.

As shown in FIG. 2H, the first resist layer 21 and the second resist layer 23 are removed.

As shown in FIG. 2I, a first encapsulant 25 covering the first metal block 221, the line 222 and the second metal block 24 is formed on the carrier board 20.

As shown in FIG. 2J, the first encapsulant 25 is polished until the bottom surface of the second metal block 24 is exposed, so that the first surface 25a (bottom surface) and the second surface 25b of the first encapsulant 25 are The roughness of the top surface is not equal.

As shown in FIG. 2K, the first metal block 221 and the second metal block 24 are removed, and a slot 250 is defined in the first encapsulant 25 of each of the carrier block blocks 201.

As shown in FIG. 2L, a portion of the carrier 20 is removed, and the first pad 222a, the second pad 222b, and the slot 250 are exposed. For example, only the frame 202 can be left as shown in the drawing. The substrate structure 3 of the invention.

As shown in FIG. 2M, a surface treatment layer 26 such as a nickel/palladium/gold layer is formed on the first pad 222a and the second pad 222b.

As shown in FIG. 2N, a semiconductor wafer 30 having a plurality of semiconductor wafers 31 is disposed on the first surface 25a of the first encapsulant 25, each of the semiconductor wafers 31 having an active surface 31a and an inactive surface 31b, and the active A plurality of connection pads 311 corresponding to the slots 250 are formed on the surface 31a. Then, the connection pads 311 and the first pads 222a are electrically connected by a first conductive member 32 such as a bonding wire, and a cover is formed. The first conductive element 32, the connection pad 311 and the second encapsulant 33 of the first pad 222a, and the second conductive element 34 such as a solder ball are formed on the second pad 222b.

Or, as shown in FIG. 2N-1, the first surface 25a of the first encapsulant 25 is connected to the substrate 37, and includes a plurality of semiconductor wafers 31 and a third encapsulant 36 covering each of the semiconductor wafers 31. Each of the semiconductor wafers 31 has an active surface 31a and an inactive surface 31b, and the active surface 31a is formed with a plurality of connection pads 311 corresponding to the respective apertures 250.

Alternatively, as shown in the second N-1', the substrate 37 of the second N-1 is further provided with a heat sink 35 attached to the bottom surface of the third encapsulant 36.

Alternatively, as shown in FIG. 2N-2, the substrate 37 is attached to the first surface 25a of the first encapsulant 25, and includes a plurality of semiconductor wafers 31, a third encapsulant 36 and a heat sink 35. The third package The colloid 36 is disposed on the side surface of each of the semiconductor wafers 31. Each of the semiconductor wafers 31 has an active surface 31a and an inactive surface 31b. The active surface 31a is formed with a plurality of connection pads 311 corresponding to the slots 250. The heat sink 35 is disposed on the third encapsulant 36 and the inactive surface 31b of the semiconductor wafer 31. In the method of the present embodiment, the bottom surface of the third encapsulant 36 of the package structure of the second N-1 is polished, and the inactive surface 31b of the semiconductor wafer 31 is exposed, and the fins 35 are attached.

Alternatively, as shown in FIG. 2N-3, the heat sink 35 may be attached to the bottom surface of the semiconductor wafer 30 to enhance the overall heat dissipation effect.

As shown in the 2nd, 2O-1, 2O-1', 2O-2, and 2O-3 diagrams, the graphs are continued from the 2N, 2N-1, 2N-1', 2N-2, and 2N-3 maps, respectively. A singulation process is performed to form a plurality of package structures 2.

The present invention discloses a substrate structure 3, comprising: a substrate having a plurality of substrate units, each of the substrate units comprising: a first encapsulant 25 having a first surface 25a and a second surface 25b opposite to each other a slot 250 of the surface 25a and the second surface 25b; and a line 222 formed on the second surface 25b of the first encapsulant 25 and having a plurality of first pads 222a and a second exposed on the second surface 25b The pad 222b; and the frame 202 are circumferentially disposed on the periphery of the substrate.

In the substrate structure 3, a surface treatment layer 26 including, for example, a nickel/palladium/gold layer is formed on the first pad 222a and the second pad 222b.

In the substrate structure 3 of the present invention, the roughness of the first surface 25a and the second surface 25b of the first encapsulant 25 is not equal.

According to the substrate structure 3, the slot 250 of the first encapsulant 25 is stepped, and the aperture of the slot 250 is tapered from the second surface 25b to the first surface 25a.

The package structure 2 includes a semiconductor wafer 31 having an opposite active surface 31a and an inactive surface 31b, and the active surface 31a has a plurality of connection pads 311. The first encapsulant 25 is disposed on the semiconductor package 31. The active surface 31a has an opposite first surface 25a and a second surface 25b and a slot 250 extending through the first surface 25a and the second surface 25b and exposing the connecting pad 311. The first surface 25a is connected to the slot The active surface 31a; the line 222 is formed on the second surface 25b of the first encapsulant 25, and has a plurality of first pads 222a and second pads 222b exposed on the second surface 25b; the first conductive element 32 The connection pad 311 and the first pad 222a are electrically connected, and the second encapsulant 33 covers the first conductive element 32, the connection pad 311 and the first pad 222a.

The package structure 2 of the present invention further includes a third encapsulant 36 disposed on the first surface 25a of the first encapsulant 25 and completely covering each of the semiconductor wafers 31; or The third package encapsulant 36 is disposed on the first surface 25a of the first encapsulant 25 and covers the side surface of each of the semiconductor wafers 31.

According to the package structure 2, a heat sink 35 is disposed on the third encapsulant 36 or the third encapsulant 36 and the inactive surface 31b of the semiconductor wafer 31.

In the foregoing package structure 2, a surface treatment layer 26 including, for example, a nickel/palladium/gold layer is formed on the first pad 222a and the second pad 222b.

In the package structure 2 of the embodiment, the heat sink 35 is further provided and is attached to the inactive surface 31b of the semiconductor wafer 31.

In the package structure 2 described above, the second conductive element 34 is further disposed on the second pad 222b.

In the package structure 2, the first conductive element 32 is a bonding wire, and the second conductive element 34 is a solder ball.

According to the package structure 2, the slot 250 of the first encapsulant 25 is stepped, and the aperture of the slot 250 is tapered from the second surface 25b to the first surface 25a.

In summary, the present invention can achieve the requirements of fine lines because the present invention forms lines by means of, for example, electroplating or electroless plating, rather than using an etching removal method, as compared with the prior art. The package structure of the present invention finally has only a package colloid, and does not have a core plate or the like, so that material cost can be effectively saved.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10. . . Core board

100. . . Slot

11. . . Copper layer

111. . . Copper line

111a. . . Welding finger pad

111b. . . Solder ball pad

12. . . Resistance layer

120. . . Resistive open area

13. . . Solder mask

131. . . First opening

132. . . Second opening

14. . . Metal layer

15, 31. . . Semiconductor wafer

151. . . Solder pad

16. . . Welding wire

17. . . Encapsulant

18. . . Solder ball

20. . . Carrier board

201. . . Carrier board block

202. . . frame

twenty one. . . First resistive layer

211. . . First barrier opening

212. . . Patterned barrier opening

221. . . First metal block

222. . . line

222a. . . First pad

222b. . . Second pad

twenty three. . . Second resistive layer

230. . . Second barrier opening

twenty four. . . Second metal block

25. . . First encapsulant

250. . . Slot

25a. . . First surface

25b. . . Second surface

26. . . Surface treatment layer

30. . . Semiconductor wafer

31a. . . Active surface

31b. . . Inactive surface

311. . . Connection pad

32. . . First conductive element

33. . . Second encapsulant

34. . . Second conductive element

35. . . heat sink

36. . . Third encapsulant

37. . . Substrate

2. . . Package structure

3. . . Substrate structure

1A to 1I are cross-sectional views of a conventional package structure and a method of manufacturing the same;

2A to 2O are cross-sectional views showing a package structure, a substrate structure, and a method of manufacturing the same according to the present invention, wherein the second N-1, 2N-1', 2N-2, and 2N-3 patterns are different from the second embodiment. The 2O-1, 2O-1', 2O-2, and 2O-3 diagrams are different from the second embodiment.

2. . . Package structure

222. . . line

222a. . . First pad

222b. . . Second pad

25. . . First encapsulant

250. . . Slot

25a. . . First surface

25b. . . Second surface

26. . . Surface treatment layer

31. . . Semiconductor wafer

31a. . . Active surface

31b. . . Inactive surface

311. . . Connection pad

32. . . First conductive element

33. . . Second encapsulant

34. . . Second conductive element

Claims (27)

A package structure without a core board includes: a semiconductor wafer having opposite active and non-active surfaces, and the active surface has a plurality of connection pads; the first encapsulant is disposed on the active surface and has a first surface and a second surface and a slot extending through the first surface and the second surface and exposing the connection pad, the first surface is connected to the active surface; and the circuit is formed on the first encapsulant a second surface having a plurality of first pads and second pads exposed on the second surface; a first conductive element electrically connecting the first pad and the connection pad; and a second encapsulant covering The first conductive element, the connection pad and the first pad. The package structure of claim 1, further comprising a third encapsulant disposed on the first surface of the first encapsulant and completely covering the semiconductor wafer. The package structure of claim 1, further comprising a third encapsulant disposed on the first surface of the first encapsulant and covering the side surface of the semiconductor wafer. The package structure according to claim 2 or 3, further comprising a heat sink disposed on the third encapsulant or the third encapsulant and the inactive surface of the semiconductor wafer. The package structure as described in item 1 of the patent application, including the setting a second conductive element on the second pad. The package structure according to claim 5, wherein the first conductive element is a bonding wire, and the second conductive element is a solder ball. The package structure of claim 1, wherein the nickel/palladium/gold layer is formed on the first pad and the second pad. The package structure as claimed in claim 1 further comprises a heat sink attached to the inactive surface of the semiconductor wafer. The package structure of claim 1, wherein the slot of the first encapsulant is stepped, and the slot aperture is tapered from the second surface to the first surface. A substrate structure without a core board includes: a substrate having a plurality of substrate units, each of the substrate units comprising: an encapsulant having opposite first and second surfaces and through the first surface and the second surface a slot; and a line formed on the second surface of the encapsulant and having a plurality of first pads and second pads exposed on the second surface; and a frame disposed around the periphery of the substrate. The substrate structure of claim 10, wherein the nickel/palladium/gold layer is formed on the first pad and the second pad. The substrate structure of claim 10, wherein the roughness of the first surface and the second surface of the encapsulant is not equal. The substrate structure according to claim 10, wherein the slot of the encapsulant is stepped, and the slot aperture is the second The surface tapers to the first surface. A method for fabricating a substrate structure without a core board, comprising: providing a patterned metal layer having a first metal block and a line; forming a second metal block on the first metal block; forming the pattern Forming a metal layer and the second metal block and exposing the encapsulant of the second metal block; and removing the first metal block and the second metal block to define a slot. The method for fabricating a substrate structure according to claim 14, wherein the step of forming the patterned metal layer comprises: forming a first resist layer on a surface of one of the carrier plates, and the carrier plate is defined by a plurality of carrier plate blocks; forming a first barrier opening and a patterned barrier opening in the first resist layer of each of the carrier blocks; and opening and patterning the first barrier layer The first metal block and the line are respectively formed in the layer opening; and after the slot is defined, the carrier board is removed. The method of fabricating a substrate structure according to claim 14, wherein the circuit has a plurality of first pads and second pads. The method of fabricating a substrate structure according to claim 16, wherein the first pad and the second pad are formed to form a nickel/palladium/gold layer. The method of fabricating a substrate structure according to claim 17, wherein removing the carrier plate removes a portion of the carrier plate and leaving the periphery The lower part of the carrier is used as a frame. The method of fabricating a substrate structure according to claim 14, wherein the step of forming the encapsulant comprises grinding the encapsulant until the second metal block is exposed. A method for fabricating a package structure without a core board includes: providing a substrate structure, the substrate structure comprising: a first encapsulant having opposite first and second surfaces and through the first surface and the second surface a slot, and a circuit formed on the second surface of the first encapsulant and having a plurality of first pads and second pads exposed on the second surface; having opposite active and inactive surfaces The semiconductor wafer is disposed on the first surface of the first encapsulant with its active surface, and the active surface has a plurality of connection pads corresponding to the exposed holes; forming an electrical connection between the first pad and the connection pad a first conductive element; and a second encapsulant covering the first conductive element, the connection pad and the first pad. A method for fabricating a package structure without a core board includes: providing a substrate and a frame disposed around a periphery of the substrate, the substrate having a plurality of substrate units, each of the substrate units comprising: a first encapsulant having a relative a first surface and a second surface and a slot extending through the first surface and the second surface; And a circuit formed on the second surface of the first encapsulant and having a plurality of first pads and second pads exposed on the second surface; and having a first surface on the first encapsulant a semiconductor wafer of a plurality of semiconductor wafers, each of the semiconductor wafers having an opposite active surface and a non-active surface, and each of the active surfaces is formed with a plurality of connection pads exposed to the respective holes; forming an electrical connection between the connection pads and a first conductive element of the first pad; and a second encapsulant covering the first conductive element, the connection pad and the first pad. The method for manufacturing a package structure according to claim 20 or 21, wherein the method further comprises: before the electrically connecting the connection pad and the first pad by the first conductive element, the first pad and the first pad A nickel/palladium/gold layer is formed on the second pad. The method of fabricating a package structure according to claim 21, wherein the heat sink is attached to a bottom surface of the semiconductor wafer. The method for manufacturing a package structure according to claim 20 or 21, further comprising forming a second conductive member on the second pad. For example, the method for manufacturing the package structure described in claim 21 of the patent application includes the singulation process. The method for manufacturing a package structure according to claim 20 or 21, wherein the package structure comprises a first package encapsulant a third encapsulant on the first surface, and the third encapsulant encapsulates the semiconductor wafer. The method of fabricating the package structure of claim 26, comprising: grinding the bottom surface of the third encapsulant until the inactive surface of the semiconductor wafer is exposed.