KR20080011617A - Wafer level chip size package and manufacturing process for the same - Google Patents

Abstract

A wafer level chip size package is provided to increase a vertical distance between a ball land and a semiconductor chip by forming a redistribution in contact with an input/output pad of the semiconductor chip and a ball land in different layers. A plurality of input/output pads(12) are formed in a semiconductor chip(10). A first insulation layer(14) is formed on the semiconductor chip to expose the input/output pads. A plurality of redistributions(20) are formed on the first insulation layer, separately coming in contact with the exposed input/output pads. A second insulation layer(22) is formed on the first insulation layer and the redistributions wherein part of each redistribution is exposed. A plurality of ball lands(26) are formed on each exposed redistribution and a part of the second insulation layer adjacent to the exposed redistribution. A solder ball(28) is attached to the surface of the ball lands. The redistribution and the ball land can be made of a stack structure of a metal seed layer and a metal layer.

Description

Wafer Level Chip Size Package and Manufacturing Method thereof {WAFER LEVEL CHIP SIZE PACKAGE AND MANUFACTURING PROCESS FOR THE SAME}

1 is a cross-sectional view showing a wafer level chip size package prior to a conventional sawing step.

2A through 2F are cross-sectional views illustrating a method of manufacturing a wafer level chip size package according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10 semiconductor chip 12 input / output pad

14: first insulating layer 16: first metal seed layer

20: rewiring 22: second insulating layer

24: second metal seed layer 26: Borland

28: solder ball

The present invention relates to a wafer level chip size package, and more particularly, to a wafer level chip size package in which a redistribution layer and a borland layer are separated, and a manufacturing method thereof.

With the development of the electronics industry, the use of semiconductors in almost all electronic products requires packages of various sizes and shapes.In particular, small home appliances and mobile products require fast processing speed, light weight and high integration of semiconductor chips. do.

The wafer level chip size package is one of the packages that meets the above requirements. Unlike the traditional packaging process starting from the sawing stage, the wafer-level chip size package is used to package the entire wafer at once and cut along the scribe line of the wafer at the end of the process. It is manufactured by separating it into individual die level.

These wafer-level chip-size packages are chip-scale packages with exactly the same die size and package size, resulting in increased substrate efficiency by reducing the foot print for bonding.

In addition, the wafer-level chip size package has an advantage that it is easy to be applied to a high frequency device because the mounting area is short and the wiring length is short compared with a conventional lead type package. Compared to the flip chip package, the pad pitch can be widened, which makes it easy to mount the board.

1 is a cross-sectional view illustrating a wafer level chip size package prior to a sawing step, and the manufacturing method thereof will be described below with reference to the drawing.

As shown in Fig. 1, a first insulating layer 2 is formed on a wafer (not shown) made of several semiconductor chips 1, and then the first insulating layer 2 is known in a known manner. Is patterned to expose the input / output pads 3 and scribe lines of each semiconductor chip 1.

Then, the metal material is rewired through a sputtering process through the sputtering process, and the metal material is patterned to form metal wires 4 electrically connected to the exposed input / output pads 3. Then, the second insulating layer 5 made of a polymer material is coated on the first insulating layer 2 including the metal redistribution 4, and then the second insulating layer 5 is patterned to be Borland. The other end portion 4 of the metal wiring is exposed, and the second insulating layer portion on the scribe line of the wafer (not shown) is also removed.

Subsequently, a solder ball 6 used as an electrical connection means with the outside is attached on the ball land 4 of the exposed metal redistribution.

Then, although not shown, the wafer is cut along the scribe line using a diamond wheel or the like to separate into individual packages.

However, when the metal redistribution and the borland are formed on the same layer during the above process, an electrical short may occur depending on the shape and location of the solder balls attached to the predetermined metal redistribution, so that the distance between the metal redistributions is wide. And thus there is a lack of space for wiring.

Also, in the case of a package that requires a large number of solder balls as the size of the semiconductor chip becomes smaller and more integrated, the design may be impossible or limited due to insufficient wiring space, and the layout design of Borland may be variably changed as necessary. As a result, the spacing between the wires follows a set design rule. In this case, when it is necessary to change the size or shape of the borland for reasons of electrical characteristics or reliability of the package, it is more difficult to manufacture a wafer level chip size package because the overall design of the semiconductor chip has to be changed.

The present invention has been made to solve the conventional problems as described above, the object of the present invention is to design a package that is made to consider the electrical characteristics and improve the spatial efficiency by increasing the variability of the design.

In order to achieve the above object, a wafer level chip size package according to the present invention, a semiconductor chip having a plurality of input and output pads, a first insulating layer formed to expose the input and output pads on the semiconductor chip, the first insulation A plurality of redistribution lines formed to individually contact each input / output pad exposed on the layer, a second insulating layer formed on the first insulation layer and redistribution lines and formed so that a portion of each redistribution line is exposed; And a plurality of ball lands respectively formed on the portion and the portion of the second insulating layer adjacent thereto, and solder balls attached on the ball lands.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2F is a cross-sectional view illustrating a package manufactured according to an embodiment of the present invention. As illustrated, the wafer level chip size package of the present invention may include a semiconductor chip 10 having a plurality of input / output pads 12 and a plurality of input / output pads 12 exposed on the semiconductor chip 10. 1 insulating layer 14, a plurality of redistributions 20 formed so as to make individual contact with each of the input / output pads 12 exposed on the first insulating layer 14, and the first insulating layer 14 and the cultivation A second insulating layer 22 formed on the lines 20 and formed to expose a portion of each redistribution 20, and a portion of the exposed redistribution 20 and the second insulating layer 22 adjacent thereto. And a plurality of ball lands 26 each formed on the portion, and a plurality of solder balls 28 attached on the ball lands 26.

Here, the first metal seed layer 16 and the second seed metal layer 24 are formed under the redistribution 20 and the borland 26 to be used as a cathode during electroplating to allow smooth flow of electricity to the wafer. It is.

In addition, the electrical wiring structure of the package includes a first metal layer (hereinafter referred to as "rewiring": 20) in contact with the input / output pad of the semiconductor chip and a second metal layer (hereinafter, referred to as a means for making electrical connection with the outside). Borland ": formed into a double layer separated into upper layers, including 26).

In addition, if necessary, a set of layers having a lamination form of the first insulating layer 14, the first metal seed layer 16, and the redistribution 20 may be stacked in multiple layers or more, and the second layer may be disposed thereon. A wafer level chip size package may be formed in the form of an insulating layer, a second metal seed layer, and a borland.

2A through 2F are cross-sectional views illustrating a method of manufacturing a wafer level chip size package according to an exemplary embodiment of the present invention. In detail, as illustrated in FIG. 2A, a plurality of input / output pads 12 may be formed. A first insulating layer 14 made of a polymer material is coated on several semiconductor chips 10 arranged, and a portion of the first insulating layer 14 is etched to expose the input / output pads 12.

Then, as shown in FIG. 2B, the electrode is used as a cathode during electroplating to form metal wiring while contacting the input / output pad 12 exposed on the first insulating layer 14 to smoothly flow electricity to the wafer. And depositing a first metal seed layer 16, and applying photoresist to form metal wires by electroplating on the first metal seed layer 16, and then patterning some regions. One mask pattern 18a is formed to expose the first metal seed layer 16.

Subsequently, as shown in FIG. 2C, redistribution lines 20 made of copper (Cu) or the like are formed on the exposed first metal seed layer 16 by using electrolytic plating, and the first mask pattern and The lower first metal seed layer 16 is removed to form a lower layer including redistribution.

Then, as illustrated in FIG. 2D, a second insulating layer 22 is applied on the redistribution 20 and the first insulating layer 14 to insulate the upper layer on the redistribution 20. In addition, a portion of the second insulating layer 22 is patterned to form an electrical contact between the redistribution 20 and the upper layer.

Subsequently, the processes in FIGS. 2B and 2C are repeated to deposit the second metal seed layer 24 on the second insulating layer 22 and in contact with the redistribution 20, as shown in FIG. 2E. After forming the second mask pattern 18c coated with the photoresist and patterned thereon, electroplating is performed to form the ball land 26.

Then, as shown in FIG. 2F, the second mask pattern and the second metal seed layer 24 underneath are removed to form an upper layer including the ball land, and the solder balls 28 are mounted on the ball land 26. (Mount)

According to the present invention, a wafer level chip size package having stable electrical characteristics and high space efficiency can be fabricated by separating redistribution and borland contacted to input / output pads of a semiconductor chip into different layers.

In addition, thermal fatigue characteristics in solder joints with temperature, which is one of the most vulnerable parts of the wafer level chip size package, can be improved.

If the metal rewiring and borland are present in the same layer, the entire metal rewiring should be changed if the borland needs to be changed, and the electrical characteristics, design possibilities, and fairness of the semiconductor chip must be reassessed by the partially changed borlands. When the line and the borland are separated into different layers, even if the design of the device changes, the position of the borland remains fixed and only the design of the redistribution can be changed without affecting the overall device design.

As described above, since the redistribution and the borland contacted to the input and output pads of the semiconductor chip are separated into different layers, the vertical distance between the borland and the semiconductor chip is increased, and the space for forming the borland is increased.

Therefore, it is easy to change the size and shape of the ball land, which gives a lot of freedom in the design of the package, it is possible to increase the variability of the design for the solder joint, it is possible to design a package that fully considers the electrical characteristics. .

In addition, it is possible to use the same Borland design in common among different chips, and standardize various types of devices, thereby reducing the test cost for evaluating the characteristics of the semiconductor chip and not damaging the structure of the entire semiconductor chip. It is easy to evaluate the characteristics of the package, thereby reducing the manufacturing cost of the entire semiconductor chip.

Claims (5)

A semiconductor chip having a plurality of input / output pads; A first insulating layer formed to expose the input / output pads on the semiconductor chip; A plurality of redistribution formed to individually contact each input / output pad exposed on the first insulating layer; A second insulating layer formed on the first insulating layer and the redistribution lines and formed to expose a portion of each redistribution line; A plurality of borland formed on each of the exposed redistribution portions and the second insulating layer portions adjacent thereto; And A solder ball attached to the ball land; of And a wafer level chip size package. The method of claim 1, The redistribution and borland is a wafer level chip size package, characterized in that consisting of a metal seed layer and a layer structure of the metal layer. Forming a first insulating layer on the wafer, which is partitioned by a scribe line and provided with a plurality of semiconductor chips with a plurality of input / output pads, to expose the input / output pads; Forming a plurality of redistribution lines individually connected to the input / output pads exposed on the first insulating layer; Forming a second insulating layer on the first insulating layer including the redistribution so that a portion of each redistribution is exposed; Forming a ball land on each of the exposed redistribution portion and a portion of the second insulating layer adjacent thereto; And Attaching solder balls on the borlands; And Cutting to each semiconductor chip level along the scribe line; Method of manufacturing a wafer level chip size package comprising a. The method of claim 3, wherein forming the redistribution step, Forming a first metal seed layer on the first insulating layer; Forming a first mask pattern exposing redistribution forming regions on the first metal seed layer; Forming a first metal layer on the exposed first metal seed layer portions through a plating process; And Removing the first mask pattern and portions of the first metal seed layer thereunder; Method for producing a wafer level chip size package, characterized in that consisting of. The method of claim 3, wherein the forming of the borland, Depositing a second metal seed layer on the second insulating layer including the exposed redistribution portion; Forming a second mask pattern exposing the ballland forming regions on the second metal seed layer; Forming a second metal layer on the exposed second metal seed layer portions through a plating process; And Removing the second mask pattern and portions of the second metal seed layer thereunder; And a wafer level chip size package.

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