TWI400783B - Package structure and manufacturing method thereof - Google Patents

Package structure and manufacturing method thereof Download PDF

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Publication number
TWI400783B
TWI400783B TW099124010A TW99124010A TWI400783B TW I400783 B TWI400783 B TW I400783B TW 099124010 A TW099124010 A TW 099124010A TW 99124010 A TW99124010 A TW 99124010A TW I400783 B TWI400783 B TW I400783B
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metal layer
layer
wafer
conductive layer
package structure
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TW099124010A
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TW201205744A (en
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Chia Ching Chen
Yi Chuan Ding
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

封裝結構及其製作方法Package structure and manufacturing method thereof

本發明是有關於一種半導體結構及其製作方法，且特別是有關於一種封裝結構及其製作方法。The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a package structure and a method of fabricating the same.

晶片封裝的目的在於保護裸露的晶片、降低晶片接點的密度及提供晶片良好的散熱。常見的封裝方法是晶片透過打線接合(wire bonding)或覆晶接合(flip chip bonding)的方式而安裝至一封裝載板，以使晶片上的接點可電性連接至封裝載板。因此，晶片的接點分佈可藉由封裝載板重新配置，以符合下一層級的外部元件的接點分佈。The purpose of the chip package is to protect the exposed wafer, reduce the density of the wafer contacts, and provide good heat dissipation from the wafer. A common packaging method is that the wafer is mounted to a loading board by wire bonding or flip chip bonding so that the contacts on the wafer can be electrically connected to the package carrier. Therefore, the contact distribution of the wafer can be reconfigured by the package carrier to conform to the junction distribution of the external components of the next level.

本發明提供一種封裝結構，用以封裝晶片。The present invention provides a package structure for packaging a wafer.

本發明提供一種封裝結構的製作方法，用以製作上述之封裝結構。The invention provides a method for fabricating a package structure for fabricating the above package structure.

本發明提出一種封裝結構，其包括一基板、一晶片、一第一金屬層、一第二金屬層、一第三金屬層及一防銲層。基板具有彼此相對的一第一表面與一第二表面及至少一連接第一表面與第二表面的貫孔。晶片配置於基板上且位於第一表面上。第一金屬層配置於基板的第一表面上且暴露出部分第一表面，其中第一金屬層延伸至晶片上。第二金屬層配置於基板的第二表面上且暴露出部分第二表面。第三金屬層覆蓋貫孔的內壁且連接第一金屬層與第二金屬層。晶片透過第一金屬層與第三金屬層及第二金屬層電性連接。防銲層填充貫孔且包覆晶片、至少部分第一金屬層、至少部分第二金屬層及第三金屬層。The invention provides a package structure comprising a substrate, a wafer, a first metal layer, a second metal layer, a third metal layer and a solder resist layer. The substrate has a first surface and a second surface opposite to each other and at least one through hole connecting the first surface and the second surface. The wafer is disposed on the substrate and on the first surface. The first metal layer is disposed on the first surface of the substrate and exposes a portion of the first surface, wherein the first metal layer extends onto the wafer. The second metal layer is disposed on the second surface of the substrate and exposes a portion of the second surface. The third metal layer covers the inner wall of the through hole and connects the first metal layer and the second metal layer. The wafer is electrically connected to the third metal layer and the second metal layer through the first metal layer. The solder resist layer fills the via and covers the wafer, at least a portion of the first metal layer, at least a portion of the second metal layer, and the third metal layer.

本發明提出一種封裝結構的製作方法，其包括下述步驟。提供一基板。基板具有彼此相對的一第一表面與一第二表面及至少一連接第一表面與第二表面的貫孔。基板上已形成有一位於第一表面上且暴露出部分第一表面的第一導電層及一位於第二表面上的第二導電層。配置一晶片於第一導電層所暴露出的部分第一表面上。形成一圖案化電鍍罩幕於部分第一導電層上、部分第二導電層上及部分晶片上。形成一金屬層於未配置圖案化電鍍罩幕的第一導電層與第二導電層上。金屬層覆蓋貫孔的內壁及第一導電層所暴露出的部分第一表面上。金屬層延伸至於晶片上，且晶片透過金屬層與第一導電層及第二導電層電性連接。移除圖案化電鍍罩幕及其下方之第二導電層，以暴露出部分第一表面、部分第二表面及部分晶片。形成一防銲層以填充貫孔且包覆晶片及部分金屬層。The present invention provides a method of fabricating a package structure that includes the following steps. A substrate is provided. The substrate has a first surface and a second surface opposite to each other and at least one through hole connecting the first surface and the second surface. A first conductive layer on the first surface and exposing a portion of the first surface and a second conductive layer on the second surface are formed on the substrate. A wafer is disposed on a portion of the first surface exposed by the first conductive layer. A patterned plating mask is formed on a portion of the first conductive layer, a portion of the second conductive layer, and a portion of the wafer. A metal layer is formed on the first conductive layer and the second conductive layer where the patterned plating mask is not disposed. The metal layer covers the inner wall of the through hole and a portion of the first surface exposed by the first conductive layer. The metal layer extends onto the wafer, and the wafer is electrically connected to the first conductive layer and the second conductive layer through the metal layer. The patterned plating mask and the second conductive layer thereunder are removed to expose a portion of the first surface, a portion of the second surface, and a portion of the wafer. A solder mask is formed to fill the via and cover the wafer and a portion of the metal layer.

基於上述，由於本發明是在進行基板製程時，同時進行晶片封裝製程，如此一來，可以減少製程步驟。Based on the above, since the present invention performs the wafer packaging process while performing the substrate process, the process steps can be reduced.

為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖1是本發明之一實施例之一種封裝結構的剖面示意圖。請參考圖1，在本實施例中，封裝結構100包括一基板110、一晶片140、一第一金屬層152、一第二金屬層154、一第三金屬層156及一防銲層160。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a package structure in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the package structure 100 includes a substrate 110 , a wafer 140 , a first metal layer 152 , a second metal layer 154 , a third metal layer 156 , and a solder resist layer 160 .

詳細來說，基板110具有彼此相對的一第一表面112與一第二表面114及至少一連接第一表面112與第二表面114的貫孔116(圖1中僅示意地繪示一個貫孔116)。在本實施例中，基板110為一介電核心(dielectric core)。In detail, the substrate 110 has a first surface 112 and a second surface 114 opposite to each other and at least one through hole 116 connecting the first surface 112 and the second surface 114 (only one through hole is schematically illustrated in FIG. 1 ) 116). In this embodiment, the substrate 110 is a dielectric core.

晶片140配置於基板110上且位於第一表面112上，其中晶片140具有一主動面142與多個位於主動面142上的接點144。The wafer 140 is disposed on the substrate 110 and located on the first surface 112 . The wafer 140 has an active surface 142 and a plurality of contacts 144 on the active surface 142 .

第一金屬層152配置於基板110的第一表面112上且暴露出部分第一表面112，其中第一金屬層152從第一表面112經由晶片140的一側延伸至晶片140的主動面142上的這些接點144。第二金屬層154配置於基板110的第二表面114上且暴露出部分第二表面114。第一金屬層152及第二金屬層154為兩層水平導電圖案，而第三金屬層156則為兩層線路圖案之間的垂直導電通道。The first metal layer 152 is disposed on the first surface 112 of the substrate 110 and exposes a portion of the first surface 112, wherein the first metal layer 152 extends from the first surface 112 through one side of the wafer 140 to the active surface 142 of the wafer 140. These contacts 144. The second metal layer 154 is disposed on the second surface 114 of the substrate 110 and exposes a portion of the second surface 114. The first metal layer 152 and the second metal layer 154 are two horizontal conductive patterns, and the third metal layer 156 is a vertical conductive path between the two line patterns.

第三金屬層156覆蓋貫孔116的內壁且連接第一金屬層152與第二金屬層154。特別是，在本實施例中，由於第一金屬層152延伸至晶片140的這些接點144上，因此晶片140上的這些接點144可透過第一金屬層152與第三金屬層156及第二金屬層154電性連接。防銲層160填充貫孔116且包覆晶片140、至少部分第一金屬層152、至少部分第二金屬層154及第三金屬層156。The third metal layer 156 covers the inner wall of the through hole 116 and connects the first metal layer 152 and the second metal layer 154. In particular, in the present embodiment, since the first metal layer 152 extends to the contacts 144 of the wafer 140, the contacts 144 on the wafer 140 can pass through the first metal layer 152 and the third metal layer 156 and The two metal layers 154 are electrically connected. The solder resist layer 160 fills the through holes 116 and covers the wafer 140, at least a portion of the first metal layer 152, at least a portion of the second metal layer 154, and the third metal layer 156.

值得一提的是，在本實施例中，一部分未被防銲層160所包覆之部分第一金屬層152可構成多個第一接墊172，而一部分未被防銲層160所包覆之部分第二金屬層154可構成多個第二接墊174。這些第一接墊172及這些第二接墊174適於與一外部電路(例如電路板或另一晶片)電性連接。因此，可增加本實施例之封裝結構100的應用性。It is worth mentioning that in this embodiment, a portion of the first metal layer 152 not covered by the solder resist layer 160 may constitute a plurality of first pads 172, and a portion is not covered by the solder resist layer 160. A portion of the second metal layer 154 may constitute a plurality of second pads 174. The first pads 172 and the second pads 174 are adapted to be electrically connected to an external circuit, such as a circuit board or another wafer. Therefore, the applicability of the package structure 100 of the present embodiment can be increased.

以下將以另一實施例配合圖2A至圖2I來詳細說明上述實施例之封裝結構的製作方法。Hereinafter, a method of fabricating the package structure of the above embodiment will be described in detail with another embodiment in conjunction with FIGS. 2A to 2I.

圖2A至圖2I為本發明之另一實施例之一種封裝結構的製作方法的剖面示意圖。請先參考圖2A，依照本實施例的封裝結構的製作方法，首先，提供一基板110，其中基板110具有彼此相對的一第一表面112與一第二表面114，且此基板110上已形成有一位於第一表面112上且暴露出部分第一表面112的第一導電層120及一位於第二表面114上的第二導電層130。2A to 2I are schematic cross-sectional views showing a method of fabricating a package structure according to another embodiment of the present invention. Referring to FIG. 2A , a method for fabricating a package structure according to the present embodiment, firstly, a substrate 110 is provided, wherein the substrate 110 has a first surface 112 and a second surface 114 opposite to each other, and the substrate 110 is formed. There is a first conductive layer 120 on the first surface 112 and exposing a portion of the first surface 112 and a second conductive layer 130 on the second surface 114.

接著，請參考圖2B，形成至少一連接基板110之第一表面112與第二表面114的貫孔116。在本實施例中，形成貫孔116的方法例如是機械式鑽孔法，但在此並不以此為限。Next, referring to FIG. 2B, at least one through hole 116 connecting the first surface 112 and the second surface 114 of the substrate 110 is formed. In the present embodiment, the method of forming the through hole 116 is, for example, a mechanical drilling method, but is not limited thereto.

接著，請參考圖2C，配置一晶片140於第一導電層120所暴露出之基板110的部分第一表面112上。在本實施例中，晶片140具有一主動面142與多個位於主動面142上的接點144。Next, referring to FIG. 2C, a wafer 140 is disposed on a portion of the first surface 112 of the substrate 110 exposed by the first conductive layer 120. In the present embodiment, the wafer 140 has an active surface 142 and a plurality of contacts 144 on the active surface 142.

接著，請參考圖2D，形成一電鍍種子層180於第一導電層120、第一導電層130所暴露出的第一表面112、第二導電層130、貫孔116內壁及晶片140上。Next, referring to FIG. 2D, a plating seed layer 180 is formed on the first conductive layer 120, the first surface 112 exposed by the first conductive layer 130, the second conductive layer 130, the inner wall of the through hole 116, and the wafer 140.

接著，請參考圖2E，形成一電鍍罩幕190於電鍍種子層180上，其中電鍍罩幕190並未覆蓋位於貫孔116內壁上的電鍍種子層180。Next, referring to FIG. 2E, a plating mask 190 is formed on the plating seed layer 180, wherein the plating mask 190 does not cover the plating seed layer 180 on the inner wall of the through hole 116.

接著，請參考圖2F，圖案化電鍍罩幕190，以形成一圖案化電鍍罩幕192，其中圖案化電鍍罩幕192位於部分第一導電層120上方之電鍍種子層180上、部分第二導電層130上方之電鍍種子層180上及晶片140之部分主動面142上方之電鍍種子層180上。在本實施例中，圖案化電鍍罩幕192可藉由形成光阻層並對光阻層曝光及顯影來加以製作。Next, referring to FIG. 2F, the plating mask 190 is patterned to form a patterned plating mask 192, wherein the patterned plating mask 192 is located on the plating seed layer 180 above the portion of the first conductive layer 120, and partially partially conductive. The plating seed layer 180 over the layer 130 and the plating seed layer 180 over the active surface 142 of the wafer 140. In this embodiment, the patterned plating mask 192 can be fabricated by forming a photoresist layer and exposing and developing the photoresist layer.

接著，請參考圖2G，以圖案化電鍍罩幕190為罩幕來進行一電鍍製程，以於未配置圖案化電鍍罩幕192且對應第一導電層120與第二導電層130的電鍍種子層180上形成一金屬層。Next, referring to FIG. 2G, a plating process is performed by patterning the plating mask 190 as a mask to form a plating seed layer that is not configured with the patterned plating mask 192 and corresponding to the first conductive layer 120 and the second conductive layer 130. A metal layer is formed on 180.

在本實施例之中，金屬層包括一第一金屬層152、一第二金屬層154及一第三金屬層156。詳細來說，第一金屬層152配置於基板110之第一表面112上方的電鍍種子層180上，第二金屬層154配置於基板110之第二表面114上方的電鍍種子層180上，而第三金屬層156覆蓋貫孔116內壁上的電鍍種子層180，且連接第一金屬層152與第二金屬層154。特別是，在本實施例中，第一金屬層152從第一表面112經由晶片140的一側延伸至於晶片140之主動面142的這些接墊144上方的電鍍種子層180，且晶片140上的這些接墊144可透過第一金屬層152與第三金屬層156及第二金屬層154電性連接。In this embodiment, the metal layer includes a first metal layer 152, a second metal layer 154, and a third metal layer 156. In detail, the first metal layer 152 is disposed on the plating seed layer 180 above the first surface 112 of the substrate 110, and the second metal layer 154 is disposed on the plating seed layer 180 above the second surface 114 of the substrate 110. The three metal layer 156 covers the plating seed layer 180 on the inner wall of the through hole 116 and connects the first metal layer 152 and the second metal layer 154. In particular, in the present embodiment, the first metal layer 152 extends from the first surface 112 through one side of the wafer 140 to the plating seed layer 180 over the pads 144 of the active surface 142 of the wafer 140, and on the wafer 140 The pads 144 are electrically connected to the third metal layer 156 and the second metal layer 154 through the first metal layer 152 .

然後，請參考圖2H，移除圖案化電鍍罩幕192及其下方之部分電鍍種子層180，以暴露出部分第一表面112及晶片140的部分主動面142。再次必須說明的是，移除圖案化電鍍罩幕192及其下方之第一導電層120與第二導電層130的方法例如是剝離法(stripping)，而移除電鍍種子層180的方法例如是快速蝕刻法(flash etching)。Then, referring to FIG. 2H, the patterned plating mask 192 and a portion of the plating seed layer 180 thereunder are removed to expose a portion of the first surface 112 and a portion of the active surface 142 of the wafer 140. It must be noted again that the method of removing the patterned plating mask 192 and the first conductive layer 120 and the second conductive layer 130 therebelow is, for example, stripping, and the method of removing the plating seed layer 180 is, for example, Flash etching.

接著，請同樣參考圖2H，當最初即採用第一導電層120及第二導電層130時，在移除圖案化電鍍罩幕192及其下方之部分電鍍種子層180以後，再圖案化第一導電層120及第二導電層130，以暴露出部分第一表面112及部分第二表面114。圖案化第一導電層120及第二導電層130的方法可藉由蝕刻罩幕配合蝕刻來達成，其中蝕刻罩幕例如是圖案化光阻。Next, referring to FIG. 2H, when the first conductive layer 120 and the second conductive layer 130 are initially used, after the patterned plating mask 192 and a portion thereof under the plating seed layer 180 are removed, the first pattern is patterned. The conductive layer 120 and the second conductive layer 130 expose a portion of the first surface 112 and a portion of the second surface 114. The method of patterning the first conductive layer 120 and the second conductive layer 130 can be achieved by an etching mask matching etching, wherein the etching mask is, for example, a patterned photoresist.

最後，請參考圖2I，形成一防銲層160以填充貫孔116且包覆晶片140、至少部分第一金屬層152、至少部分第二金屬層154及第三金屬層156。至此，已大致完成封裝結構100a的製作。Finally, referring to FIG. 2I, a solder mask layer 160 is formed to fill the through holes 116 and cover the wafer 140, at least a portion of the first metal layer 152, at least a portion of the second metal layer 154, and the third metal layer 156. So far, the fabrication of the package structure 100a has been substantially completed.

值得一提的是，在本實施例中，一部分未被防銲層160所包覆之第一金屬層152及其下方之部分第一導電層120可構成多個第一接墊172，而一部分未被防銲層160所包覆之第二金屬層154及其下方之部分第二導電層130可構成多個第二接墊174。這些第一接墊172與這些第二接墊174可與外部電路(例如電路板、另一晶片或另一封裝結構)電性連接。It should be noted that, in this embodiment, a portion of the first metal layer 152 not covered by the solder resist layer 160 and a portion of the first conductive layer 120 underneath may form a plurality of first pads 172, and a portion thereof The second metal layer 154 not covered by the solder resist layer 160 and a portion of the second conductive layer 130 underneath may form a plurality of second pads 174. The first pads 172 and the second pads 174 can be electrically connected to an external circuit such as a circuit board, another wafer or another package structure.

綜上所述，由於本實施例是在基板110上進行線路(例如是第一金屬層152、第二金屬層154、第三金屬層156)製作時，同時進行晶片140的封裝製程。如此一來，可以減少封裝結構100的製程步驟。此外，由於這些第一接墊172及這些第二接墊174可與外部電路(例如電路板、另一晶片或另一封裝結構)電性連接，因此可增加本實施例之封裝結構100a的應用性。As described above, in the present embodiment, when the wiring (for example, the first metal layer 152, the second metal layer 154, and the third metal layer 156) is formed on the substrate 110, the packaging process of the wafer 140 is simultaneously performed. As a result, the process steps of the package structure 100 can be reduced. In addition, since the first pads 172 and the second pads 174 can be electrically connected to an external circuit (such as a circuit board, another chip, or another package structure), the application of the package structure 100a of the embodiment can be increased. Sex.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100、100a．．．封裝結構100, 100a. . . Package structure

110．．．基板110. . . Substrate

112．．．第一表面112. . . First surface

114．．．第二表面114. . . Second surface

116．．．貫孔116. . . Through hole

120．．．第一導電層120. . . First conductive layer

130．．．第二導電層130. . . Second conductive layer

140．．．晶片140. . . Wafer

142．．．主動面142. . . Active surface

144．．．接點144. . . contact

152．．．第一金屬層152. . . First metal layer

154．．．第二金屬層154. . . Second metal layer

156．．．第三金屬層156. . . Third metal layer

160．．．防銲層160. . . Solder mask

172．．．第一接墊172. . . First pad

174．．．第二接墊174. . . Second pad

180．．．電鍍種子層180. . . Electroplated seed layer

190．．．電鍍罩幕190. . . Plating mask

192．．．圖案化電鍍罩幕192. . . Patterned plating mask

圖1是本發明之一實施例之一種封裝結構的剖面示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a package structure in accordance with an embodiment of the present invention.

圖2A至圖2I為本發明之另一實施例之一種封裝結構的製作方法的剖面示意圖。2A to 2I are schematic cross-sectional views showing a method of fabricating a package structure according to another embodiment of the present invention.

100．．．封裝結構100. . . Package structure

110．．．基板110. . . Substrate

112．．．第一表面112. . . First surface

114．．．第二表面114. . . Second surface

116．．．貫孔116. . . Through hole

140．．．晶片140. . . Wafer

142．．．主動面142. . . Active surface

144．．．接點144. . . contact

152．．．第一金屬層152. . . First metal layer

154．．．第二金屬層154. . . Second metal layer

156．．．第三金屬層156. . . Third metal layer

160．．．防銲層160. . . Solder mask

172．．．第一接墊172. . . First pad

174．．．第二接墊174. . . Second pad

Claims (13)

一種封裝結構，包括：一基板，具有彼此相對的一第一表面與一第二表面及至少一連接該第一表面與該第二表面的貫孔；一晶片，配置於該基板上且位於該第一表面上；一第一金屬層，配置於該基板的該第一表面上且暴露出部分該第一表面，其中該第一金屬層延伸至該晶片上；一第二金屬層，配置於該基板的該第二表面上且暴露出部分該第二表面；一第三金屬層，覆蓋該貫孔的內壁且連接該第一金屬層與該第二金屬層，其中該晶片透過該第一金屬層與該第三金屬層及該第二金屬層電性連接；以及一防銲層，填充該貫孔且包覆該晶片、至少部分該第一金屬層、至少部分該第二金屬層及該第三金屬層。A package structure comprising: a substrate having a first surface and a second surface opposite to each other and at least one through hole connecting the first surface and the second surface; a wafer disposed on the substrate and located at the substrate a first metal layer disposed on the first surface of the substrate and exposing a portion of the first surface, wherein the first metal layer extends onto the wafer; and a second metal layer is disposed on the first surface a portion of the second surface is exposed on the second surface of the substrate; a third metal layer covering the inner wall of the through hole and connecting the first metal layer and the second metal layer, wherein the wafer transmits the first surface a metal layer electrically connected to the third metal layer and the second metal layer; and a solder mask filling the via and covering the wafer, at least a portion of the first metal layer, and at least a portion of the second metal layer And the third metal layer. 如申請專利範圍第1項所述之封裝結構，其中該晶片具有一主動面與多個位於該主動面上的接點，該第一金屬層延伸至該些接點上，且該些接點透過該第一金屬層與該第三金屬層與該第二金屬層電性連接。The package structure of claim 1, wherein the wafer has an active surface and a plurality of contacts on the active surface, the first metal layer extends to the contacts, and the contacts The first metal layer is electrically connected to the third metal layer and the second metal layer. 如申請專利範圍第2項所述之封裝結構，其中該第一金屬層從該第一表面經由該晶片的一側延伸至該主動面。The package structure of claim 2, wherein the first metal layer extends from the first surface to the active surface via a side of the wafer. 如申請專利範圍第1項所述之封裝結構，其中部分未被該防銲層所包覆的該第一金屬層構成至少一第一接墊。The package structure of claim 1, wherein the first metal layer not covered by the solder resist layer constitutes at least one first pad. 如申請專利範圍第1項所述之封裝結構，其中部分未被該防銲層所包覆的該第二金屬層構成至少一第二接墊。The package structure of claim 1, wherein the second metal layer not covered by the solder resist layer constitutes at least one second pad. 一種封裝結構的製作方法，包括：提供一基板，該基板具有彼此相對的一第一表面與一第二表面及至少一連接該第一表面與該第二表面的貫孔，其中該基板上已形成有一位於該第一表面上且暴露出部分該第一表面的第一導電層及一位於該第二表面上的第二導電層；配置一晶片於該第一導電層所暴露出的部分該第一表面上；形成一圖案化電鍍罩幕於部分該第一導電層上、部分該第二導電層上及部分該晶片上；形成一金屬層於未配置該圖案化電鍍罩幕的該第一導電層與該第二導電層上，其中該金屬層覆蓋該貫孔的內壁及該第一導電層所暴露出的部分該第一表面上，該金屬層延伸至於該晶片上，且該晶片透過該金屬層與該第一導電層及該第二導電層電性連接；移除該圖案化電鍍罩幕及其下方之該第二導電層，以暴露出部分該第一表面、部分該第二表面及部分該晶片；以及形成一防銲層，以填充該貫孔且包覆該晶片及至少部分該金屬層。A method for fabricating a package structure includes: providing a substrate having a first surface and a second surface opposite to each other and at least one through hole connecting the first surface and the second surface, wherein the substrate has been Forming a first conductive layer on the first surface and exposing a portion of the first surface and a second conductive layer on the second surface; arranging a portion of the wafer exposed by the first conductive layer Forming a patterned plating mask on a portion of the first conductive layer, a portion of the second conductive layer, and a portion of the wafer; forming a metal layer on the first portion of the patterned plating mask a conductive layer and the second conductive layer, wherein the metal layer covers an inner wall of the through hole and a portion of the first surface exposed by the first conductive layer, the metal layer extends onto the wafer, and the metal layer The wafer is electrically connected to the first conductive layer and the second conductive layer through the metal layer; the patterned plating mask and the second conductive layer below the conductive layer are removed to expose a portion of the first surface, and the portion Second surface and Division of the wafer; and a solder resist layer is formed to fill the through hole and at least partially covering the chip and the metal layer. 如申請專利範圍第6項所述之封裝結構的製作方法，更包括：在配置該晶片於該第一導電層所暴露出的部分該第一表面上之後，形成一電鍍種子層於該第一導電層、該第一導電層所暴露出的該第一表面、該第二導電層、該貫孔內壁及該晶片上。The method for fabricating a package structure according to claim 6, further comprising: forming a plating seed layer on the first surface after arranging the wafer on a portion of the first surface exposed by the first conductive layer a conductive layer, the first surface exposed by the first conductive layer, the second conductive layer, the inner wall of the through hole, and the wafer. 如申請專利範圍第6項所述之封裝結構的製作方法，更包括：在移除該圖案化電鍍罩幕及其下方之該第二導電層之後，進行一蝕刻製程，以移除位於該圖案化電鍍罩幕下方的該電鍍種子層。The manufacturing method of the package structure of claim 6, further comprising: after removing the patterned plating mask and the second conductive layer below the etching layer, performing an etching process to remove the pattern The electroplated seed layer under the electroplated mask. 如申請專利範圍第6項所述之封裝結構的製作方法，其中形成該圖案化電鍍罩幕的步驟，包括：形成一電鍍罩幕於該第一導電層、該第一導電層所暴露出的該第一表面、該第二導電層及該晶片上；以及圖案化該電鍍罩幕以形成該圖案化電鍍罩幕。The method for fabricating a package structure according to claim 6, wherein the step of forming the patterned plating mask comprises: forming a plating mask on the first conductive layer and exposing the first conductive layer The first surface, the second conductive layer, and the wafer; and patterning the plating mask to form the patterned plating mask. 如申請專利範圍第6項所述之封裝結構的製作方法，其中該晶片具有一主動面與多個位於該主動面上的接點，該金屬層延伸至該些接點上，且該些接點透過該金屬層與該第一導電層與該第二導電層電性連接。The method for fabricating a package structure according to claim 6, wherein the wafer has an active surface and a plurality of contacts on the active surface, the metal layer extends to the contacts, and the connections A point is electrically connected to the first conductive layer and the second conductive layer through the metal layer. 如申請專利範圍第10項所述之封裝結構，其中該金屬層從該第一表面經由該晶片的一側延伸至該主動面。The package structure of claim 10, wherein the metal layer extends from the first surface to the active surface via one side of the wafer. 如申請專利範圍第6項所述之封裝結構的製作方法，其中部分未被該防銲層所包覆之該金屬層及其下方之部分該第一導電層構成至少一第一接墊。The method for fabricating a package structure according to claim 6, wherein a portion of the metal layer not covered by the solder resist layer and a portion of the underlying conductive layer constitute at least one first pad. 如申請專利範圍第6項所述之封裝結構的製作方法，其中部分未被該防銲層所包覆之該金屬層及其下方之部分該第二導電層構成至少一第二接墊。The method for fabricating a package structure according to claim 6, wherein a portion of the metal layer not covered by the solder resist layer and a portion of the second conductive layer below the second conductive layer constitute at least one second pad.
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US6590291B2 (en) * 2000-01-31 2003-07-08 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method therefor
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