TWI607681B - Fabrication method for circuit substrate - Google Patents

Description

Circuit board manufacturing method

The present invention relates to a circuit substrate and a method of fabricating the same, and more particularly to an embedded circuit substrate and a method of fabricating the same.

In the current chip packaging technology commonly used in the industry, the early stage is wire bonding, which is less able to meet the demand of high I/O pins. Therefore, in order to meet the demand for the number of high I/O pins, the industry has gradually adopted a flip chip bonding technology to electrically connect the wafer to the package substrate.

In order to save costs and increase the degree of integration of circuits on a package substrate, a technique of replacing a conventional package substrate with a buried circuit package substrate has been proposed. In the process of the existing buried circuit package substrate, conductive bumps are required to be formed on the pads of the buried circuit to serve as contacts for subsequent electrical connection with the wafer. In general, the method of manufacturing the buried circuit can be distinguished according to the fabrication of the circuit and the dielectric layer; and for the process of the circuit prior to the fabrication of the dielectric layer, if the copper foil is used as the plating conductive path and the buried circuit Located on the surface of the dielectric layer, there is often a copper foil covering it, so that the conductive bumps are electroplated over the pads of the buried circuit. Before, a patterned photoresist layer is formed on the metal layer to expose the region to be plated through the opening of the patterned photoresist layer, wherein the region to be plated is substantially above the pad of the buried circuit.

Specifically, the conductive bumps are formed by electroplating on the pads of the buried circuits, and the metal layers exposed by the openings are used as a basis for growth, and the pads of the buried circuits are not used as a growth basis. Therefore, whether the aforementioned opening can be completely aligned with the pad of the embedded circuit affects the alignment between the formed conductive bump and the pad of the buried circuit. During the formation of the patterned photoresist layer on the metal layer, the dielectric layer may be deformed, the target target or the allowable error of the lithography machine may be affected, so that the opening is seriously deviated from the buried line. Pads. Even if the conductive bumps formed subsequently cannot be completely aligned with the pads of the buried circuit, the production yield is low.

The invention provides a circuit substrate and a manufacturing method thereof, which can improve alignment precision of electroplating forming conductive bumps on a buried circuit layer, thereby improving production yield.

The invention provides a circuit substrate comprising a dielectric layer, a first patterned circuit layer and a meandering conductive bump. The dielectric layer has a first surface and a second surface opposite the first surface. The first patterned circuit layer is buried in the dielectric layer and exposed to the first surface. The first patterned circuit layer has at least one pad. The meandering conductive bump is bonded to the at least one pad. The bottom surface of the meandering conductive bump is bonded to the top surface of the at least one pad exposed to the first surface. The bottom surface completely overlaps the top surface.

In an embodiment of the invention, the circuit substrate further includes a second patterned circuit layer on the second surface.

The invention provides a method for manufacturing a circuit substrate, which comprises the following steps. First, a circuit substrate body is provided. The circuit substrate body includes a dielectric layer, a first patterned circuit layer, and a first metal layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first patterned circuit layer is buried in the dielectric layer and covered by the first metal layer covering the first surface. Next, a first photoresist layer is formed on the first surface to cover the first metal layer. Next, a first photoresist layer is formed on the first surface to cover the first metal layer. Next, the first photoresist layer is patterned to form at least one opening, and the at least one opening is aligned with the pad of the first patterned circuit layer, and a portion of the first metal layer is exposed. Next, a portion of the first metal layer located in the at least one opening is removed to expose the pads. Electroplating forms a doped conductive bump on the pad. Next, the first photoresist layer is removed. Thereafter, the first metal layer is removed.

In an embodiment of the invention, the circuit substrate body further includes a second metal layer and a second patterned circuit layer. The second patterned circuit layer is on the second surface, and the second metal layer covers the second surface and is located between the second patterned circuit layer and the dielectric layer. Before the step of patterning the first photoresist layer to form the at least one opening, the method further comprises: forming a second photoresist layer on the second surface to cover the second patterned circuit layer and not being patterned by the second patterned circuit layer A portion of the second metal layer covered.

In an embodiment of the invention, after the step of electroplating the doped conductive bumps on the pad, the method further comprises: removing the second photoresist layer and the portion not covered by the second patterned circuit layer The second metal layer.

Based on the above, the present invention will first be located in the first photoresist layer covering the first metal layer to form an opening corresponding to the pad of the first patterned circuit layer (ie, the buried wiring layer). A portion of the first metal layer within the opening is removed to completely expose the top surface of the pads of the first patterned circuit layer. After that, in the process of forming the conductive bumps on the pads by electroplating, the dome-shaped conductive bumps are based on the top surface of the pads, so that the bottom surface of the conductive bumps can be bonded to the corresponding pads. The top surface, and the bottom surface of the meandering conductive bumps will completely overlap the top surface of the corresponding pads without offset. Therefore, the method for fabricating the circuit substrate of the present invention can effectively improve the alignment accuracy of the conductive bumps formed on the buried wiring layer by plating, so as to improve the production yield of the circuit substrate.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Line substrate body

100‧‧‧Line substrate

110‧‧‧ dielectric layer

111‧‧‧ first surface

112‧‧‧ second surface

120‧‧‧First patterned circuit layer

120a, 121a‧‧‧ top

121‧‧‧ pads

121b‧‧‧ side surface

130‧‧‧First metal layer

140‧‧‧Second metal layer

150‧‧‧Second patterned circuit layer

160‧‧‧First photoresist layer

161‧‧‧Opening

161a‧‧‧ inner wall

170‧‧‧second photoresist layer

180‧‧‧蕈like conductive bumps

181‧‧‧ bottom

1A to 1G are schematic diagrams showing a manufacturing process of a circuit substrate according to an embodiment of the present invention.

1A to 1G are schematic diagrams showing a manufacturing process of a circuit substrate according to an embodiment of the present invention. Referring to FIG. 1A, the circuit substrate body 10 is provided, for example, a single-layer buried circuit substrate body, but the invention is not limited thereto. In detail, the circuit substrate body 10 includes a dielectric layer 110, a first patterned wiring layer 120, a first metal layer 130, a second metal layer 140, and a second patterned wiring layer 150, wherein the dielectric layer 110 has a first surface 111 and is opposite to the first The second surface 112 of the surface 111. The first patterned circuit layer 120 is buried in the dielectric layer 110 having a top surface 120a that is flush with the first surface 111 and covered by the first metal layer 130 overlying the first surface 111. That is, the first metal layer 130 is connected to the top surface 120a of the first patterned wiring layer 120.

In the embodiment, the first patterned circuit layer 120 has a plurality of pads 121 (three are schematically shown in the drawing). Similarly, the top surface 121a of each pad 121 is also flush with the first surface 111. . On the other hand, the second patterned circuit layer 150 is located on the second surface 112, and the second metal layer 140 covers the second surface 112 and is located between the second patterned circuit layer 150 and the dielectric layer 110. That is, the second metal layer 140 and the second patterned wiring layer 150 are sequentially stacked on the second surface 112 of the dielectric layer 110, wherein the second patterned wiring layer 150 exposes a portion of the second metal layer 140. Generally, the first patterned circuit layer 120, the first metal layer 130, the second metal layer 140, and the second patterned circuit layer 150 may be made of the same material, such as copper or other suitable conductive metal, or conductive. The alloy of metal is not limited in the present invention.

Next, referring to FIG. 1B, a first photoresist layer 160 is formed on the first metal layer 130 and a second photoresist layer 170 is formed on the second metal layer 140 by a lamination method, wherein the second photoresist is formed. The layer 170 covers the second patterned wiring layer 150 and a portion of the second metal layer 140 that is not covered by the second patterned wiring layer 150. Here, the first photoresist layer 160 and the second photoresist layer 170 are, for example, dry film photoresists. (dry film photoresist), but the present invention does not limit the manner in which the dry film photoresist is formed on the first surface 111 and the second surface 112 by pressing. In other embodiments, the first photoresist layer 160 and the second photoresist layer 170 may also be formed by inkjet, printing, or coating.

Next, referring to FIG. 1C, the first photoresist layer 160 is patterned to form a plurality of openings 161 (three are schematically shown in the drawing), and each of the openings 161 is aligned with the corresponding pad 121 and exposed. A portion of the first metal layer 130 of the corresponding pad 121 is covered. In detail, when the first photoresist layer 160 is patterned to form the openings 161, the cross-sectional area of each of the openings 161 is larger than the area of the top surface 121a of the corresponding pad 121. That is, the pads 121 located in the respective openings 161 are surrounded by the corresponding openings 161. To be different, when the first photoresist layer 160 is patterned to form the openings 161, a space is required between the inner wall surface 161a of each of the openings 161 and the side surface 121b of the corresponding pad 121.

Next, referring to FIG. 1D, a portion of the first metal layer 130 exposed by each of the openings 161 is removed to expose the top surface 121a of the corresponding pad 121. Since the present embodiment can be etched by flash etching, when the first metal layer 130 located in each of the openings 161 is removed, the top surface 121a of each of the pads 121 is substantially flush with the first surface 111. Or it is slightly lower than the first surface 111 (not shown).

Next, referring to FIG. 1E, a conductive conductive bump 180 is formed on each of the pads 121 by electroplating. Since the inner wall surface 161a of each of the openings 161 and the side surface 121b of the corresponding pad 121 are spaced apart, the molded surface is formed. Each of the braided conductive bumps 180 will not come into contact with the inner wall surface 161a of the corresponding opening 161. on the other hand, During the process of forming the conductive bumps 180 on the pads 121, the respective conductive bumps 180 are based on the top surface 121a of the corresponding pads 121, so that the respective conductive bumps can be formed. The bottom surface 181 of the 180 is bonded to the corresponding surface 121 of the first surface 111, and the bottom surface 181 of each of the conductive bumps 180 completely overlaps the top surface 121a of the corresponding pad 121 without An offset is generated.

Next, referring to FIG. 1F, the first photoresist layer 160 and the second photoresist layer 170 are removed. Thereafter, referring to FIG. 1G, the first metal layer 130 and a portion of the second metal layer 140 not covered by the second patterned circuit layer 150 are removed, so that there is a portion covered by the second patterned circuit layer 150. The second metal layer 140 is retained. So far, the circuit substrate 100 of the present embodiment has been substantially completed.

In summary, the present invention will be located first after the first photoresist layer covering the first metal layer forms an opening corresponding to the pad of the first patterned circuit layer (ie, the buried circuit layer). A portion of the first metal layer within the aforementioned opening is removed to completely expose the top surface of the pad of the first patterned wiring layer. After that, in the process of forming the conductive bumps on the pads by electroplating, the dome-shaped conductive bumps are based on the top surface of the pads, so that the bottom surface of the conductive bumps can be bonded to the corresponding pads. The top surface, and the bottom surface of the meandering conductive bumps will completely overlap the top surface of the corresponding pads without offset. Therefore, the method for fabricating the circuit substrate of the present invention can effectively improve the alignment accuracy of the conductive bumps formed on the buried wiring layer by plating, so as to improve the production yield of the circuit substrate.

Although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. The scope of the present invention is defined by the scope of the appended claims, which are defined by the scope of the appended claims, without departing from the spirit and scope of the invention. quasi.

100‧‧‧Line substrate

110‧‧‧ dielectric layer

112‧‧‧ second surface

120‧‧‧First patterned circuit layer

120a, 121a‧‧‧ top

121‧‧‧ pads

140‧‧‧Second metal layer

150‧‧‧Second patterned circuit layer

180‧‧‧蕈like conductive bumps

181‧‧‧ bottom

Claims (3)

A circuit substrate manufacturing method includes: providing a circuit substrate body, the circuit substrate body comprising a dielectric layer, a first patterned circuit layer and a first metal layer, wherein the dielectric layer has a first surface and The first patterned circuit layer is buried in the dielectric layer and covered by the first metal layer covering the first surface with respect to a second surface of the first surface; forming a first photoresist layer And covering the first metal layer on the first surface; patterning the first photoresist layer to form at least one opening, the at least one opening being aligned with a pad of the first patterned circuit layer, and Exposing a portion of the first metal layer; removing a portion of the first metal layer located in the at least one opening to expose the pad, and having a cross-sectional area of the at least one opening greater than the at least one opening An area of a top surface of the pad; electroplating to form a meandering conductive bump on the pad; removing the first photoresist layer; and removing the first metal layer. The method of fabricating a circuit substrate according to claim 1, wherein the circuit substrate body further comprises a second metal layer and a second patterned circuit layer, wherein the second patterned circuit layer is located on the second surface. The second metal layer covers the second surface and is located between the second patterned circuit layer and the dielectric layer, before the step of patterning the first photoresist layer to form the at least one opening The method includes forming a second photoresist layer on the second surface to cover the second patterned circuit layer and a portion of the second metal layer not covered by the second patterned circuit layer. The method of manufacturing the circuit substrate of claim 1, wherein after the step of forming the conductive bump on the pad by electroplating, the method further comprises: removing the second photoresist layer; A portion of the second metal layer covered by the second patterned circuit layer.