TW201611695A - Coreless package substrate and method for manufacturing the same - Google Patents

Abstract

A method for forming a coreless package substrate is provided. First, a first patterned metal layer and a dielectric layer are sequentially formed on a carrier, in which the first patterned metal layer has a sacrifice area and a plurality of conductive posts. Then, the dielectric layer is planarized to expose the first patterned metal layer, and the first patterned metal layer is micro-etched, such that the dielectric protrudes the first patterned metal layer. Then, in order an etching stop layer and a first wiring built-up layer is formed on the sacrifice area, and a second patterned metal layer is formed on the etching stop layer and the first patterned metal layer. Finally, the carrier and the sacrifice region are removed to form a cavity for placing a die, and the etching stop layer is removed.

Description

Coreless package substrate and manufacturing method thereof

The present invention relates to a coreless package substrate and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the requirements of high integration and miniaturization of semiconductor components, the requirements for semiconductor package structures are becoming higher and higher. For example, in the package structure, the critical dimension of the line width and the line pitch of the package substrate is required to be smaller and smaller, and the overall thickness of the package structure is required to be as small as possible.

The conventional semiconductor package structure is to adhere a semiconductor wafer to the top surface of the substrate for wire bonding or Flip Chip packaging. The flip chip technology is characterized in that the electrical connection between the semiconductor wafer and the package substrate is directly solder bump instead of the general gold wire. The advantage of the flip chip technology is that the electrical contact density can be improved and the package can be reduced. Component size; at the same time, this kind of flip chip technology does not need to use a long length of gold wire, but can reduce impedance and noise, improve electrical performance to meet the needs of high-frequency signal transmission.

In order to further improve the various characteristics of the semiconductor package structure, the related fields are not exhaustively developed. How to provide a semiconductor package structure with better characteristics is one of the current important research and development topics, and it has become an urgent need for improvement in related fields.

The invention provides a coreless package substrate and a manufacturing method thereof, and the bump of the electrical connection wafer is higher than the connected or corresponding circuit layer by a special process design, and even higher than the dielectric layer surrounding the bump. The electrical connection quality between the packaged wafer and the package substrate is better.

According to an embodiment of the present invention, a method of manufacturing a coreless package substrate includes the following steps. First, a first patterned metal layer is formed on the carrier substrate, wherein the first patterned metal layer has a sacrificial block and a plurality of conductor posts. Next, a dielectric layer is formed on the carrier substrate and the first patterned metal layer, and the dielectric layer is planarized and the first patterned metal layer is exposed. The first patterned metal layer is then thinned such that the dielectric layer protrudes out of the first patterned metal layer. Next, an etch stop layer is formed on the sacrificial block, and a second patterned metal layer is formed on the etch stop layer, the dielectric layer, and the first patterned metal layer. Next, a first build-up structure is formed on the second patterned metal layer, the etch stop layer, the dielectric layer, and the first patterned metal layer. Finally, the carrier substrate is removed, the sacrificial block of the first patterned metal layer is removed, and a crystallized recess is formed, and the etch stop layer is removed.

In one or more embodiments of the present invention, the method for manufacturing a coreless package substrate further includes removing a portion of a surface thickness of the first dielectric layer, such that A second patterned metal layer in the patterned recess protrudes from the first dielectric layer and forms a plurality of bumps.

In one or more embodiments of the present invention, the first build-up structure includes at least one first dielectric layer, a first build-up wiring layer disposed on the first dielectric layer, and a first dielectric layer And a plurality of first conductive blind vias, wherein a portion of the first conductive vias are electrically connected to the second patterned metal layer and the first build-up wiring layer.

According to another embodiment of the present invention, a method of fabricating a stacked package structure includes the following steps. First, the aforementioned coreless package substrate is provided. Next, the wafer is placed in the crystallized recess and electrically connected to the bump. Then, filling the insulating material in the gap between the crystallizing recess and the wafer to fix the wafer to the coreless package substrate to form the first package structure. Finally, the second package structure is disposed on a side of the first package structure where the wafer is disposed, and the second package structure is electrically connected to the conductor post of the first package structure.

According to still another embodiment of the present invention, a method of fabricating a package structure includes the following steps. First, the aforementioned coreless package substrate is provided. Next, the wafer is placed in the crystallized recess and electrically connected to the bump. Then, filling the insulating material in the gap between the crystallizing recess and the wafer to fix the wafer to the coreless package substrate. Finally, a second build-up structure is formed on the side of the coreless package substrate on which the wafer is disposed, wherein the second build-up structure comprises at least one second dielectric layer and a second buildup layer formed on the second dielectric layer And a plurality of second conductive blind vias formed in the second dielectric layer, wherein a portion of the second conductive vias are electrically connected to the conductive pillars and the second build-up wiring layer.

According to still another embodiment of the present invention, a coreless package substrate includes a dielectric layer, a first dielectric layer, a patterned metal layer, a plurality of conductive pillars, a first build-up wiring layer, and a plurality of first conductive blind vias. The dielectric layer has a crystal opening and a plurality of through holes. The first dielectric layer is disposed on the lower surface of the dielectric layer and forms a crystallized recess with the crystallized opening. The patterned metal layer has a circuit layer buried in the first dielectric layer and partially disposed on the lower surface of the dielectric layer, and a plurality of bumps buried and exposed to a portion of the first dielectric layer constituting the crystallized recess. The conductor post is disposed in the through hole and electrically connected to the circuit layer, wherein the thickness of the circuit layer disposed on the lower surface of the conductor post and the thickness of the bump disposed on the crystallized groove are greater than the circuit layer disposed on the lower surface of the dielectric layer The thickness. The first build-up circuit layer is disposed on a lower surface of the first dielectric layer. The plurality of first conductive blind vias are disposed in the first dielectric layer, and the first conductive vias are electrically connected to the first build-up wiring layer and the circuit layer or the bumps. The first dielectric layer, the first build-up circuit layer, and the plurality of first conductive blind holes constitute a first build-up structure or a minimum build-up unit of the first build-up structure.

In one or more embodiments of the present invention, the bumps protrude from the first dielectric layer surrounding the bumps.

According to still another embodiment of the present invention, a stacked package structure includes the foregoing coreless package substrate, a wafer, an insulating material, and a second package structure. The wafer is disposed in the crystallized recess and electrically connected to the bump. The insulating material is disposed in the gap between the crystallizing recess and the wafer to fix the wafer to the coreless package substrate to form the first package structure. The second package structure is disposed on a side of the first package structure on which the wafer is disposed, and is electrically connected to the conductor post.

According to still another embodiment of the present invention, a package structure, a chip set In the crystallized recess and electrically connected to the bump. The insulating material is disposed in the gap between the crystallizing recess and the wafer to fix the wafer to the coreless package substrate. The second build-up structure is disposed on a side of the coreless package substrate on which the wafer is disposed, wherein the second build-up structure comprises at least one second dielectric layer, a second build-up circuit layer disposed on the second dielectric layer, and And a plurality of second conductive blind vias disposed in the second dielectric layer, wherein a portion of the second conductive vias are electrically connected to the conductive pillars and the second build-up wiring layer.

The above embodiments of the present invention provide better electrical connection quality between the wafer and the bumps by making the height of the bumps higher than the connected or corresponding wiring layers, even higher than the dielectric layers surrounding the bumps.

100‧‧‧Without core layer package substrate

102‧‧‧ crystallized groove

110‧‧‧Loading substrate

120, 160‧‧‧ patterned metal layer

122‧‧‧ Sacrifice block

124‧‧‧Conductor column

130‧‧‧Dielectric layer

132‧‧‧through holes

134‧‧‧ crystal opening

140‧‧‧ Conductive seed layer

150‧‧‧etch stop layer

162‧‧‧Bumps

164‧‧‧Line layer

170‧‧‧Surface treatment layer

200‧‧‧First buildup structure

210, 214‧‧‧ first dielectric layer

212‧‧‧Blind hole

220, 224‧‧‧ first layer of added circuit

230, 234‧‧‧ first conductive blind hole

300‧‧‧Second layered structure

310‧‧‧Second dielectric layer

320‧‧‧Second layered circuit layer

330‧‧‧Second conductive blind hole

600‧‧‧Stacked package structure

610‧‧‧Second package structure

611‧‧‧ solder balls

700‧‧‧Package structure

810‧‧‧ wafer

820‧‧‧Insulation materials

830, 840‧‧ ‧ insulating protective layer

920, 930, 940, 950‧‧ ‧ resistance layer

922, 942‧‧‧ openings

932‧‧‧ patterned open area

T ₁ , T ₂ ‧‧‧ thickness

1A to 1R are cross-sectional views showing respective steps of a process for manufacturing a coreless package substrate according to an embodiment of the present invention.

1F' is a cross-sectional view showing a step of a process of a coreless package substrate in accordance with another embodiment of the present invention.

1R' is a cross-sectional view showing a step of a process of a coreless package substrate according to still another embodiment of the present invention.

2A and 2B are cross-sectional views showing various steps of a process of a stacked package structure in accordance with an embodiment of the present invention.

2B' is a cross-sectional view showing one step of the process of the package structure in accordance with another embodiment of the present invention.

The various embodiments of the present invention are disclosed in the drawings, and in the written description However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

Different embodiments of the present invention provide a method of manufacturing a coreless package substrate. Since the coreless package substrate does not have a core layer, the thickness of the coreless package substrate is effectively reduced. The coreless package substrate of the different embodiments of the present invention additionally has other advantages over the prior art, which will be separately described below.

1A to 1R are cross-sectional views showing respective steps of a process for manufacturing the coreless package substrate 100 according to an embodiment of the present invention. As shown in FIG. 1A, the patterned metal layer 120 is formed on the carrier substrate 110, wherein the patterned metal layer 120 includes a sacrificial block 122 and a plurality of conductor posts 124.

Specifically, the carrier substrate 110 is first provided. The carrier substrate 110 may include a substrate layer (not shown) and a conductive seed layer (not shown), and the conductive seed layer is disposed on the substrate layer, but is not limited thereto. In other embodiments, the carrier substrate 110 can be a single piece of metal.

Next, a resist layer (not shown) is formed on the carrier substrate 110, and the resist layer is patterned to form a patterned opening region (not shown). Then, the patterned metal layer 120 is formed on the carrier substrate 110 and the patterned opening region, and includes the sacrificial block 122 and the conductor post 124. Finally, remove the barrier layer.

The aforementioned resist layer may be a dry film or a wet film (Wet Film). The material of the patterned metal layer 120 may be, for example, copper. The method of forming the foregoing patterned metal layer 120 may be electroplating.

It should be noted that in other embodiments, other fabrication processes may be used to form the patterned metal layer 120. For example, a preliminary metal layer (not shown) may be formed on the carrier substrate 110, and the preliminary metal layer may be etched to form the patterned metal layer 120.

It should be understood that the embodiments of the patterned metal layer 120 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select the patterned metal layer 120 according to actual needs. Implementation.

As shown in FIG. 1B, a dielectric layer 130 is formed on the carrier substrate 110 and the patterned metal layer 120. The material of the dielectric layer may comprise a resin and a glass fiber. The resin may be a phenol resin, an epoxy resin, a polyamidene resin or a polytetrafluoroethylene. The method of forming the dielectric layer can be, for example, lamination.

As depicted in FIG. 1C, the dielectric layer 130 is planarized and the patterned metal layer 120 is exposed. The method of planarization may be a method such as brushing or chemical-mechanical polishing (CMP).

Next, as depicted in FIG. 1D, the patterned metal layer 120 may be thinned in a micro-etching manner such that the dielectric layer 130 protrudes from the patterned metal layer 120.

As shown in FIG. 1E, a conductive seed layer 140 is formed on the dielectric layer 130. The material of the conductive seed layer 140 may be a metal such as copper. The conductive seed layer 140 can be formed by plating, such as electroless plating or chemical vapor deposition (CVD), physical vapor deposition (PVD) such as sputtering or evaporation. Wait.

As shown in FIG. 1F and FIG. 1G, an etch stop layer 150 is formed on the sacrificial block 122.

As shown in FIG. 1F , a resist layer 920 is formed on the conductive seed layer 140 and the patterned metal layer 120 , and the resist layer 920 forms an opening 922 at the sacrificial block 122 .

Next, an etch stop layer 150 is formed on the sacrificial block 122 by electroplating using the conductive seed layer 140 as a conductive path. The material of the etch stop layer 150 may be a metal such as nickel, and the material of the etch stop layer 150 is different from the material of the patterned metal layer 120. In addition, in other embodiments, the conductive seed layer 140 may not be formed, and the etching stop layer 150 may be formed by physical vapor deposition or the like.

Then, as shown in FIG. 1G, the resist layer 920 is removed.

It is noted that, as shown in FIG. 1F, since the size of the opening 922 is smaller than the size of the sacrificial block 122, a portion of the resist layer 920 covers the conductive seed layer 140 above the sacrificial block 122, so etching The stop layer 150 does not completely cover the conductive seed layer 140 above the sacrificial block 122, which would result in a difference in subsequent processes.

FIG. 1F is a cross-sectional view showing a step of a process of the coreless package substrate 100 according to another embodiment of the present invention. As shown in FIG. 1F′, since the size of the opening 922 is larger than the size of the sacrificial block 122, the bare portion of the resist layer 920 is located on the conductive seed layer 140 adjacent to the dielectric layer of the sacrificial block 122, and thus the portion A portion of the etch stop layer 150 will be formed on the conductive seed layer 140 on the dielectric layer adjacent to the sacrificial block 122.

As shown in FIG. 1H, FIG. 1I, and FIG. 1J, another patterned metal layer 160 is formed on the etch stop layer 150, the conductive seed layer 140, and the patterned metal layer 120.

As shown in FIG. 1H, a resist layer 930 is formed on the etch stop layer 150, the conductive seed layer 140, and the patterned metal layer 120, and the resist layer 930 is formed into a patterned opening region 932.

Next, as shown in FIG. 1I, the patterned metal layer 160 is formed by electroplating on the etch stop layer 150, the conductive seed layer 140, and the patterned metal layer 120 exposed by the patterned opening region 932.

Finally, as shown in FIG. 1J, the resist layer 930 is removed.

It is noted that, due to the embodiment from FIG. 1F, as illustrated in FIG. 1J, the etch stop layer 150 does not completely cover the conductive seed layer 140 above the sacrificial block 122, in order to avoid subsequent etching processes. (See FIG. 1Q), because the gap covered by the etch stop layer 150 on the inner edge of the crystallized recess 102 formed after the sacrificial block 122 is removed is not protected by the etch stop layer 150 and damages the crystallized recess. The electrical connection structure between the patterned metal layer 160 in the 102 and the patterned metal layer 160 outside the crystallized recess 102 (ie, the wiring layer, not shown), the patterned metal layer in the crystal recess 102 The patterned metal layer 160 outside the crystallized recess 102 has no electrical connection structure.

If in the embodiment of FIG. 1F', since the etch stop layer 150 completely covers the conductive seed layer 140 above the sacrificial block 122, the etch stop layer 150 is formed in a subsequent etching process (see FIG. 1Q). The patterned metal layer 160 will be protected from etching. Thus, the crystal recess 102 An electrical connection structure may be disposed between the patterned metal layer 160 and the patterned metal layer 160 outside the crystallized recess 102.

As shown in FIG. 1K, a first dielectric layer 210 is formed on the etch stop layer 150, the conductive seed layer 140, and the patterned metal layers 120, 160.

As shown in FIG. 1L, a plurality of blind vias 212 are formed in the first dielectric layer 210. The blind via 212 can be formed by laser ablation of the first dielectric layer 210.

Next, as shown in FIG. 1M, the first build-up wiring layer 220 and the plurality of first conductive blind vias 230 are formed by electroplating, wherein the first build-up wiring layer 220 is disposed on the first dielectric layer 210, and the first conductive layer The blind vias 230 are formed in the first dielectric layer 210 and electrically connected to the patterned metal layer 160 and the first build-up wiring layer 220. The first dielectric layer 210, the first build-up wiring layer 220, and the first conductive blind via 230 constitute a minimum build-up unit of the first build-up structure 200 or the first build-up structure 200.

As shown in FIG. 1N, at least another first dielectric layer 214 may be selectively formed on the first dielectric layer 210 and the first build-up wiring layer 220 to form another first build-up wiring layer 224. On the first dielectric layer 214, a plurality of first conductive vias 234 are formed in the first dielectric layer 214 and electrically connected to the first build-up wiring layer 220 and the first build-up wiring layer 224.

Next, an insulating protective layer 830 is formed on the first dielectric layer 214 and the first build-up wiring layer 224 to protect the first build-up wiring layer 224. The material of the insulating protective layer 830 may be a solder resist material or a resin such as an epoxy resin. The method of forming the insulating protective layer 830 may be a method of lamination, printing, or coating.

The carrier substrate 110 is removed as shown in FIGS. 1N and 10O. The method of removing the carrier substrate 110 may be a method of detaching, peeling, or etching.

As depicted in FIG. 1P and FIG. 1Q, the sacrificial block 122 of the patterned metal layer 120 is removed and a crystallized recess 102 is formed.

As shown in FIG. 1P, a resist layer 940 is formed on the patterned metal layer 120 and the dielectric layer 130, and a resist layer 950 is formed on the insulating protective layer 830 and the first build-up wiring layer 224. An opening 942 is then formed in the resist layer 940 to expose the sacrificial block 122.

Next, as depicted in FIG. 1Q, the sacrificial block 122 of the patterned metal layer 120 is removed and a crystallized recess 102 is formed. The method of removing the sacrificial block 122 can be an etch and the etch will stop at the etch stop layer 150.

Finally, as shown in FIG. 1R, the inverted coreless package substrate 100 is removed, and the resist layers 940, 950 and the etch stop layer 150 are removed.

1R' is a cross-sectional view showing a step of a process of the coreless package substrate 100 according to still another embodiment of the present invention. As shown in FIG. 1R', laser ablation may be used to remove a portion of the surface thickness of the first dielectric layer 210 in the crystallized recess 102, such that the patterned metal layer 160 located in the crystallized recess 102 protrudes. A plurality of bumps 162 are formed on the first dielectric layer 210.

The core-free package substrate 100 may further form a surface treatment layer 170 on the patterned metal layer 160 exposed on the first dielectric layer 210. The material of the surface treatment layer 170 may be tin, silver, nickel, gold, chromium/titanium, Nickel/gold, nickel/palladium, nickel/palladium/gold or organic solder mask (OSP).

It should be understood that the embodiments of the resistive layer described above are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select the embodiment of the resistive layer according to actual needs.

The package structure of the two-application coreless package substrate 100 is disclosed below.

2A and 2B are cross-sectional views showing various steps of the process of the stacked package structure 600 in accordance with an embodiment of the present invention. The coreless package substrate 100 can be applied to a package on package (PoP). As shown in FIG. 2A, the coreless package substrate 100 (as shown in FIG. 1R') is first provided, and the wafer 810 is placed in the crystallized recess 102, and can be soldered or the like. Block 162 forms an electrical connection. Next, a non-conductive paste 820 is filled in the gap between the crystallized recess 102 and the wafer. Then, the insulating material 820 is cured by heating or the like to fix the wafer 810 in the coreless package substrate 100 to form a first package structure.

As shown in FIG. 2B, the second package structure 610 (the internal structure is omitted) and the coreless package substrate 100 and the packaged wafer 810 are used, wherein the second package structure 610 can be electrically connected by a plurality of solder balls 611. On the conductor post 124.

As shown in FIG. 1J, since the dielectric layer 130 protrudes from the patterned metal layer 120, the bottom of the patterned metal layer 160 on the dielectric layer 130 will be higher than the pattern on the patterned metal layer 120. The bottom of the metal layer 160. Therefore, as shown in FIG. 1R', the height of the bump 162 will be higher than the bottom of the dielectric layer 130, and the wiring layer 164 of the patterned metal layer 160 will be disposed on the lower surface of the dielectric layer 130, thus being convex. The height of the block 162 will be higher than the wiring layer 164 (ie, the thickness T _{1 of the} bump 162 is greater than the thickness T ₂ of the wiring layer 164 disposed on the lower surface of the dielectric layer 130). The bump 162 is disposed at a higher height than the first dielectric layer 210, and the wiring layer 164 is disposed in the first dielectric layer 210. Therefore, the wiring layer 164 is compared to the bump 162 protruding from the first dielectric layer 210. It is buried in the first dielectric layer 210. Thus, the bumps 162 are clearly spaced from the arrangement of the wiring layer 164, and thus will not interfere with each other when the core-free package substrate 100 operates. In addition, since the bump 162 protrudes from the wiring layer 164 and the first dielectric layer 210, the electrical connection quality of the wafer 810 and the bump 162 will be better.

It is particularly noted that the effect of the bumps 162 protruding from the wiring layer 164 and the first dielectric layer 210 to produce a preferred electrical connection quality is particularly important in embodiments having bumps 162 having fine pitch. obvious. Further, the thickness of the bumps 162 and the thickness T ₁ of the lower surface of the wiring layer 164 of dielectric layer 130 in thickness between the ₂ T may be determined by FIG. 1C and FIG. 1D first thinning process depicted.

In addition, the coreless package substrate 100 is connected to the solder balls 611 using the conductor posts 124 as compared with the conventional lower substrate by solder balls connected to the solder balls 611 of the second package structure 610. In this way, the solder ball of the conventional first package structure and the solder ball 611 can be prevented from being simultaneously melted during reflow, so that the solder structure of the conventional first package structure and the solder ball 611 of the second package structure 610 are integrated. The width of the structure becomes larger. Thus, the use of the coreless encapsulation substrate 100 will achieve the need to achieve a fine pitch.

In addition, since the dielectric layer 130 surrounding the wafer 810 is formed in the early process of the core-free package substrate 100, the shape of the core-free package substrate 100 will be fixed by the dielectric layer 130, and the temperature difference due to the process process is reduced. And the warpage of the core-free package substrate 100 is generated, thereby avoiding The solder-free ball 611 causes warpage and the like due to the difference in thermal expansion degree of the upper and lower package structures, and further causes the stacked package structure 600 to fail to operate normally.

A package structure 700 of another embodiment will be discussed below. As shown in FIG. 2A, the first package structure described above is first provided. Next, as shown in FIG. 2B′, a cross-sectional view showing one step of the process of the package structure 700 according to another embodiment of the present invention is performed, and the second build-up structure 300 is formed on the coreless package substrate 100. One side of the 810, wherein the second build-up structure 300 includes a second dielectric layer 310, a second build-up wiring layer 320 disposed on the second dielectric layer 310, and a plurality of layers formed in the second dielectric layer 310. The second conductive vias 330 are electrically connected to the conductive pillars 124 and the second build-up wiring layer 320. Finally, an insulating protective layer 840 is formed on the second dielectric layer 310 and the second build-up wiring layer 320 to protect the second build-up wiring layer 320.

As shown in FIG. 1R, a coreless package substrate 100 can be fabricated by the processes illustrated in FIGS. 1A-1R. The coreless package substrate 100 includes a dielectric layer 130, a first dielectric layer 210, a patterned metal layer 160, and a plurality of conductor pillars 124. The dielectric layer 130 has a plurality of through holes 132 and a crystal opening 134. A first dielectric layer 210 is disposed on the lower surface of the dielectric layer 130 and forms a crystallized recess 102 with the crystal opening 134. The patterned metal layer 160 has a circuit layer 164 embedded in the first dielectric layer 210 and partially disposed on the lower surface of the dielectric layer 130, and a portion of the first dielectric layer 210 embedded and exposed in the crystal forming recess. A plurality of bumps 162. The plurality of conductor posts 124 are disposed in the through holes 132 and electrically connected to the circuit layer 164. The thickness T ₁ of the circuit layer 164 and the bumps 162 disposed on the lower surface of the conductor post 124 is greater than the lower surface of the dielectric layer 130. The thickness of the circuit layer 164 is T ₂ .

As shown in FIG. 1R', the coreless package substrate 100 in the 1R' diagram is substantially the same as the coreless package substrate 100 in the 1Rth diagram, and the main difference is that the bump 162 protrudes from the first Dielectric layer 210. The coreless package substrate 100 further includes a first build-up layer 220 and a plurality of first conductive vias 230. The first build-up circuit layer 220 is disposed on a lower surface of the first dielectric layer 210. A plurality of first conductive vias 230 are disposed in the first dielectric layer 210 , and a portion of the first conductive vias 230 are electrically connected to the first build-up wiring layer 220 and the circuit layer 164 . The first dielectric layer 210, the first build-up wiring layer 220, and the first conductive blind vias 230 constitute the first build-up structure 200.

As shown in FIG. 2B, a stacked package structure 600 can be fabricated by the processes illustrated in FIGS. 2A and 2B. The stacked package structure 600 includes the aforementioned coreless package substrate 100, the wafer 810, the insulating material 820, and the second package structure 610. The wafer 810 is disposed in the crystallized recess 102 and electrically connected to the bump 162. The insulating material 820 is disposed in the gap between the crystallized recess 102 and the wafer 810 to fix the wafer 810 to the coreless package substrate 100 to form a first package structure. The second package structure 610 is disposed on a side of the first package structure on which the wafer is disposed, and is electrically connected to the conductor post 124 of the first package structure by a plurality of solder balls 611.

As shown in Fig. 2B', another package structure 700 can be fabricated by the processes illustrated in Figs. 2A and 2B'. The package structure 700 includes the aforementioned coreless package substrate 100, wafer 810, insulating material 820, and second build-up structure 300. The wafer 810 is disposed in the crystallized recess 102 and electrically connected to the bump 162. The insulating material 820 is disposed on the crystallized recess 102 and the wafer In the gap between the 810, the wafer 810 is fixed to the coreless package substrate 100. The second build-up structure 300 is disposed on a side of the core-free package substrate 100 on which the wafer 810 is disposed. The second build-up structure 300 includes at least one second dielectric layer 310 and is disposed on the second dielectric layer 310. The second conductive vias 320 and the plurality of second conductive vias 330 are disposed in the second dielectric layer 310. The second conductive vias 330 are electrically connected to the conductive pillars 124 and the second build-up wiring layers 320.

The above embodiment of the present invention electrically connects the wafer 810 and the bump 162 by making the bump 162 higher than the wiring layer 164 and even protruding the bump 162 from the surrounding first dielectric layer 210. Better quality.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Without core layer package substrate

102‧‧‧ crystallized groove

120‧‧‧ patterned metal layer

124‧‧‧Conductor column

130‧‧‧Dielectric layer

132‧‧‧through holes

134‧‧‧ crystal opening

160‧‧‧ patterned metal layer

162‧‧‧Bumps

164‧‧‧Line layer

170‧‧‧Surface treatment layer

200‧‧‧First buildup structure

210, 214‧‧‧ first dielectric layer

212‧‧‧Blind hole

220, 224‧‧‧ first layer of added circuit

230, 234‧‧‧ first conductive blind hole

Claims (8)

A method for manufacturing a coreless package substrate, comprising: forming a first patterned metal layer on a carrier substrate, wherein the first patterned metal layer has a sacrificial block and a plurality of conductor posts; forming a dielectric layer Overlying the carrier substrate and the first patterned metal layer; planarizing the dielectric layer and exposing the first patterned metal layer; thinning the first patterned metal layer to cause the dielectric layer to protrude from the first a patterned metal layer; forming an etch stop layer on the sacrificial block; forming a second patterned metal layer on the etch stop layer, the dielectric layer, and the first patterned metal layer; forming a first a build-up structure on the second patterned metal layer, the etch stop layer, the dielectric layer, and the first patterned metal layer; removing the carrier substrate; removing the first patterned metal layer Sacrificing the block and forming a crystallized recess; and removing the etch stop layer; wherein the first build-up structure comprises at least one first dielectric layer, and one of the first build-up layers disposed on the first dielectric layer a circuit layer and a plurality of layers formed in the first dielectric layer Conductive vias, wherein the first portion of the plurality of electrically conductive vias of the patterned second layer and the first metal wiring layer by layer connection. The manufacturing method according to claim 1, further comprising: Removing a portion of the surface thickness of the first dielectric layer such that the second patterned metal layer in the patterned recess protrudes from the first dielectric layer and forms a plurality of bumps. A manufacturing method of a stacked package structure, comprising: providing a coreless package substrate manufactured by using the manufacturing method according to claim 1 or 2; placing a wafer in the crystallized groove and forming with the bump Electrically connecting; filling an insulating material in the gap between the crystallizing recess and the wafer, fixing the wafer to the coreless package substrate to form a first package structure; and providing a second package structure The first package structure is provided with one side of the chip, and the second package structure is electrically connected to the conductor posts of the first package structure. A manufacturing method of a package structure, comprising: providing a coreless package substrate manufactured by using the manufacturing method according to claim 1 or 2; placing a wafer in the crystallized groove and forming with the bumps Electrically connecting; filling an insulating material in the gap between the crystallizing recess and the wafer to fix the wafer to the coreless package substrate; and forming a second build-up structure on the coreless package substrate With the crystal a side of the sheet, wherein the second build-up structure comprises at least a second dielectric layer, a second build-up wiring layer formed on the second dielectric layer, and a plurality of layers formed in the second dielectric layer a second conductive via hole, wherein a portion of the second conductive blind vias are electrically connected to the conductive pillars and the second build-up wiring layer. A coreless package substrate comprises: a dielectric layer having a crystal opening and a plurality of through holes; a first dielectric layer disposed on a lower surface of the dielectric layer and forming a space with the crystal opening a patterned metal layer having a wiring layer embedded in the first dielectric layer and partially disposed on a lower surface of the dielectric layer, buried and exposed to a portion constituting the crystal recess a plurality of bumps of the first dielectric layer; a plurality of conductor pillars disposed in the through holes and electrically connected to the circuit layer, wherein a thickness of the circuit layer disposed on a lower surface of the conductor pillars is The thickness of the bumps of the crystal recess is greater than the thickness of the circuit layer disposed on the lower surface of the dielectric layer; a first build-up layer is disposed on the lower surface of the first dielectric layer; and; a first conductive layer is electrically connected to the first conductive layer and the circuit layer or the bumps; wherein the first dielectric layer The first build-up circuit layer and the plurality of first conductive blind vias form a first build-up structure or the first The minimum build-up structure of the unit. The coreless package substrate of claim 5, wherein the bumps protrude from the first dielectric layer surrounding the bumps. A stacked package structure, comprising: the coreless package substrate according to claim 5 or 6, wherein a wafer is disposed in the crystallized recess and electrically connected to the bumps; an insulating material is disposed on the a first package structure is formed on the coreless package substrate to form a first package structure; and a second package structure is disposed on the first package structure. One side of the chip is electrically connected to the conductor posts of the first package structure. A package structure comprising: the coreless package substrate according to claim 5 or 6, wherein a wafer is disposed in the crystallized recess and electrically connected to the bumps; an insulating material is disposed on the substrate a gap between the crystal recess and the wafer to fix the wafer to the coreless package substrate; and a second build-up structure disposed on a side of the coreless package substrate on which the wafer is disposed, wherein the The second build-up structure includes at least one second dielectric layer, a second build-up circuit layer disposed on the second dielectric layer, and a plurality of second conductive blind vias disposed in the second dielectric layer, wherein A portion of the second conductive blind vias electrically connect the conductor posts to the second build-up wiring layer.