CN112261801A - Manufacturing method of multilayer circuit board and multilayer circuit board - Google Patents
Manufacturing method of multilayer circuit board and multilayer circuit board Download PDFInfo
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- CN112261801A CN112261801A CN202011166200.6A CN202011166200A CN112261801A CN 112261801 A CN112261801 A CN 112261801A CN 202011166200 A CN202011166200 A CN 202011166200A CN 112261801 A CN112261801 A CN 112261801A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
Abstract
The application provides a manufacturing method of a multilayer circuit board and the multilayer circuit board. The manufacturing method of the multilayer circuit board comprises the steps of carrying out hole forming operation on a substrate to form blind holes on the substrate, wherein the substrate comprises a copper-free substrate; filling a conductive layer into the blind hole; forming a calendering layer on the substrate, wherein the calendering layer covers the blind holes; and forming a circuit pattern layer on the substrate and the extension layer to form the multilayer circuit board. Through preparation blind hole on the base plate to wherein with the conducting layer embedding that has the electrical conductivity ability, the conducting layer is as inlayer circuit pattern, and forms the circuit pattern layer as outer circuit on base plate and extension layer promptly, makes at least part of the inlayer circuit of multiply wood inlay in the base plate, thereby makes the interval between inlayer circuit and the outer circuit reduce, and then makes the whole thickness of multilayer circuit board reduce.
Description
Technical Field
The invention relates to the technical field of circuit boards, in particular to a manufacturing method of a multilayer circuit board and the multilayer circuit board.
Background
With the gradual maturity of the manufacturing technology of printed circuit boards, the manufacture of single-layer boards, multi-layer boards and flexible boards has become the mainstream form of circuit boards, wherein a complete system is basically formed for the structural design and the process flow of the circuit boards. In the conventional circuit board, especially a multilayer circuit board, a plurality of circuit systems of different levels are integrated on the same substrate, and in the process of manufacturing circuit patterns of inner and outer layers, copper foils thereon are usually developed and etched to form different required circuit patterns, thereby achieving the effect of high integration.
However, the conventional multilayer circuit board is used by combining a plurality of single-layer boards, the thickness of the multilayer circuit board is still related to the number of manufactured hierarchical boards, and even if the thickness of the copper foil is reduced, the thickness of the multilayer circuit board is still thick, so that the reduction of the overall volume of an electronic device using the multilayer circuit board cannot be realized.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a manufacturing method of a multilayer circuit board capable of reducing the overall thickness of the circuit board and the multilayer circuit board.
The purpose of the invention is realized by the following technical scheme:
a method of making a multilayer wiring board, the method comprising: performing a hole forming operation on a substrate to form a blind hole on the substrate, wherein the substrate comprises a copper-free substrate; filling a conductive layer into the blind hole; forming a calendering layer on the substrate, wherein the calendering layer covers the blind holes; and forming a circuit pattern layer on the substrate and the extension layer to form the multilayer circuit board.
In one embodiment, the perforating operation on the substrate includes: and carrying out sputtering pore-forming on a preset position on the substrate so as to form the blind hole at the preset position.
In one embodiment, the perforating operation on the substrate includes: and mechanically controlling the depth of the preset position on the substrate to drill and gong so as to form the blind hole at the preset position.
In one embodiment, the forming a rolling layer on the substrate further comprises: and carrying out surface treatment operation on the substrate once so that the conductive layer is flush with the substrate.
In one embodiment, the filling of the conductive layer into the blind hole includes: and embedding a graphene plastic layer into the blind hole.
In one embodiment, the forming a hole in the substrate to form a blind hole in the substrate includes: performing a hole forming operation on the first side surface of the substrate to form a first blind hole on the substrate; and carrying out hole forming operation on the second side surface of the substrate so as to form a second blind hole which is not communicated with the first blind hole on the substrate.
In one embodiment, the forming a line pattern layer on the substrate and the rolling layer includes: drilling the substrate and the rolling layer to form a copper deposition through hole on the substrate and the rolling layer; and carrying out copper plating operation on the substrate and the calendering layer so as to form a copper foil circuit layer on the side wall of the copper deposition through hole and the calendering layer.
In one embodiment, the copper plating operation is performed on the substrate and the rolling layer, and then the method further includes: arranging a dry film on the copper foil circuit layer; etching the copper foil circuit layer; and removing the dry film on the copper foil circuit layer to form a circuit pattern layer.
In one embodiment, the removing the upper dry film further comprises: performing a solder mask operation on the line pattern layer to form a solder mask layer in a gap of the line pattern layer; and carrying out secondary surface treatment operation on the copper foil circuit layer and the solder mask layer so as to form a tin paste layer on the copper foil circuit layer.
A multilayer circuit board comprising the multilayer circuit board manufacturing method of any one of the above embodiments.
Compared with the prior art, the invention has at least the following advantages:
through preparation blind hole on the base plate to wherein with the conducting layer embedding that has the electrical conductivity ability, the conducting layer is as inlayer circuit pattern, and forms the circuit pattern layer as outer circuit on base plate and extension layer promptly, makes at least part of the inlayer circuit of multiply wood inlay in the base plate, thereby makes the interval between inlayer circuit and the outer circuit reduce, and then makes the whole thickness of multilayer circuit board reduce.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a flow chart of a method for fabricating a multi-layer circuit board according to an embodiment;
fig. 2 to 11 are schematic structural views of a multilayer circuit board in an embodiment during a manufacturing process;
FIG. 12 is a schematic diagram of a multi-layer circuit board according to an embodiment;
FIG. 13 is an enlarged schematic view of the multilayer wiring board shown in FIG. 12 at A1;
FIG. 14 is a schematic view showing the structure of a multilayer wiring board according to another embodiment;
fig. 15 is an enlarged schematic view of the multilayer wiring board shown in fig. 14 at a 2.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The invention relates to a method for manufacturing a multilayer circuit board. In one embodiment, the method for manufacturing the multilayer circuit board comprises the steps of carrying out hole forming operation on a substrate to form blind holes on the substrate, wherein the substrate comprises a copper-free substrate; filling a conductive layer into the blind hole; forming a calendering layer on the substrate, wherein the calendering layer covers the blind holes; and forming a circuit pattern layer on the substrate and the extension layer to form the multilayer circuit board. Through preparation blind hole on the base plate to wherein with the conducting layer embedding that has the electrical conductivity ability, the conducting layer is as inlayer circuit pattern, and forms the circuit pattern layer as outer circuit on base plate and extension layer promptly, makes at least part of the inlayer circuit of multiply wood inlay in the base plate, thereby makes the interval between inlayer circuit and the outer circuit reduce, and then makes the whole thickness of multilayer circuit board reduce.
Please refer to fig. 1, which is a flowchart illustrating a method for fabricating a multilayer circuit board according to an embodiment of the invention. The manufacturing method of the multilayer circuit board comprises part or all of the following steps. The following describes the manufacturing method of the multilayer circuit board in detail with reference to the drawings 2 to 11 of the specification.
S100: a via forming operation is performed on a substrate 100 to form a blind via 110 on the substrate 100, wherein the substrate 100 includes a copper-free substrate 100.
In the embodiment, referring to fig. 2 and fig. 3, the blind via 110 is a groove on the substrate 100, that is, the blind via 110 is a hole that does not penetrate through the substrate 100, so that a recess with a missing part of the structure is formed on the substrate 100, and the conductive layer is conveniently filled in the blind via 110, so that the conductive layer is conveniently embedded in the substrate 100, and the conductive layer is embedded in the substrate 100, so that part of the conductive layer is overlapped with the substrate 100. In this embodiment, the substrate 100 is a resin board, that is, the material of the substrate 100 is resin, and the substrate 100 has no copper foil, so that the filling of the conductive layer is an operation before forming a circuit pattern on the copper foil, which is convenient for forming an inner circuit in the substrate 100 in a subsequent step, and thus, the inner circuit and an outer circuit of a circuit pattern layer formed in a subsequent step form a multilayer circuit board. Therefore, copper foil is not needed to be used when the inner layer circuit is manufactured, the using amount of the copper foil is reduced, and the manufacturing cost of the multilayer circuit board is reduced.
S200: the blind via 110 is filled with a conductive layer 200.
In this embodiment, please refer to fig. 4 and 5 together, the conductive layer 200 has a conductive property, for example, the conductive layer 200 is a graphene plastic layer, and under the condition of high conductive property of graphene, the graphene plastic layer improves the overall conductive property of the multilayer circuit board, and the graphene plastic layer is filled in the blind hole 110, so that the graphene plastic layer is embedded in the substrate 100, and thus the graphene plastic layer forms a layer of circuit inside the substrate 100 instead of forming an inner layer circuit between the substrate 100 and the calendering layer, and further the distance between the substrate 100 and the calendering layer is reduced, that is, the distance between the inner layer circuit and the outer layer circuit is reduced. Therefore, under the condition that the circuit formed by the graphene plastic layer has high conductivity, the thickness of the multilayer circuit board is further reduced, and the multilayer circuit board has the characteristic of being ultrathin.
S300: an extrusion layer 300 is formed on the substrate 100, wherein the extrusion layer 300 covers the blind hole 110.
In the embodiment, referring to fig. 6, the extension layer 300 is disposed on the substrate 100 as an insulating layer, on one hand, the extension layer 300 covers the blind via 110, so as to reduce the possibility of erosion of the conductive layer 200; on the other hand, the extension layer 300 separates the conductive layer 200 from the circuits on other levels, so that the inner-layer circuit and the outer-layer circuit are insulated from each other, the operation stability of the inner-layer circuit and the outer-layer circuit is improved, and the electrical safety of the multilayer circuit board is improved.
S400: a circuit pattern layer 400 is formed on the substrate 100 and the rolling layer 300 to form a multilayer wiring board.
In this embodiment, referring to fig. 7 to 12, the circuit pattern layer 400 is an outer layer circuit, and the circuit pattern layer 400 is an outer layer copper foil circuit, that is, a circuit pattern formed by etching the copper covering the substrate 100 and the extension layer 300, so as to form another circuit pattern in a region other than the conductive layer 200, thereby forming a circuit board with a multilayer structure, so that the overall thickness of the multilayer circuit board is reduced when the multilayer circuit board has a conductive property.
In one embodiment, referring to fig. 3, the performing the via-forming operation on the substrate 100 includes: and performing sputtering pore-forming on a preset position on the substrate 100 to form the blind hole 110 at the preset position. In this embodiment, the preset position on the substrate 100 corresponds to a circuit pattern of an inner-layer circuit, and by using a laser ablation technology, the substrate 100 is bombarded by high-energy laser, so that a groove with a smaller diameter, i.e., a blind hole 110, is formed at the preset position on the substrate 100, and by moving the position of the laser emitter, a plurality of densely and adjacently distributed grooves form a linear groove, i.e., a plurality of blind holes 110 form a groove for embedding the pattern of the inner-layer circuit. Like this, through decomposing the pattern of inlayer circuit into the recess on the preset position, carry out the pore-forming operation again to the preset position in proper order, be convenient for form a plurality of blind holes 110 that communicate each other to be convenient for fill conducting layer 200.
In one embodiment, the performing the hole forming operation on the substrate 100 includes: and mechanically controlling the depth of the preset position on the substrate 100 to form the blind hole 110 at the preset position. In this embodiment, the preset position on the substrate 100 corresponds to a circuit pattern of an inner-layer circuit, a groove with a smaller diameter, that is, a blind hole 110, is milled at the preset position on the substrate 100 in a depth control routing manner for a ring, and a plurality of dense and adjacently distributed grooves form a linear groove by moving the position of a drill bit, that is, a plurality of blind holes 110 form a groove for embedding the pattern of the inner-layer circuit. Like this, through decomposing the pattern of inlayer circuit into the recess on the preset position, carry out the pore-forming operation again to the preset position in proper order, be convenient for form a plurality of blind holes 110 that communicate each other to be convenient for fill conducting layer 200.
In one embodiment, referring to fig. 4 and 5, the forming of the rolling layer 300 on the substrate 100 further includes: the substrate 100 is subjected to a surface treatment operation so that the conductive layer 200 is flush with the substrate 100. In this embodiment, the conductive layer 200 is formed by injecting graphene plastic into the blind hole 110 and then solidifying, and after the conductive layer 200 is filled into the blind hole 110, there is a situation that the conductive layer 200 is excessively filled, that is, a part of the conductive layer 200 protrudes from the substrate 100, so that the conductive layer 200 is not flush with the substrate 100. In order to facilitate the subsequent covering of the rolling layer 300 on the substrate 100, the protruding portion of the conductive layer 200 is removed, so that the surface of the conductive layer 200 is parallel to the surface of the substrate 100, and thus the conductive layer 200 is completely embedded in the blind hole 110, and further the gap between the rolling layer 300 and the substrate 100 is reduced, so that the rolling layer 300 is conveniently tiled on the substrate 100, and the coverage rate of the rolling layer 300 on the substrate 100 is improved.
In one embodiment, the filling of the conductive layer 200 into the blind via 110 includes: and embedding a graphene plastic layer into the blind hole 110. In this embodiment, conducting layer 200 is the graphite alkene plastic layer, promptly the material of conducting layer 200 is the graphite alkene plastic, will the graphite alkene plastic pours into behind the blind hole 110, treat that the graphite alkene plastic is stable after, the graphite alkene plastic with the lateral wall of blind hole 110 is laminated completely, is convenient for conducting layer 200 inlays in the blind hole 110, makes conducting layer 200 with area of contact increase between the base plate 100 has improved conducting layer 200 is in installation stability on the base plate 100.
In one embodiment, the forming a hole in the substrate to form a blind hole in the substrate includes: performing a hole forming operation on the first side surface of the substrate to form a first blind hole on the substrate; and carrying out hole forming operation on the second side surface of the substrate so as to form a second blind hole which is not communicated with the first blind hole on the substrate. In this embodiment, in order to facilitate the formation of the multilayer circuit board, two sides on the substrate are respectively subjected to hole forming operation, so that the two sides of the substrate are respectively formed with the first blind hole and the second blind hole, the first blind hole and the second blind hole are respectively filled with the conductive layer, so that two sides of the substrate are respectively formed with an inner layer circuit, thereby making the multilayer circuit board at least have three layers of circuit patterns, namely, an outer layer circuit pattern and two inner layer circuit patterns, and the multilayer circuit board is suitable for the multilayer circuit board with more than three layers of circuits, so that the distance between the substrate and the extension layers on two sides is reduced, namely, the distance between the outer layer circuit on the two sides of the substrate and the inner layer circuit on the corresponding side is reduced, and the overall thickness of the multilayer circuit board is further.
In one embodiment, referring to fig. 7, the forming of the circuit pattern layer 400 on the substrate 100 and the rolling layer 300 includes: drilling the substrate 100 and the rolling layer 300 to form a copper deposition through hole 700 on the substrate 100 and the rolling layer 300; the substrate 100 and the rolling layer 300 are subjected to a copper plating operation to form a copper foil circuit layer 410 on the sidewall of the copper deposition through hole 700 and the rolling layer 300. In this embodiment, due to the structure of the multi-layer board to be formed, the copper deposition via 700 is formed on the substrate 100 and the extension layer 300, which facilitates connection of the circuits between different levels, so that the circuits between the circuits of different levels are conducted, and thus more circuits are integrated on the same board. The copper foil circuit layer 410 formed subsequently is a copper clad laminate, which is used as a base plate of an outer layer circuit, i.e., a required outer layer circuit pattern is formed on the copper foil circuit layer 410.
In one embodiment, referring to fig. 8, the copper plating operation on the substrate 100 and the rolling layer 300 further includes: arranging a dry film 800 on the copper foil circuit layer 410; etching the copper foil circuit layer 410; the dry film 800 on the copper foil circuit layer 410 is removed to form a circuit pattern layer 400. In this embodiment, the dry film 800 covers the copper foil circuit layer 410, and an etching area of the copper foil circuit layer 410 is selected, so as to form a required circuit pattern on the copper foil circuit layer 410, wherein the dry film 800 has an etching-resistant characteristic, that is, in the process of etching the copper foil, the copper foil covered by the dry film 800 is retained, and the copper foil uncovered by the dry film 800 is etched, and is removed by a cleaning solution, so that the circuit pattern layer 400 with a specified pattern shape is finally formed on the copper foil circuit layer 410 by etching.
In one embodiment, referring to fig. 9 to 11, the removing the dry film 800 further includes: performing a solder mask operation on the line pattern layer 400 to form a solder mask layer 420 in the gap of the line pattern layer 400; and performing a secondary surface treatment operation on the copper foil circuit layer 410 and the solder mask layer 420 to form a solder paste layer 430 on the copper foil circuit layer 410. In this embodiment, after the circuit pattern layer 400 is formed, in order to reduce short circuit between circuits in the circuit pattern layer 400, the solder resist layer 420 is disposed in the gap of the circuit pattern layer 400, and the solder resist layer 420 is a glue layer with insulating property, so as to avoid short circuit inside the outer layer circuit. The second surface treatment operation is to treat the copper foil on the circuit pattern layer 400, and form a solder paste layer 430 on the copper foil circuit layer 410, so that the copper foil on the circuit pattern layer 400 is covered with solder paste, and the conductivity and the weldability of the bonding pad of the multilayer circuit board are improved.
It is understood that after the hole forming operation, the blind hole 110 for filling the conductive layer 200 is formed on the substrate 100, and the blind hole 110 is different from a through hole on a conventional circuit board, and the blind hole 110 is used for embedding the conductive layer 200, so that the conductive layer 200 is partially overlapped with the substrate 100 and cannot penetrate through the substrate 100, thereby avoiding the short circuit of the inner layer circuit on both sides of the substrate 100.
In order to reduce the short circuit probability of the inner layer circuit of the produced multilayer circuit board, namely reduce the scrap probability of the multilayer circuit board, before step S200, the method further comprises the following steps:
obtaining the illumination reflection time of each blind hole on the substrate;
comparing the illumination reflection time with a preset reflection time to obtain reflection delay time;
detecting whether the reflection delay time is greater than 0;
and when the reflection delay time is more than 0, sending a defective alarm signal to a monitoring system.
In this embodiment, the illumination reflection time is obtained by an infrared transmitter-receiver, that is, an output end of the infrared transmitter-receiver is aligned with the blind hole 110 of the substrate 100, and emits an infrared light to the bottom of the blind hole 110, and according to the time of receiving the reflected infrared light, it is determined whether the blind hole 110 penetrates through the substrate 100. When the blind hole 110 does not penetrate through the substrate 100, the blind hole 110 has a bottom on the substrate 100, and the infrared light emitted by the output end of the infrared emission receiver returns along the original path after meeting the bottom of the blind hole 110, that is, the infrared emission receiver receives the reflected infrared light; when the blind hole 110 penetrates the substrate 100, the infrared transmitter-receiver cannot receive the reflected infrared light, i.e., the illumination reflection time is infinite. When the preset reflection time is on one side of the substrate 100 and the other side of the substrate 100 is used as the bottom of the blind hole 110, the infrared transceiver receives the reflection time of the reflected infrared light. Thus, the reflection delay time is obtained by comparing the illumination reflection time with a preset reflection time, and the reflection delay time is a reflection time difference for determining infrared light, so that whether the blind hole 110 is penetrated or not is determined conveniently. When the reflection delay time is greater than 0, it indicates that the reflection time of the infrared light is greater than the preset reflection time, i.e., it indicates that the bottom of the blind via 110 is outside the substrate 100, i.e., it indicates that the blind via 110 penetrates through the substrate 100. The multilayer circuit board is an unqualified multilayer board, cannot be used as a normal circuit board, and can be conveniently found by the monitoring system in time by sending a defective alarm signal to the monitoring system, so that unqualified multilayer circuit boards can be conveniently removed in time, and the qualification rate of the multilayer circuit board is improved.
Further, when the hole forming operation is performed, at least one of a sputtering hole forming mode and a mechanical depth control drilling gong mode is used for forming the blind hole 110. However, the above-mentioned hole forming method needs to remove part of the material of the substrate 100, and during the removing process, part of the waste material is inevitably left, and the remaining waste material will affect the molding volume of the conductive layer 200 in the blind hole 110, so that the volume of the conductive layer 200 in the blind hole 110 is reduced, and the thickness of the conductive layer 200 directly affects the conductivity thereof, which is easy to cause the conductivity of the multilayer circuit board to be reduced.
In order to facilitate timely finding and cleaning the residual waste material to improve the conductivity of the multilayer circuit board, before step S200, the method further comprises the following steps:
acquiring a blind hole imaging image of the substrate;
acquiring the brightness value of each blind hole according to the blind hole imaging image;
comparing the brightness value with a preset brightness to obtain a brightness feedback quantity;
and adjusting the cleaning time and times of the plasma cleaner for the substrate according to the brightness feedback quantity.
In this embodiment, the image of the blind hole 110 is an image of a side surface of the substrate 100 where the blind hole 110 is opened, and the image capturing device captures the brightness of the substrate 100 to form the image of the blind hole 110, where the image of the blind hole 110 includes a brightness value corresponding to each blind hole 110, that is, the brightness of the reflected light at the sidewall and the bottom of the blind hole 110. The brightness value is a value corresponding to the brightness in the blind hole 110, and is used for reflecting the light reflection performance of the side wall and the bottom of the blind hole 110, and when waste materials remain in the blind hole 110, the light is not in mirror reflection in the blind hole 110, that is, the light is in diffuse reflection in the blind hole 110, so that the number of light finally reflected back to the image acquisition device is reduced, and the reflection brightness obtained by the image acquisition device is reduced. In this way, the brightness feedback quantity is obtained by comparing the brightness value with a preset brightness, wherein the preset brightness is the brightness corresponding to the blind hole 110 without the residue, and the brightness feedback quantity represents the difference between the current brightness of the blind hole 110 and the brightness without the residue, so as to determine whether the residue exists in the blind hole 110. The brightness feedback quantity determines the cleaning parameters of the plasma cleaning machine, namely the brightness feedback quantity is in direct proportion to the cleaning time and times of the plasma cleaning machine for the substrate 100, namely the brightness feedback quantity is increased, the cleaning time and times of the plasma cleaning machine for the substrate 100 are increased, residues in the blind hole 110 can be conveniently removed, the cleanliness in the blind hole 110 is improved, the volume of the conductive layer 200 in the blind hole 110 is improved, and the conductivity of the multilayer circuit board is further improved.
In addition, the preset brightness may also be determined according to the shape of the blind via 110 on the substrate 100, and different shape structures, and the brightness value of the blind via 110 without the residue is also different, that is, before the brightness value is compared with the preset brightness, the shape of the blind via 110 corresponding to the used preset brightness is the same as the shape of the blind via 110 currently being detected, so as to ensure that the comparison standard is correspondingly adjusted when the brightness of the blind vias 110 of different shapes is compared, so as to improve the cleanliness of the residue in the blind via 110.
Furthermore, after the conductive layer 200 is filled in the blind hole 110, that is, after the graphene plastic is embedded in the substrate 100, a portion of the conductive layer 200 may protrude from the substrate 100, and the protruding conductive layer 200 will block the bonding between the calendering layer 300 and the substrate 100, so that the surface flatness of the calendering layer 300 is reduced, thereby improving the defective rate of the multilayer circuit board.
In order to improve the flatness of the rolled layer 300, before step S300, the following steps are further included:
acquiring a conductive convex image of the substrate;
acquiring the maximum value of the ectopic bulge of the conducting layer according to the conducting bulge image;
comparing the maximum value of the ectopic bulge with a preset bulge value to obtain compensation quantity of the ectopic bulge;
and adjusting the removal sinking amount of the surface foreign matter remover according to the compensation amount of the ectopic bulge.
In this embodiment, the conductive protrusion image is obtained by an image capturing device from the side of the substrate 100, that is, the capturing direction of the image capturing device is toward the side of the substrate 100, so as to obtain the protrusion height of the conductive layer 200 on the substrate 100. After the conductive layer 200 is embedded in the blind hole 110, the depth of the blind hole 110 is different due to the different shape of the blind hole 110, so that the protrusion of the conductive layer 200 is different from the height of the substrate 100. In order to remove the protruding portion of the conductive layer 200, the height of the highest protruding portion of the conductive layer 200 on the substrate 100, i.e., the maximum value of the ectopic protrusion, is obtained. And comparing the maximum value of the ectopic bump with a preset bump value facilitates determining the height difference between the highest height of the protrusion of the conductive layer 200 and the bump corresponding to the preset bump value. Thus, according to the magnitude of the compensation amount of the ectopic protrusion, the surface foreign matter remover can determine the distance of downward movement which is finally needed, namely, the amount of subsidence is removed, so that the excessive protruding parts of the conducting layer 200 on the substrate 100 are removed, the flatness of the plane formed by the substrate 100 and the conducting layer 200 is improved, the surface flatness of the rolling layer 300 is improved, and the smooth circuit pattern layer 400 can be conveniently formed on the rolling layer 300 in the follow-up process.
In the above embodiments, the image capturing Device includes a CCD (Charge Coupled Device) camera or a CMOS (Complementary Metal Oxide Semiconductor) camera. Moreover, the conductive layer 200 is made of graphene, for example, the conductive layer 200 is made of graphene plastic, and the graphene has the characteristics of small thickness, strong hardness, high conductivity, high compactness, strong light transmittance, strong flexibility and large thermal conductivity. For example, lmm graphite may contain 300 ten thousand layers of graphene; the thickness of the single-layer graphene is 0.35 nm; such as with lm2The graphene is used as a hammock, the weight of the hammock is less than lmg, and the hammock can bear 1kg of cats; loz graphite covers 28 football fields; the hardness of the graphene plastic is greater than that of diamond, and the breaking strength of the graphene plastic is 125 Gpa; the smallest gas atom (helium) is also impermeable; the visible light transmittance exceeds 97 percent; the resistivity of the graphene plastic is 10-8Ω · m, less than the resistivity of pure copper; the current transfer speed of the graphene plastic is 1/300 of the speed of light; the carrier mobility of the graphene plastic is 2 multiplied by 10-5cm2v.S, which is 100 times of the silicon material; the thermal conductivity coefficient of the graphene plastic is 5300 w/(m.K); twisting the bi-layer graphene to a specific angle, the so-called "magic angle", the material becomes a superconductor at 1.7K. So that the conductive layer 200 serves as a conductive material for forming an inner wiring.
The application also provides a multilayer circuit board which is obtained by adopting the manufacturing method of the multilayer circuit board in any embodiment. In this embodiment, the conducting layer with conductive performance is embedded in the blind hole on the substrate, the conducting layer is as the inner layer circuit pattern, namely the conducting layer is as the inner layer circuit, and the circuit pattern layer is formed as the outer layer circuit on the substrate and the extension layer, so that at least part of the inner layer circuit of the multilayer board is embedded in the substrate, thereby the distance between the inner layer circuit and the outer layer circuit is reduced, and further the whole thickness of the multilayer circuit board is reduced.
Referring to fig. 12, which is a schematic structural diagram of a multilayer circuit board according to an embodiment of the present invention, the multilayer circuit board 10 includes a substrate 100, a conductive layer 200, a rolling layer 300, and a circuit pattern layer 400. Referring to fig. 13, the substrate 100 is provided with a blind hole 110. The conductive layer 200 is disposed in the blind hole 110, and the conductive layer 200 is connected to the substrate 100. The extension layer 300 is respectively connected to the conductive layer 200 and the substrate 100, and a projection of the extension layer 300 on the substrate 100 covers the blind hole 110. The line pattern layer 400 is connected to the substrate 100 and the rolling layer 300, respectively.
In this embodiment, the blind hole 110 on the substrate 100 is used for accommodating the conductive layer 200, so that the conductive layer 200 is embedded in the blind hole 110, so that the conductive layer 200 is embedded in the substrate 100, that is, there is a situation of partial overlap between the conductive layer 200 and the substrate 100, the conductive layer 200 is used as an inner circuit of the multilayer circuit board, a circuit on the circuit pattern layer 400 is used as an outer circuit, and the conductive layer 200 is connected with the substrate 100 in an embedded manner, so that the distance between the inner circuit and the outer circuit of the multilayer circuit board is reduced, so that the distance between the circuit pattern layer 400 and the substrate 100 is reduced, and the overall thickness of the multilayer circuit board is reduced.
In one embodiment, referring to fig. 12 and 13, the conductive layer 200 is attached to the bottom of the blind via 110. In this embodiment, the conductive layer 200 is accommodated in the blind hole 110, the conductive layer 200 forms an inner-layer circuit in the substrate 100, and in order to reduce short circuit with the inner-layer circuit of other layers, the conductive layer 200 is connected to the bottom of the blind hole 110, so that the blind hole 110 is a hole that does not penetrate through the substrate 100, that is, the blind hole 110 is equivalent to a groove, and the conductive layer 200 is embedded in the substrate 100.
In one embodiment, the blind holes comprise a first blind hole and a second blind hole, and the opening direction of the first blind hole is opposite to the opening direction of the second blind hole; the conducting layer comprises a first conducting layer and a second conducting layer, and the first conducting layer is positioned in the first blind hole to form a first inner-layer circuit; the second conductive layer is located in the second blind hole to form a second inner layer circuit. In this embodiment, the first blind hole and the second blind hole are respectively located on two sides of the substrate, the first conductive layer is arranged in the first blind hole, the first conductive layer is embedded in the substrate to form an inner circuit of one level, the second conductive layer is arranged in the second blind hole, and the second conductive layer is also embedded in the substrate to form an inner circuit of another level. Therefore, the circuit of two different levels can be formed in the substrate, the outer-layer circuit on the circuit pattern layer is combined to form the multilayer circuit board of at least three levels, and the embedded distribution of the inner-layer circuit reduces the distance between the outer-layer circuit and the inner-layer circuit, so that the thickness of the multilayer circuit board is reduced, and the ultra-thinning of the multilayer circuit board is realized.
In one embodiment, the first blind hole and the second blind hole are arranged in a staggered manner. In this embodiment, the first conductive layer in the first blind hole forms a first inner layer circuit, the second conductive layer in the first blind hole forms a second inner layer circuit, the two inner layer circuits are simultaneously embedded in the substrate, and in order to reduce electromagnetic interference between different inner layer circuits, the first blind hole and the second blind hole are arranged in a staggered manner, so that the facing area between the first conductive layer and the second conductive layer is reduced, and the staggered area between the first inner layer circuit and the second inner layer circuit is increased. After the circuit is powered on, the electromagnetic signals of the other inner layer circuit received by the first inner layer circuit or the second inner layer circuit are reduced, and the electromagnetic interference between the first inner layer circuit and the second inner layer circuit is reduced, so that the electromagnetic shielding performance of the inner layer circuit is improved, and the operation stability of the multilayer circuit board is improved. In one embodiment, in order to reduce the probability of short circuit between the inner-layer lines, the first conducting layer and the second conducting layer are arranged in an interval insulation mode.
In one embodiment, referring to fig. 12, the circuit pattern layer 400 includes a copper foil circuit layer 410, the copper foil circuit layer 410 is respectively connected to the substrate 100, the calendering layer 300 and the conductive layer 200, the copper foil circuit layer 410 has an outer circuit pattern, and the copper foil circuit layer 410 is used for forming an outer circuit. In this embodiment, the copper foil circuit layer 410 covers the substrate 100 and the rolling layer 300, and the copper foil circuit layer 410 is electrically connected to the conductive layer 200. The copper foil circuit layer 410 forms an outer layer circuit pattern by means of development and exposure, so that the copper foil on the copper foil circuit layer 410 forms a required outer layer circuit. The copper foil circuit layer 410 is connected to the conductive layer 200 by drilling the substrate 100 and the rolling layer 300 to form a copper deposition through hole on the substrate 100 and the rolling layer 300, and then performing a copper plating operation on the substrate 100 and the rolling layer 300 to form the copper foil circuit layer 410 on the sidewall of the copper deposition through hole and the rolling layer 300, and after the copper deposition through hole penetrates through the substrate 100, the blind hole 110 is exposed, and the copper plating is performed on the sidewall of the copper deposition through hole to electrically connect the copper foil circuit layer 410 to the conductive layer 200.
In one embodiment, referring to fig. 12, the circuit pattern layer 400 further includes a solder resist layer 420, the copper foil circuit layer 410 is provided with solder mask holes 412, and at least a portion of the solder resist layer 420 is disposed in the solder mask holes 412. In this embodiment, the pattern of the copper foil circuit layer 410 is an outer layer circuit pattern, the outer layer circuit of the copper foil circuit layer 410 is composed of a plurality of copper foil lines, and a gap exists between the plurality of copper foil lines, that is, the solder mask hole 412 is located. In order to reduce the probability of damage to the calendering layer 300 and the substrate 100 caused by welding at a position without a copper foil, the gap between the copper foil circuits in the copper foil circuit layer 410 is blocked by the solder mask layer 420, namely the solder mask layer 420 is used for sealing the solder resisting hole 412, so that the contact probability of hot melting solder paste and the calendering layer 300 during welding is reduced, and the damage probability of the multilayer circuit board is reduced.
In one embodiment, referring to fig. 12, the circuit pattern layer 400 further includes a solder paste layer 430, and the solder paste layer 430 is connected to the copper foil circuit layer 410 and the solder resist layer 420 respectively. In this embodiment, the solder paste layer 430 is made of a tin-lead mixture, which facilitates melting with solder during soldering, and improves soldering strength between the soldering element and the multilayer circuit board, thereby improving conductivity and solderability of the bonding pad on the multilayer circuit board.
In the above embodiments, the conductive layer is made of graphene, for example, the conductive layer is made of graphene plastic, and graphene has the characteristics of small thickness, strong hardness, high conductivity, high compactness, strong light transmittance, strong flexibility, and large thermal conductivity. For example, lmm graphite may contain 300 ten thousand layers of graphene; the thickness of the single-layer graphene is 0.35 nm; such as with lm2The graphene is used as a hammock, the weight of the hammock is less than lmg, and the hammock can bear 1kg of cats; loz graphite covers 28 football fields; the hardness of the graphene plastic is greater than that of diamond, and the breaking strength of the graphene plastic is 125 Gpa; the smallest gas atom (helium) is also impermeable; the visible light transmittance exceeds 97 percent; the resistivity of the graphene plastic is 10-8Ω · m, less than the resistivity of pure copper; the current transfer speed of the graphene plastic is 1/300 of the speed of light; the carrier mobility of the graphene plastic is 2 multiplied by 10-5cm2v.S, which is 100 times of the silicon material; the thermal conductivity coefficient of the graphene plastic is 5300 w/(m.K); twisting the bi-layer graphene to a specific angle, the so-called "magic angle", the material becomes a superconductor at 1.7K. So that the conductive layer 200 serves as a conductive material for forming an inner wiring.
It can be understood that the material of conducting layer 200 is graphite alkene, for example, conducting layer 200 is graphite alkene plastic layer, and graphite alkene plastic layer sets up through the mode of pouring into in blind hole 110, treat that graphite alkene plastic layer is stable after for graphite alkene plastic layer inlays in blind hole 110. Although the extension layer 300 can cover the blind hole 110, so that the graphene plastic layer is enclosed in the blind hole 110, when the injection amount of the conductive layer 200 is small, that is, the thickness of the conductive layer 200 is smaller than the depth of the blind hole 110, so that a gap exists between the conductive layer 200 and the extension layer 300, and the conductive layer 200 shakes in the blind hole 110, so that the connection stability between the conductive layer 200 and the substrate 100 is poor, and the inner line formed by the conductive layer 200 is easily damaged.
In order to improve the connection stability between the conductive layer 200 and the substrate 100, please refer to fig. 14 and 15, the substrate 100 is provided with a reverse chamfer groove 120 communicated with the blind hole 110, the reverse chamfer groove 120 is disposed away from the extension layer 300, the substrate 100 is provided with a chamfer supporting surface 130, the chamfer supporting surface 130 is located in the reverse chamfer groove 120, the chamfer supporting surface 130 is located outside the opening extension direction of the blind hole 110, and the chamfer supporting surface 130 abuts against the conductive layer 200. In this embodiment, a portion of the conductive layer 200 is located in the inverted chamfer groove 120, that is, a portion of the conductive layer 200 extends into the inverted chamfer groove 120, the conductive layer 200 abuts against the chamfer supporting surface 130, the chamfer supporting surface 130 provides an acting force towards the direction away from the extension layer 300 for the conductive layer 200, and the conductive layer 200 is clamped in the inverted chamfer groove 120 stably under the common clamping of the bottom of the inverted chamfer groove 120 and the chamfer supporting surface 130, so that the conductive layer 200 is clamped in the blind hole 110 stably, and the connection stability between the conductive layer 200 and the substrate 100 is improved. In one embodiment, the number of the reverse chamfer grooves 120 is two, two reverse chamfer grooves 120 are oppositely arranged, and the openings of two reverse chamfer grooves 120 are oppositely arranged. In this way, the part of the conductive layer 200 extending into the inverted chamfer groove 120 is increased, so that the clamping area between the conductive layer 200 and the substrate 100 is increased, and the connection stability between the conductive layer 200 and the substrate 100 is improved. Moreover, the supporting force provided by the chamfered supporting surfaces 130 in the two oppositely-arranged reverse chamfered grooves 120 is symmetrical, so that the stress of the conductive layer 200 is stable, and the connection stability between the conductive layer 200 and the substrate 100 is further improved.
Further, since the conductive layer 200 is partially in contact with the rolling layer 300, the adhesive force between the conductive layer 200 and the rolling layer 300 is adjusted by the contact area therebetween, that is, the adhesive force between the conductive layer 200 and the rolling layer 300 is proportional to the contact area therebetween, that is, the larger the contact area between the conductive layer 200 and the rolling layer 300 is, the larger the adhesive force between the conductive layer 200 and the rolling layer 300 is, so that the connection therebetween is more stable. In order to improve the connection stability between the conductive layer 200 and the rolling layer 300, please refer to fig. 15, the aperture of the blind hole 110 far from the substrate 100 is larger than the aperture of the blind hole 110 near the substrate 100. In this embodiment, the conductive layer 200 is embedded in the blind hole 110, and the conductive layer 200 is stably clamped in the blind hole 110, wherein the rolling layer 300 covers the blind hole 110, so that the rolling layer 300 abuts against a plane of the conductive layer 200 away from the bottom of the blind hole 110. Under the condition of adjusting the aperture of the blind hole 110, that is, the aperture of the blind hole 110 far from the substrate 100 is larger than the aperture of the blind hole 110 near the substrate 100, so that the contact area between the calendering layer 300 and the conductive layer 200 is increased, the adhesive force between the conductive layer 200 and the calendering layer 300 is increased, the connection stability between the calendering layer 300 and the conductive layer 200 is improved, and the probability of separation between the conductive layer 200 and the calendering layer 300 is reduced. In other embodiments, the aperture of the blind hole 110 gradually increases along the opening direction thereof, so that the contact area between the rolling layer 300 and the conductive layer 200 increases.
Furthermore, in order to further improve the stability of the conductive layer 200 in the blind hole 110, referring to fig. 15, the multilayer circuit board 10 further includes a positioning protrusion 500, the positioning protrusion 500 is disposed in the blind hole 110, the positioning protrusion 500 is connected to the substrate 100, and the positioning protrusion 500 is used for being clamped with the positioning groove on the conductive layer 200. In the present embodiment, the positioning protrusion 500 is located in the blind hole 110, for example, the positioning protrusion 500 is connected to a sidewall of the blind hole 110; for another example, the positioning protrusion 500 is protruded from the bottom of the blind hole 110; for another example, the positioning protrusion 500 is protruded from the sidewall of the blind hole 110 and the bottom of the blind hole 110, respectively. The positioning protrusion 500 corresponds to the positioning groove on the conductive layer 200, so that the conductive layer 200 is clamped in the positioning protrusion 500 in the blind hole 110, the conductive layer 200 is stably connected with the positioning protrusion 500, the conductive layer 200 is arranged in the blind hole 110, and the connection stability between the conductive layer 200 and the substrate 100 is improved.
In one embodiment, referring to fig. 15, the multilayer circuit board 10 further includes a heat dissipation layer 600, the heat dissipation layer 600 is disposed in the blind hole 110, the heat dissipation layer 600 is connected to the substrate 100 and the conductive layer 200, respectively, and a portion of the heat dissipation layer 600 is used to protrude to an external environment. In this embodiment, since the conductive layer 200 is used as an inner circuit, after the current is conducted, heat is generated on the conductive layer 200, the heat gradually gathers in the blind hole 110, and the portion of the heat dissipation layer 600 extends out to the external environment, and the heat dissipation layer 600 guides the heat on the conductive layer 200 to the external environment, so that the heat on the conductive layer 200 is dissipated to the external environment through the heat dissipation layer 600, thereby reducing the temperature in the blind hole 110 and improving the heat dissipation effect of the multilayer circuit board.
The application also provides a mobile communication device comprising the multilayer circuit board in any one of the above embodiments. In this embodiment, the blind hole on the substrate is used for accommodating the conductive layer, so that the conductive layer is embedded in the blind hole, so that the conductive layer is embedded in the substrate, that is, there is a partially overlapped condition between the conductive layer and the substrate, the conductive layer serves as an inner layer circuit of the multilayer circuit board, the circuit on the circuit pattern layer serves as an outer layer circuit, the conductive layer is connected with the substrate in an embedded manner, so that the distance between the inner layer circuit and the outer layer circuit of the multilayer circuit board is reduced, so that the distance between the circuit pattern layer and the substrate is reduced, the overall thickness of the multilayer circuit board is reduced, and the miniaturization of the mobile communication device is facilitated.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for manufacturing a multilayer circuit board, comprising:
performing a hole forming operation on a substrate to form a blind hole on the substrate, wherein the substrate comprises a copper-free substrate;
filling a conductive layer into the blind hole;
forming a calendering layer on the substrate, wherein the calendering layer covers the blind holes;
and forming a circuit pattern layer on the substrate and the extension layer to form the multilayer circuit board.
2. The method of claim 1, wherein the perforating operation on the substrate comprises:
and carrying out sputtering pore-forming on a preset position on the substrate so as to form the blind hole at the preset position.
3. The method of claim 1, wherein the perforating operation on the substrate comprises:
and mechanically controlling the depth of the preset position on the substrate to drill and gong so as to form the blind hole at the preset position.
4. The method of claim 1, wherein the forming a calendering layer on the substrate further comprises:
and carrying out surface treatment operation on the substrate once so that the conductive layer is flush with the substrate.
5. The method according to claim 1, wherein the filling of the blind via with a conductive layer comprises:
and embedding a graphene plastic layer into the blind hole.
6. The method of claim 1, wherein the drilling the substrate to form blind holes in the substrate comprises:
performing a hole forming operation on the first side surface of the substrate to form a first blind hole on the substrate;
and carrying out hole forming operation on the second side surface of the substrate so as to form a second blind hole which is not communicated with the first blind hole on the substrate.
7. The method of claim 1, wherein the forming a circuit pattern layer on the substrate and the calendering layer comprises:
drilling the substrate and the rolling layer to form a copper deposition through hole on the substrate and the rolling layer;
and carrying out copper plating operation on the substrate and the calendering layer so as to form a copper foil circuit layer on the side wall of the copper deposition through hole and the calendering layer.
8. The method of claim 7, wherein the step of copper plating the substrate and the calendering layer further comprises the steps of:
arranging a dry film on the copper foil circuit layer;
etching the copper foil circuit layer;
and removing the dry film on the copper foil circuit layer to form a circuit pattern layer.
9. The method of claim 8, wherein removing the dry film further comprises:
performing a solder mask operation on the line pattern layer to form a solder mask layer in a gap of the line pattern layer;
and carrying out secondary surface treatment operation on the copper foil circuit layer and the solder mask layer so as to form a tin paste layer on the copper foil circuit layer.
10. A multilayer wiring board obtained by the method for producing a multilayer wiring board according to any one of claims 1 to 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI768761B (en) * | 2021-03-11 | 2022-06-21 | 萬億股份有限公司 | Method for optimizing hole filling and making fine lines on printed circuit boards |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007221068A (en) * | 2006-02-20 | 2007-08-30 | Canon Components Inc | Flush printed wiring board, method for manufacturing same, and multilayer printed wiring board made thereof |
| TW201036509A (en) * | 2009-03-17 | 2010-10-01 | Advanced Semiconductor Eng | Structure of embedded-trace substrate and method of manufacturing the same |
| CN102387672A (en) * | 2010-08-30 | 2012-03-21 | 富葵精密组件(深圳)有限公司 | Method for manufacturing multilayer circuit board |
| JP2012216583A (en) * | 2011-03-31 | 2012-11-08 | Ngk Insulators Ltd | Wiring board and manufacturing method of the same |
| CN103458628A (en) * | 2012-05-30 | 2013-12-18 | 富葵精密组件(深圳)有限公司 | Multi-layer circuit board and manufacturing method thereof |
| CN104244616A (en) * | 2014-08-27 | 2014-12-24 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method for thin coreless substrate |
| TW201628478A (en) * | 2015-01-23 | 2016-08-01 | 欣興電子股份有限公司 | Circuit substrate and fabrication method thereof |
| CN106634221A (en) * | 2016-10-28 | 2017-05-10 | 南京林业大学 | Graphene conductive ink, preparation method therefor and inkjet-printed flexible paper-based conductive line |
| CN107686688A (en) * | 2017-09-23 | 2018-02-13 | 南京林业大学 | Graphene/polypyrrole/carbon black conductive ink and preparation method and flexible-paper-base writing conducting wire |
| CN210381445U (en) * | 2019-07-16 | 2020-04-21 | 湖北理工学院 | Novel circuit board based on thermal conductive plastic |
| CN111465174A (en) * | 2020-04-21 | 2020-07-28 | 深圳光韵达激光应用技术有限公司 | Manufacturing method of high-heat-dissipation single-sided circuit board |
-
2020
- 2020-10-27 CN CN202011166200.6A patent/CN112261801A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007221068A (en) * | 2006-02-20 | 2007-08-30 | Canon Components Inc | Flush printed wiring board, method for manufacturing same, and multilayer printed wiring board made thereof |
| TW201036509A (en) * | 2009-03-17 | 2010-10-01 | Advanced Semiconductor Eng | Structure of embedded-trace substrate and method of manufacturing the same |
| CN102387672A (en) * | 2010-08-30 | 2012-03-21 | 富葵精密组件(深圳)有限公司 | Method for manufacturing multilayer circuit board |
| JP2012216583A (en) * | 2011-03-31 | 2012-11-08 | Ngk Insulators Ltd | Wiring board and manufacturing method of the same |
| CN103458628A (en) * | 2012-05-30 | 2013-12-18 | 富葵精密组件(深圳)有限公司 | Multi-layer circuit board and manufacturing method thereof |
| CN104244616A (en) * | 2014-08-27 | 2014-12-24 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method for thin coreless substrate |
| TW201628478A (en) * | 2015-01-23 | 2016-08-01 | 欣興電子股份有限公司 | Circuit substrate and fabrication method thereof |
| CN106634221A (en) * | 2016-10-28 | 2017-05-10 | 南京林业大学 | Graphene conductive ink, preparation method therefor and inkjet-printed flexible paper-based conductive line |
| CN107686688A (en) * | 2017-09-23 | 2018-02-13 | 南京林业大学 | Graphene/polypyrrole/carbon black conductive ink and preparation method and flexible-paper-base writing conducting wire |
| CN210381445U (en) * | 2019-07-16 | 2020-04-21 | 湖北理工学院 | Novel circuit board based on thermal conductive plastic |
| CN111465174A (en) * | 2020-04-21 | 2020-07-28 | 深圳光韵达激光应用技术有限公司 | Manufacturing method of high-heat-dissipation single-sided circuit board |
Non-Patent Citations (2)
| Title |
|---|
| 许德平: "印制电路板检孔机技术及突破", pages 195 - 198 * |
| 高宏伟等: "《电子制造装备技术》", pages: 259 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI768761B (en) * | 2021-03-11 | 2022-06-21 | 萬億股份有限公司 | Method for optimizing hole filling and making fine lines on printed circuit boards |
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