CN111293099B - Semiconductor circuit structure and manufacturing method thereof - Google Patents
Semiconductor circuit structure and manufacturing method thereof Download PDFInfo
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- CN111293099B CN111293099B CN201910175242.7A CN201910175242A CN111293099B CN 111293099 B CN111293099 B CN 111293099B CN 201910175242 A CN201910175242 A CN 201910175242A CN 111293099 B CN111293099 B CN 111293099B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 205
- 239000002184 metal Substances 0.000 claims abstract description 205
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 91
- 238000005272 metallurgy Methods 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 6
- 239000003504 photosensitizing agent Substances 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor circuit structure. A semiconductor substrate is provided, and the semiconductor substrate is provided with an under bump metallurgy layer. And forming a patterned photoresist layer on the under bump metal layer, wherein the patterned photoresist layer is provided with an opening to partially expose the under bump metal layer, the opening is divided into a first hole part and a second hole part, the first hole part is positioned between the second hole part and the under bump metal layer, and the aperture of the first hole part is larger than that of the second hole part. And forming a conductive layer in the first hole part, wherein the conductive layer is connected with the under bump metal layer. And forming a first metal layer in the second hole part, wherein the first metal layer is connected with the conductive layer. And forming a second metal layer in the second hole part, wherein the second metal layer is connected with the first metal layer. The patterned photoresist layer is removed. The conductive layer is partially removed to form a conductive portion. And partially removing the under bump metal layer to form an under bump metal pad connected with the conductive part.
Description
Technical Field
The present disclosure relates to circuit structures, and particularly to a semiconductor circuit structure and a method for fabricating the same.
Background
In a common semiconductor circuit packaging process, a semiconductor chip can be electrically connected to a circuit substrate by wire bonding or flip chip bonding, for example, the electrical connection of flip chip bonding requires a bump formed on the semiconductor chip, and then the semiconductor chip is bonded to a pad of the circuit substrate by the bump; in addition, in order to increase the flexibility of the wiring design of the chip circuit, a redistribution circuit (RDL) may be formed on the chip during the semiconductor manufacturing process, and the original pad of the chip may be moved to another region suitable for bonding by redistribution.
Taking the step of forming bumps on a semiconductor chip as an example, a photoresist layer is patterned on the semiconductor chip to partially expose an Under Bump Metallurgy (UBM), and then a bump is formed on the under bump metallurgy by electroplating. And finally, removing the patterned photoresist layer, and etching at least part of the under bump metal layer which is not overlapped with the bump according to the circuit design. In the step of removing a portion of the under bump metallurgy layer by etching, if an over-etching condition occurs, an undercut (undercut) problem may be derived, even etching to the sidewall of the bump, thereby causing poor contact between the bump and the under bump metallurgy layer, and further causing a decrease in reliability of the semiconductor device. Since the redistribution layer (RDL) is fabricated in the same manner as the bump fabrication, the same problem occurs in fabricating the redistribution layer (RDL).
Disclosure of Invention
The invention provides a method for manufacturing a semiconductor circuit structure, which can avoid the problem of undercut.
The invention provides a semiconductor circuit structure with good reliability.
The manufacturing method of the semiconductor circuit structure comprises the following steps. First, a semiconductor substrate is provided, wherein the semiconductor substrate is provided with an under bump metallurgy layer. Then, a patterned photoresist layer is formed on the under bump metallurgy layer, wherein the patterned photoresist layer is formed with an opening to partially expose the under bump metallurgy layer. The opening is divided into a first opening part and a second opening part, wherein the first opening part is positioned between the second opening part and the under bump metal layer, and the aperture of the first opening part is larger than that of the second opening part. Then, a conductive layer is formed in the first hole portion, and the conductive layer is connected with the under bump metallurgy layer. Then, a first metal layer is formed in the second hole portion, and the first metal layer is connected with the conductive layer. Then, a second metal layer is formed in the second hole portion, and the second metal layer is connected with the first metal layer. Then, the patterned photoresist layer is removed. Then, the conductive layer is partially removed to form a conductive portion. And then, partially removing the under bump metal layer to form an under bump metal pad connected with the conductive part.
In an embodiment of the invention, the step of forming the patterned photoresist layer on the under bump metallurgy layer includes the following steps. First, a first photoresist layer is formed on the under bump metallurgy layer. Then, a second photoresist layer is formed on the first photoresist layer. And finally, exposing and developing the first photoresist layer and the second photoresist layer to form a first hole part in the first photoresist layer and a second hole part in the second photoresist layer.
In an embodiment of the invention, the step of forming the patterned photoresist layer on the under bump metallurgy layer includes the following steps. First, a photoresist layer is formed on the under bump metallurgy layer. Next, the photoresist layer is exposed and developed. And then, forming a reserved hole on the photoresist layer, and carrying out dry etching on the photoresist layer in the reserved hole to partially remove the photoresist layer in the reserved hole so as to form a first hole part and a second hole part.
In an embodiment of the invention, an outer diameter of the conductive layer is larger than an outer diameter of the first metal layer, and an outer diameter of the conductive portion is equal to the outer diameter of the first metal layer by removing a portion of the conductive layer that is not overlapped with the first metal layer.
In an embodiment of the invention, the aperture of the first hole portion increases from the second hole portion toward the semiconductor substrate.
In an embodiment of the invention, an outer diameter of the conductive layer is larger than an outer diameter of the first metal layer, and the outer diameter of the conductive layer increases from the first metal layer toward the semiconductor substrate. The outer diameter of the manufactured conductive part is increased gradually from the first metal layer to the semiconductor substrate by partially removing the conductive layer along the outer contour of the conductive layer, wherein the conductive part is provided with an end part connected with the first metal layer, and the outer diameter of the end part is equal to that of the first metal layer.
In an embodiment of the invention, the conductive portion has an end portion connected to the under bump metallurgy. The outer diameter of the manufactured under bump metal pad is smaller than that of the end part by removing the part of the under bump metal layer which is not overlapped with the end part and the other part of the outer wall surface of the under bump metal layer adjacent to the end part.
In an embodiment of the invention, the under bump metallurgy pad is located within an orthographic projection range of the conductive portion on the semiconductor substrate.
The semiconductor circuit structure of the invention comprises a semiconductor substrate, an under bump metal pad, a conductive part, a first metal layer and a second metal layer. The under bump metallurgy pad is disposed on the semiconductor substrate. The conductive part is arranged on the under bump metal pad, and the under bump metal pad is positioned between the conductive part and the semiconductor substrate. The first metal layer is arranged on the conductive part, and the conductive part is positioned between the first metal layer and the under bump metal pad. The second metal layer is arranged on the first metal layer, and the first metal layer is positioned between the second metal layer and the conductive part. The conductive part is provided with a first end part connected with the first metal layer, and the outer diameter of the first end part is equal to that of the first metal layer.
In an embodiment of the invention, the outer diameters of the conductive portions are equal.
In an embodiment of the invention, an outer diameter of the conductive portion increases from the first metal layer toward the semiconductor substrate.
In an embodiment of the invention, the conductive portion has a second end portion connected to the under bump metallurgy pad, and an outer diameter of the second end portion is larger than an outer diameter of the under bump metallurgy pad.
Based on the above, the method for fabricating a semiconductor circuit structure of the present invention can prevent the undercut problem possibly generated when fabricating the conductive portion (e.g. the conductive pillar or the redistribution trace) by the opening design of the patterned photoresist layer, so as to increase the contact area between the conductive portion and the first metal layer and the contact area between the conductive portion and the under bump metal layer. Therefore, the semiconductor circuit structure manufactured has good reliability.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a manufacturing process of a semiconductor circuit structure according to an embodiment of the invention;
FIGS. 2A to 2G are schematic cross-sectional views illustrating a process for fabricating a semiconductor circuit structure according to another embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a semiconductor circuit structure according to still another embodiment of the invention.
Description of the reference numerals
10. 10a, 20: semiconductor circuit structure
100. 200: semiconductor substrate
101. 201: connecting pad
102. 202: dielectric layer
103. 203: surface of
110. 210: under bump metallurgy
112. 112a, 212: under bump metal pad
120. 220, and (2) a step of: photoresist layer
121: a first photoresist layer
122: a second photoresist layer
123. 223: opening holes
124. 224: a first hole part
125. 225: second hole part
130. 230: patterned photoresist layer
140. 240: conductive layer
142. 242: conductive pole
142 a: rewiring circuit
143. 243, and (3) a step of: first end part
144. 244: second end portion
150. 150a, 250: a first metal layer
160. 160a, 260: second metal layer
231: preformed hole
D1, D2, D3, D4: pore diameter
d1, d2, d3, d4, d5, d6, d 7: outer diameter
Detailed Description
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a manufacturing process of a semiconductor circuit structure according to an embodiment of the invention. Referring to fig. 1A, a semiconductor substrate 100, which may be a wafer or a chip, is provided, optionally depending on a wafer-level package, a wafer-level chip-scale package, or a chip-level package. In the present embodiment, a surface 103 of the semiconductor substrate 100 is provided with a pad 101, a dielectric layer 102 and an under bump metallurgy layer 110, the pad 101 is disposed on the surface 103, and the dielectric layer 102 covers the surface 103 but exposes at least a portion of the pad 101. The under bump metallurgy layer 110 covers the dielectric layer 102 and contacts the pad 101 exposed outside the dielectric layer 102. For example, the under bump metallurgy layer 110 may be a titanium/copper stack, and the titanium layer is located between the copper layer and the dielectric layer 102. It is specifically noted that the combination of the under bump metallurgy layer 110 is not limited to the above, and in other embodiments, the under bump metallurgy layer may be a ti-w/cr-cu/cu stack, a cr/cr-cu/cu stack, a ti-w/cu/ni stack, a ti-w/ni-v/cu stack, or other suitable stack.
Referring to fig. 1B, a photoresist layer 120 is formed on the under bump metal layer 110 by means of bonding, printing or coating, and the entire surface of the under bump metal layer 110 is covered. In the present embodiment, the photoresist layer 120 includes a first photoresist layer 121 and a second photoresist layer 122, and as for the manufacturing sequence, first, the first photoresist layer 121 is formed on the under bump metallurgy layer 110, and then, the second photoresist layer 122 is formed on the first photoresist layer 121. The first photoresist layer 121 is located between the second photoresist layer 122 and the under bump metallurgy layer 110, wherein the first photoresist layer 121 and the second photoresist layer 122 can be both positive photoresists, and the photosensitizer content of the first photoresist layer 121 is higher than that of the second photoresist layer 122. For example, the ratio of the photosensitizer content of the first photoresist layer 121 to the photosensitizer content of the second photoresist layer 122 is between 1.5 and 2 times.
Referring to fig. 1C, next, the first photoresist layer 121 and the second photoresist layer 122 are exposed and developed, in this embodiment, the same mask (not shown) is used to expose the first photoresist layer 121 and the second photoresist layer 122, because the content of the photosensitizer in the first photoresist layer 121 is higher than that in the second photoresist layer 122, the solubility of the developer in the exposed part of the first photoresist layer 121 is higher than that in the exposed part of the second photoresist layer 122. That is, when the exposed first and second photoresist layers 121 and 122 are developed, the developing speed of the first photoresist layer 121 exposed to light is faster than that of the first photoresist layer 121 exposed to light, so that the aperture D1 of the first hole portion 124 formed in the first photoresist layer 121 is larger than the aperture D2 of the second hole portion 125 formed in the second photoresist layer 122. At this point, the patterned photoresist layer 130 is substantially completed, and the first hole portion 124 and the second hole portion 125, which are connected to each other, form an opening 123 to partially expose the ubm layer 110.
Referring to fig. 1D, a conductive layer 140 is formed in the first hole portion 124 by electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or other suitable processes, wherein the conductive layer 140 is connected to the ubm layer 110 and fills the first hole portion 124. Next, a first metal layer 150 is formed in the second hole 125 by electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or other suitable processes, wherein the first metal layer 150 is connected to the conductive layer 140 and does not fill the second hole 125. Next, a second metal layer 160 is formed in the second hole 125 by electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or other suitable processes, and is formed on the first metal layer 150, so as to fill other areas of the second hole 125 not filled by the first metal layer 150. That is, the second hole 125 is filled with the first metal layer 150 and the second metal layer 160 connected to each other, wherein the first metal layer 150 is located between the conductive layer 140 and the second metal layer 160, and the conductive layer 140, the first metal layer 150 and the second metal layer 160 can be a copper layer, a nickel layer and a gold layer, respectively, but not limited thereto.
Referring to fig. 1E, the patterned photoresist layer 130 is removed to expose the conductive layer 140, the first metal layer 150, the second metal layer 160, and the ubm layer 110. Based on the design of the opening 123, the outer diameter d1 of the conductive layer 140 is larger than the outer diameter d2 of the first metal layer 150, and the conductive layer 140 has a portion that does not overlap with the first metal layer 150. Specifically, the portion of the conductive layer 140 that does not overlap with the first metal layer 150 generally refers to the portion of the conductive layer 140 that exceeds the outer wall surface of the first metal layer 150 in the direction parallel to the surface 103.
Referring to fig. 1E and fig. 1F, the conductive layer 140 is etched to remove the portion not overlapped with the first metal layer 150, so as to obtain a conductive portion, in this embodiment, the conductive portion may be a conductive pillar 142, and an outer diameter d3 of the conductive pillar 142 is equal to an outer diameter d2 of the first metal layer 150. On the other hand, the conductive pillar 142 has a first end 143 connected to the first metal layer 150, wherein an outer diameter d3 of the conductive pillar 142 is designed with a constant diameter, and an outer diameter (i.e., an outer diameter d3) of the first end 143 is equal to the outer diameter d2 of the first metal layer 150. Based on setting the outer diameter of the base material (i.e., the conductive layer 140) of the conductive pillar 142 to be larger than the outer diameter of the first metal layer 150, when the base material (i.e., the conductive layer 140) is etched, only the portion of the base material (i.e., the conductive layer 140) that is not overlapped with the first metal layer 150 is etched and removed, so as to ensure that the outer diameter of the manufactured conductive pillar 142 is equal to the outer diameter of the first metal layer 150, and the first end 143 is in full contact with the first metal layer 150, thereby increasing the contact area between the conductive pillar 142 and the first metal layer 150, and avoiding the influence on the bonding strength between the conductive pillar 142 and the first metal layer 150 due to the undercut problem.
Then, the under bump metal layer 110 is partially removed to form an under bump metal pad 112 connected to the conductive pillar 142. Further, the conductive pillar 142 has a second end 144 connected to the under bump metallurgy 110, wherein the under bump metallurgy 110 may be generally divided into a first portion not overlapping with the second end 144 and a second portion overlapping with the second end 144, the first portion of the under bump metallurgy 110 generally refers to a region of the under bump metallurgy 110 exceeding the outer wall surface of the second end 144 in a direction parallel to the surface 103, and the second portion of the under bump metallurgy 110 generally refers to another region of the under bump metallurgy 110 located within an orthographic projection range of the second end 144 on the semiconductor substrate 100.
In the process of partially removing the under bump metal layer 110, the first portion of the under bump metal layer 110 is etched and removed, and the portion of the outer wall surface of the second end portion 144 adjacent to the second portion of the under bump metal layer 110 is etched and removed, so that the under bump metal pad 112 obtained by the process is located within the range of the orthographic projection of the conductive pillar 142 on the semiconductor substrate 100, and the outer diameter d4 of the under bump metal pad 112 is smaller than the outer diameter (i.e., outer diameter d3) of the second end portion 144. That is, in the direction perpendicular to the surface 103, the orthogonal projection of the under bump metallurgy pad 112 on the semiconductor substrate 100 overlaps the orthogonal projection of the conductive pillar 142 on the semiconductor substrate 100, and the orthogonal projection of the under bump metallurgy pad 112 on the semiconductor substrate 100 falls within the orthogonal projection of the conductive pillar 142 on the semiconductor substrate 100.
Thus, the semiconductor circuit structure 10 is substantially completed, and besides the contact area and bonding strength between the conductive pillar 142 and the first metal layer 150 are greatly improved, the contact area and bonding strength between the conductive pillar 142 and the under bump metal pad 112 are also greatly improved, so that the semiconductor circuit structure 10 has good reliability.
Referring to fig. 1F, the semiconductor circuit structure 10 includes a semiconductor substrate 100, an under bump metal pad 112, a conductive pillar 142, a first metal layer 150, and a second metal layer 160. The under bump metallurgy pad 112 is disposed on the semiconductor substrate 100. The conductive pillar 142 is disposed on the under bump metallurgy pad 112, and the under bump metallurgy pad 112 is located between the conductive pillar 142 and the semiconductor substrate 100. The first metal layer 150 is disposed on the conductive pillar 142, and the conductive pillar 142 is located between the first metal layer 150 and the under bump metallurgy pad 112. The second metal layer 160 is disposed on the first metal layer 150, and the first metal layer 150 is located between the second metal layer 160 and the conductive pillar 142, wherein the conductive pillar 142 has a first end 143 connected to the first metal layer 150, and an outer diameter (i.e., an outer diameter d3) of the first end 143 is equal to an outer diameter d2 of the first metal layer 150.
It is particularly noted that the semiconductor circuit structure 10 of the present embodiment includes a combination of two sets of under bump metallurgy pads 112, conductive pillars 142, first metal layers 150 and second metal layers 160, wherein one set of under bump metallurgy pads 112, conductive pillars 142, first metal layers 150 and second metal layers 160 may be functional bumps for transmitting signals, transmitting power or grounding, and the other set of under bump metallurgy pads 112, conductive pillars 142, first metal layers 150 and second metal layers 160 may be dummy bumps for supporting in the subsequent packaging process, but the invention is not limited thereto. In other embodiments, the number of the combination of the under bump metallurgy pad, the conductive pillar, the first metal layer and the second metal layer may be increased or decreased according to actual requirements.
Fig. 2A to fig. 2G are schematic cross-sectional views illustrating a manufacturing process of a semiconductor circuit structure according to another embodiment of the invention. It should be noted that the semiconductor circuit structure 20 and the manufacturing process thereof in the present embodiment are similar to the semiconductor circuit structure 10 and the manufacturing process thereof in the previous embodiment, so the same or similar elements have the same or similar reference numerals, and the same or similar technical contents may refer to the previous embodiment, which is not repeated herein.
Referring to fig. 2A, first, a semiconductor substrate 200 is provided. In the present embodiment, a surface 203 of the semiconductor substrate 200 is provided with a pad 201, a dielectric layer 202 and an under bump metallurgy layer 210, the pad 201 is disposed on the surface 203, and the dielectric layer 202 covers the surface 203 but exposes at least a portion of the pad 201. The under bump metallurgy layer 210 covers the dielectric layer 202 and contacts the pad 201 exposed outside the dielectric layer 202.
Referring to fig. 2B, a photoresist layer 220 is formed on the under bump metal layer 210 by means of bonding, printing or coating, and the photoresist layer 220 may be a positive photoresist, and covers the under bump metal layer 210 completely. Next, the photoresist layer 220 is exposed and developed to form a preformed hole 231 on the photoresist layer 220, as shown in fig. 2C. Next, a dry etching process, such as an anisotropic etching process, is performed on the photoresist layer 220 in the preformed hole 231 to partially remove the photoresist layer 220 in the preformed hole 231, thereby forming a first hole portion 224 and a second hole portion 225, wherein the first hole portion 224 is located between the second metal layer 260 and the under bump metal layer 210, and an aperture D3 of the first hole portion 224 is larger than an aperture D4 of the second hole portion 225, as shown in fig. 2D.
At this point, the patterned photoresist layer 230 is substantially completed, and the first hole portion 224 and the second hole portion 225 which are communicated with each other constitute an opening 223 to partially expose the under bump metallurgy layer 210, and the aperture D3 of the first hole portion 224 increases from the second hole portion 225 toward the semiconductor substrate 200. That is, first hole portion 224 has a plurality of cross sections in a direction parallel to surface 203, and the size of the cross section of first hole portion 224 that is farther from second hole portion 225 is larger.
Referring to fig. 2E, a conductive layer 240 is formed in the first hole portion 224, wherein the conductive layer 240 is connected to the under bump metallurgy 210 and fills the first hole portion 224. Next, a first metal layer 250 is formed in the second hole portion 225, wherein the first metal layer 250 is connected to the conductive layer 240 and does not fill the second hole portion 225. Subsequently, a second metal layer 260 is formed in the second hole portion 225 and on the first metal layer 250, so as to fill the other areas of the second hole portion 225 not filled by the first metal layer 250. That is, the second hole portion 225 is filled with the first metal layer 250 and the second metal layer 260 connected to each other, wherein the first metal layer 250 is located between the conductive layer 240 and the second metal layer 260.
Referring to fig. 2F, the patterned photoresist layer 230 is removed to expose the conductive layer 240, the first metal layer 250, the second metal layer 260 and the under bump metallurgy 210. Based on the design of the opening 223, the outer diameter of the conductive layer 240 increases from the first metal layer 250 toward the semiconductor substrate 200, and the outer diameter of the conductive layer 240 is larger than the outer diameter d5 of the first metal layer 250. That is, the conductive layer 240 has a plurality of cross sections in a direction parallel to the surface 203, and the size of the cross section of the conductive layer 240 farther from the first metal layer 250 is larger. On the other hand, the conductive layer 240 has a portion not overlapping with the first metal layer 250, and particularly, the portion of the conductive layer 240 not overlapping with the first metal layer 250 refers to a portion of the conductive layer 240 exceeding the outer wall surface of the first metal layer 250 in a direction parallel to the surface 203.
Referring to fig. 2F and fig. 2G, then, a portion of the conductive layer 240 that is not overlapped with the first metal layer 250 is partially etched along an outer contour of the conductive layer 240 to obtain a conductive portion, in this embodiment, the conductive portion may be a conductive pillar 242, and an outer diameter of the conductive pillar 242 gradually increases from the first metal 250 layer toward the semiconductor substrate 200. Further, the cross-sectional profile of the conductive posts 242 in the direction perpendicular to the surface 203 is still similar to the cross-sectional profile of the conductive layer 240 in the direction perpendicular to the surface 203, but the cross-sectional profile of the conductive posts 242 in the direction perpendicular to the surface 203 is slightly reduced in size. On the other hand, the conductive pillar 242 has a first end 243 connected to the first metal layer 250, wherein the first end 243 completely contacts the first metal layer 250, and the outer diameter of the first end 243 is equal to the outer diameter d5 of the first metal layer 250. Therefore, the contact area between the conductive pillar 242 and the first metal layer 250 is increased, and the bonding strength between the conductive pillar 242 and the first metal layer 250 is not affected by the undercut problem.
Since the cross-sectional profile of the conductive pillars 242 in the direction perpendicular to the surface 203 is still similar to the cross-sectional profile of the conductive layer 240 in the direction perpendicular to the surface 203, and the minimum outer diameter of the conductive pillars 242 falls at the first end 243, the outer diameter of the conductive pillars 242 increases from the first end 243 toward the semiconductor substrate 200. That is, the conductive pillars 242 have a plurality of cross sections in a direction parallel to the surface 203, and the size of the cross section of the conductive pillar 242 farther from the first metal layer 250 is larger.
Thereafter, the under bump metal layer 210 is partially removed to form the under bump metal pad 212 connected to the conductive pillar 242. Further, the conductive pillar 242 has a second end 244 connected to the under bump metallurgy 210, wherein the under bump metallurgy 210 may be generally divided into a first portion not overlapping with the second end 244 and a second portion overlapping with the second end 244, the first portion of the under bump metallurgy 210 generally refers to a region of the under bump metallurgy 210 exceeding the outer wall surface of the second end 244 in a direction parallel to the surface 203, and the second portion of the under bump metallurgy 210 generally refers to another region of the under bump metallurgy 210 located within an orthographic projection range of the second end 244 on the semiconductor substrate 200.
In the process of partially removing the under bump metal layer 210, the first portion of the under bump metal layer 210 is etched and removed, and the second portion of the under bump metal layer 110 adjacent to the outer wall of the second end 244 is partially etched and removed, so that the manufactured under bump metal pad 212 is located within the orthographic projection range of the conductive pillar 242 on the semiconductor substrate 200, and the outer diameter d6 of the under bump metal pad 212 is smaller than the outer diameter d7 of the second end 244. That is, in the direction perpendicular to the surface 203, the orthogonal projection of the under bump metal pad 212 on the semiconductor substrate 200 overlaps the orthogonal projection of the conductive pillar 242 on the semiconductor substrate 200, and the orthogonal projection of the under bump metal pad 212 on the semiconductor substrate 200 falls within the orthogonal projection of the conductive pillar 242 on the semiconductor substrate 200.
Thus, the semiconductor circuit structure 20 of the present embodiment is substantially completed, and besides the contact area and the bonding strength of the conductive pillar 242 and the first metal layer 250 are greatly improved, the contact area and the bonding strength of the conductive pillar 242 and the under bump metal pad 212 are also greatly improved, so that the semiconductor circuit structure 20 can have good reliability.
Referring to fig. 2G, the semiconductor circuit structure 20 includes a semiconductor substrate 200, an under bump metal pad 212, a conductive pillar 242, a first metal layer 250, and a second metal layer 260. The under bump metallurgy pad 212 is disposed on the semiconductor substrate 200. The conductive pillar 242 is disposed on the under bump metallurgy pad 212, and the under bump metallurgy pad 212 is disposed between the conductive pillar 242 and the semiconductor substrate 200. The first metal layer 250 is disposed on the conductive pillars 242, and the conductive pillars 242 are located between the first metal layer 250 and the under bump metallurgy pad 212. The second metal layer 260 is disposed on the first metal layer 250, and the first metal layer 250 is located between the second metal layer 260 and the conductive pillars 242, wherein the conductive pillars 242 have first end portions 243 connected to the first metal layer 250, and an outer diameter of the first end portions 243 is equal to an outer diameter d5 of the first metal layer 250.
It is particularly noted that the semiconductor circuit structure 20 of the present embodiment includes a combination of two sets of under bump metallurgy pads 212, conductive pillars 242, first metal layers 250 and second metal layers 260, wherein one set of under bump metallurgy pads 212, conductive pillars 242, first metal layers 250 and second metal layers 260 may be functional bumps for transmitting signals, transmitting power or grounding, and the other set of under bump metallurgy pads 212, conductive pillars 242, first metal layers 250 and second metal layers 260 may be dummy bumps for supporting in the subsequent packaging process, but the invention is not limited thereto. In other embodiments, the number of the combination of the under bump metallurgy pad, the conductive pillar, the first metal layer and the second metal layer may be increased or decreased according to actual requirements.
Fig. 3 is a schematic cross-sectional view of a semiconductor circuit structure in accordance with yet another embodiment of the present invention. The structure and the manufacturing method of the semiconductor circuit structure 10a of the present embodiment are similar to those of the semiconductor circuit structure 10 of the above-described embodiment, and only the difference therebetween will be described below.
Referring to fig. 3, in the present embodiment, the conductive portion may be a redistribution circuit 142a, wherein two opposite end surfaces of the redistribution circuit 142a are respectively connected to the under bump metallurgy 112a and the first metal layer 150a, the second metal layer 160a is connected to the first metal layer 150a, and the first metal layer 150a is located between the redistribution circuit 142a and the second metal layer 160 a. Further, referring to the method for fabricating the semiconductor circuit structure 10, the redistribution trace 142a, the first metal layer 150a, and the second metal layer 160a can be fabricated by reducing the thickness of the photoresist layer. On the other hand, the contact area and the bonding strength between the redistribution layer 142a and the first metal layer 150a are greatly improved, and the contact area and the bonding strength between the redistribution layer 142a and the under bump metallurgy pad 112a are also greatly improved, so that the semiconductor circuit structure 10a has good reliability.
In summary, the method for fabricating a semiconductor circuit structure according to the present invention can prevent the undercut problem possibly generated during the fabrication of the conductive portion (e.g. the conductive pillar or the redistribution trace) by the opening design of the patterned photoresist layer, so as to increase the contact area between the conductive portion and the first metal layer and the contact area between the conductive portion and the under bump metal layer, and improve the bonding strength between the conductive portion and the first metal layer and the bonding strength between the conductive portion and the under bump metal layer. Therefore, the semiconductor circuit structure manufactured has good reliability.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (8)
1. A method for fabricating a semiconductor circuit structure, comprising:
providing a semiconductor substrate provided with an under bump metal layer;
forming a patterned photoresist layer on the under bump metallurgy layer, wherein the patterned photoresist layer has an opening to partially expose the under bump metallurgy layer, the opening is divided into a first hole and a second hole, the first hole is located between the second hole and the under bump metallurgy layer, the first hole has a larger aperture than the second hole, and the step of forming the patterned photoresist layer on the under bump metallurgy layer comprises:
forming a first photoresist layer on the under bump metallurgy layer;
forming a second photoresist layer on the first photoresist layer; and
exposing and developing the first photoresist layer and the second photoresist layer to form the first hole portion in the first photoresist layer and the second hole portion in the second photoresist layer, wherein the ratio of the content of the photosensitizer in the first photoresist layer to the content of the photosensitizer in the second photoresist layer is between 1.5 and 2 times;
forming a conductive layer in the first hole part, wherein the conductive layer is connected with the under bump metal layer;
forming a first metal layer in the second hole part, wherein the first metal layer is connected with the conductive layer;
forming a second metal layer in the second hole part, wherein the second metal layer is connected with the first metal layer;
removing the patterned photoresist layer;
partially removing the conductive layer to form a conductive part; and
and partially removing the under bump metal layer to form an under bump metal pad connected with the conductive part.
2. The method as claimed in claim 1, wherein an outer diameter of the conductive layer is larger than an outer diameter of the first metal layer, and an outer diameter of the conductive portion is made equal to the outer diameter of the first metal layer by removing a portion of the conductive layer not overlapping the first metal layer.
3. A method for fabricating a semiconductor circuit structure, comprising:
providing a semiconductor substrate provided with an under bump metal layer;
forming a patterned photoresist layer on the under bump metallurgy layer, wherein the patterned photoresist layer has an opening to partially expose the under bump metallurgy layer, the opening is divided into a first hole and a second hole, the first hole is located between the second hole and the under bump metallurgy layer, the first hole has a larger aperture than the second hole, and the step of forming the patterned photoresist layer on the under bump metallurgy layer comprises:
forming a photoresist layer on the under bump metallurgy layer;
exposing and developing the photoresist layer to form a reserved hole in the photoresist layer; and
performing anisotropic etching on the photoresist layer in the reserved hole to partially remove the photoresist layer in the reserved hole to form a first hole portion and a second hole portion, wherein a bottom aperture of the first hole portion is larger than a top aperture of the first hole portion, and the top aperture of the first hole portion is larger than a bottom aperture of the second hole portion;
forming a conductive layer in the first hole part, wherein the conductive layer is connected with the under bump metal layer;
forming a first metal layer in the second hole part, wherein the first metal layer is connected with the conductive layer;
forming a second metal layer in the second hole part, wherein the second metal layer is connected with the first metal layer;
removing the patterned photoresist layer;
partially removing the conductive layer to form a conductive part; and
and partially removing the under bump metal layer to form an under bump metal pad connected with the conductive part.
4. The method as claimed in claim 3, wherein the first hole portion has a gradually increasing diameter from the second hole portion toward the semiconductor substrate.
5. The method as claimed in claim 4, wherein an outer diameter of the conductive layer is larger than an outer diameter of the first metal layer, and the outer diameter of the conductive layer increases gradually from the first metal layer toward the semiconductor substrate, and the outer diameter of the conductive portion is increased gradually from the first metal layer toward the semiconductor substrate by partially removing the conductive layer along an outer contour of the conductive layer, wherein the conductive portion has an end portion connected to the first metal layer, and the outer diameter of the end portion is equal to the outer diameter of the first metal layer.
6. The method as claimed in claim 1 or 3, wherein the conductive portion has an end portion connected to the under bump metallurgy layer, and the outer diameter of the under bump metallurgy pad is smaller than that of the end portion by removing a portion of the under bump metallurgy layer not overlapping the end portion and another portion of the under bump metallurgy layer adjacent to the outer wall surface of the end portion.
7. The method as claimed in claim 1 or 3, wherein the under bump metallurgy pad is located within an orthographic projection range of the conductive portion on the semiconductor substrate.
8. A semiconductor circuit structure, characterized in that it is manufactured using the method for manufacturing a semiconductor circuit structure according to any one of claims 1 to 7.
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| TW107144327A TWI678743B (en) | 2018-12-10 | 2018-12-10 | Semiconductor circuit structure and manufacturing method thereof |
| TW107144327 | 2018-12-10 |
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| TWI678743B (en) | 2019-12-01 |
| CN111293099A (en) | 2020-06-16 |
| TW202022958A (en) | 2020-06-16 |
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