CN111640731B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN111640731B CN111640731B CN202010486457.3A CN202010486457A CN111640731B CN 111640731 B CN111640731 B CN 111640731B CN 202010486457 A CN202010486457 A CN 202010486457A CN 111640731 B CN111640731 B CN 111640731B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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Abstract
The semiconductor device comprises a semiconductor substrate, a patterned first metal layer and a plurality of second metal lugs, wherein the first metal layer is arranged above each conductive bonding pad of the semiconductor substrate, the first metal layer is connected between at least two adjacent conductive bonding pads in a crossing mode, and the second metal lugs are arranged on the first metal layer and correspond to the conductive bonding pads one to one. According to the method, the first metal layer is bridged between the at least two adjacent conductive bonding pads, the at least two adjacent second metal lugs are interconnected, the mode that the first metal layer is bridged between the conductive bonding pads can be further designed according to the rewiring requirement of the semiconductor device, the interconnection mode corresponding to the rewiring requirement among the second metal lugs is realized, the rewiring requirement of the semiconductor device is realized in the manufacturing process of the patterned first metal layer, the introduction of an additional rewiring process is not needed, the process is simple, and the cost is low.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
In the field of semiconductor technology, in the packaging process of various semiconductor devices, the fabrication of a bump structure is one of the key processes, and the bump is used to provide electrical connection between the semiconductor device and a package substrate. Some semiconductor devices require rewiring after the bump structure is formed, but the process of forming the rewiring layer generally involves more processes and is more costly. Therefore, it is necessary to develop a semiconductor device that can meet the rewiring requirement without increasing the rewiring process, and has a simple process and a low cost.
Disclosure of Invention
The semiconductor device and the manufacturing method thereof can meet the rewiring requirement of the semiconductor device by utilizing a bump manufacturing process, and are simple in process and low in cost.
In order to solve the technical problem, the application adopts a technical scheme that:
provided is a semiconductor device including: a semiconductor substrate, a first surface of which has a plurality of conductive pads; the patterned first metal layer is arranged above each conductive bonding pad, and the first metal layer is bridged between at least two adjacent conductive bonding pads; the second metal bumps are arranged on the surface of one side, away from the semiconductor substrate, of the first metal layer and correspond to the conductive bonding pads one to one.
Wherein the heights of the second metal bumps are the same.
The orthographic projection of the first metal layer bridged between two adjacent conductive bonding pads on the semiconductor substrate is in a bent or unbent strip shape.
The radial dimension of the strip is a fixed value.
The radial dimension of the strip is smaller than or equal to the size of the orthographic projection of the second metal bump on the semiconductor substrate.
Wherein the material of the first metal layer comprises titanium-tungsten alloy.
Wherein the material of the second metal bump comprises gold.
In order to solve the above technical problem, another technical solution adopted by the present application is:
provided is a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, wherein a first surface of the semiconductor substrate is provided with a plurality of conductive pads; forming a first metal layer on the first surface, wherein the first metal layer is electrically connected with the conductive bonding pad; forming a plurality of second metal bumps on the surface of one side, away from the semiconductor substrate, of the first metal layer, wherein one second metal bump is arranged at each conductive pad; and etching to remove part of the first metal layer, reserving the first metal layer below each second metal bump and reserving the first metal layer bridging between at least two adjacent second metal bumps.
Wherein the etching to remove a portion of the first metal layer, leaving the first metal layer under each second metal bump and leaving the first metal layer bridging between at least two adjacent second metal bumps comprises: forming a patterned first photoresist coating on the surface of one side of the first metal layer, which is far away from the semiconductor substrate, wherein each second metal bump and the first metal layer bridging between at least two adjacent second metal bumps are covered by the first photoresist coating; etching to remove the first metal layer which is not covered by the second metal bump or the first photoresist coating; and removing the first photoresist coating.
Wherein, the step of forming a plurality of second metal bumps on the surface of the first metal layer away from the semiconductor substrate, and disposing one second metal bump at each conductive pad position includes: forming a patterned second light resistance coating on the surface of one side, far away from the semiconductor substrate, of the first metal layer, wherein the second light resistance coating comprises a plurality of through holes, and the through holes correspond to the conductive bonding pads one to one; forming a second metal bump in each through hole; and removing the second photoresist coating.
The beneficial effect of this application is: different from the situation of the prior art, the semiconductor device provided by the application comprises a semiconductor substrate, a patterned first metal layer and a plurality of second metal bumps, wherein the first surface of the semiconductor substrate is provided with a plurality of conductive bonding pads, the first metal layer is arranged above each conductive bonding pad, the first metal layer is connected between at least two adjacent conductive bonding pads in a crossing mode, and the second metal bumps are arranged on the surface of one side, far away from the semiconductor substrate, of the first metal layer and are in one-to-one correspondence with the conductive bonding pads. The first metal layer is bridged between at least two adjacent conductive bonding pads, and second metal bumps are arranged on the first metal layer corresponding to the conductive bonding pads, so that the at least two adjacent second metal bumps are interconnected. And then can design the mode that the first metal layer bridges the conductive pad according to the rewiring demand of the semiconductor device, realize the interconnection mode corresponding to rewiring demand between the second metal lugs, thus realize the rewiring demand of the semiconductor device, and can realize in the manufacturing process of the patterned first metal layer, do not need to introduce the extra rewiring process, simple technological process, the cost is lower.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of one embodiment of a semiconductor device according to the present application;
FIG. 2a is a schematic structural diagram of another embodiment of a semiconductor device according to the present application;
FIG. 2b is a schematic top view of the semiconductor device of FIG. 2 a;
FIG. 3 is a schematic flow chart diagram illustrating one embodiment of a method for fabricating a semiconductor device according to the present application;
FIG. 4a is a schematic structural diagram of an embodiment corresponding to step S11 in FIG. 3;
FIG. 4b is a schematic structural diagram of an embodiment corresponding to step S12 in FIG. 3
FIG. 4c is a schematic structural diagram of an embodiment corresponding to step S13 in FIG. 3;
FIG. 5 is a schematic flow chart illustrating one embodiment of the step included in step S13 in FIG. 3;
FIG. 6a is a schematic structural diagram of an embodiment corresponding to step S131 in FIG. 5;
FIG. 6b is a schematic structural diagram of an embodiment corresponding to step S132 in FIG. 5;
FIG. 7 is a flowchart illustrating an embodiment of the step included in step S14 in FIG. 3;
FIG. 8a is a schematic structural diagram of an embodiment corresponding to step S141 in FIG. 7;
FIG. 8b is a schematic structural diagram of an embodiment corresponding to step S142 in FIG. 7
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a semiconductor device according to the present application, the semiconductor device including: a semiconductor substrate 11, a patterned first metal layer 12, and a plurality of second metal bumps 13. Specifically, the first surface of the semiconductor substrate 11 has a plurality of conductive pads 111, and the semiconductor substrate 11 may be a wafer that has been subjected to a chip production process but is not diced, or may be a single chip that is diced, in which case a single chip that includes two conductive pads 111 is schematically illustrated in fig. 1. A first metal layer 12 is disposed above each conductive pad 111, and the first metal layer 12 is bridged between at least two adjacent conductive pads 111. For example, in fig. 1, the first metal layer 12 bridges over and between two adjacent conductive pads 111, and is electrically connected to the conductive pads 111. It is preferable that the first metal layer 12 completely covers the conductive pad 111 thereunder to prevent unnecessary conduction of the conductive pad 111 with other components. The second metal bumps 13 are disposed on a side surface of the first metal layer 12 away from the semiconductor substrate 11, and are in one-to-one correspondence with the conductive pads 111, so that the first metal layer 12 bridging between two adjacent conductive pads 111 also bridges between two corresponding adjacent second metal bumps 13. From the first surface upwards, the conductive pad 111, the first metal layer 12 and the second metal bump 13 are sequentially distributed, the first metal layer 12 realizes the electrical connection between the second metal bump 13 and the conductive pad 111, and can be used as an intermediate layer to increase the connection strength between the second metal bump 13 and the conductive pad 111, so that the second metal bump 13 is not easy to fall off.
In addition, because the first metal layer 12 is bridged above and between two adjacent conductive pads 111, and the two second metal bumps 13 are arranged corresponding to the two conductive pads 111, the two second metal bumps 13 are interconnected through the first metal layer 12, which is equivalent to combining the two second metal bumps 13 into one electrical connection point, thereby realizing the function of rewiring, realizing the function of rewiring in the manufacturing process of the patterned first metal layer 12, and having no need of introducing an additional rewiring process, simple process and lower cost.
In another embodiment, please refer to fig. 2a and fig. 2b, fig. 2a is a schematic structural diagram of another embodiment of the semiconductor device of the present application, fig. 2b is a schematic top-view structural diagram of the semiconductor device in fig. 2a, wherein fig. 2a is a schematic cross-sectional structural diagram of each structural component in fig. 2b projected onto the upper side of the semiconductor substrate 21. The structure of the semiconductor device in this embodiment mode is similar to that in the above embodiment mode, and includes: a semiconductor substrate 21, a patterned first metal layer 22, and a plurality of second metal bumps 23. The first surface of the semiconductor substrate 21 includes a plurality of conductive pads 211 (six cases are schematically illustrated in fig. 2 a), a first metal layer 22 is disposed above each conductive pad 211, and the first metal layer 22 is bridged between at least two adjacent conductive pads 211. For example, in fig. 1, the first metal layer 22 is bridged over and between two of the left three conductive pads 211, the first metal layer 22 is bridged over and between two adjacent conductive pads 211 on the right, and the middle first metal layer 22 only covers the middle conductive pad 211. The first metal layer 22 is electrically connected to the conductive pad 211 at the corresponding position. The second metal bumps 23 are disposed on a side surface of the first metal layer 22 away from the semiconductor substrate 21, and correspond to the conductive pads 211 one by one, so that the first metal layer 22 bridging between two adjacent conductive pads 211 also bridges between two corresponding second metal bumps 23. Preferably, the heights of the second metal bumps 23 are the same in this embodiment, which is convenient for being manufactured by a single electroplating process.
Preferably, in the present embodiment, an orthographic projection of the first metal layer 22 bridging between two adjacent conductive pads 211 on the semiconductor substrate 21 is in a bent or unbent strip shape, that is, an orthographic projection of the first metal layer 22 bridging between two adjacent second metal bumps 23 on the semiconductor substrate 21 is in a bent or unbent strip shape. For example, the first metal layer 22 bridging between the two leftmost second metal bumps 23 in fig. 2b is in the shape of an unbent strip, and the first metal layer 22 bridging between the two rightmost second metal bumps 23 in fig. 2b is in the shape of a bent strip. The bridging form of the first metal layer 22 between two adjacent conductive pads 211 can be designed according to the rewiring requirement of the semiconductor device and the internal structure of the semiconductor substrate 11, so that the adjacent second metal bumps 23 can be interconnected through the first metal layer 22 to realize the rewiring requirement of the semiconductor device.
Preferably, in the present embodiment, the radial dimension D1 of the stripe shape is a fixed value and is less than or equal to the orthogonal projection dimension D2 of the second metal bump 23 on the semiconductor substrate 11, so that the difficulty of the manufacturing process of the patterned first metal layer 22 can be reduced, and the reliability of the semiconductor device can be improved. Of course, in other embodiments, the radial dimension of the bar may not be a fixed value, that is, the bar may be a rectangle, a parallelogram, a trapezoid, a circular arc, or other irregular shapes, which is not limited in the present application.
Preferably, the material of the first metal layer 22 in this embodiment includes titanium-tungsten alloy, and the material of the second metal bump 23 includes gold. Of course, in other embodiments, the material of the first metal layer may be other materials, such as titanium-copper alloy, and the material of the second metal bump may be copper.
Referring to fig. 3, fig. 3 is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor device according to the present application, where the method for manufacturing a semiconductor device described in fig. 2a includes the following steps:
and S11, providing a semiconductor substrate, wherein the first surface of the semiconductor substrate is provided with a plurality of conductive pads.
The semiconductor substrate may be a wafer that has been subjected to a chip production process but is not diced, or may be a single chip that is diced. Referring to fig. 4a, fig. 4a is a schematic structural diagram of an embodiment corresponding to step S11 in fig. 3, in which the semiconductor substrate 21 is a single chip having six conductive pads 211 on a first surface, the first surface is a functional surface of the chip, and the chip is electrically connected to other devices through the conductive pads 211.
And S12, forming a first metal layer on the first surface, wherein the first metal layer is electrically connected with the conductive pad.
Referring to fig. 4b, fig. 4b is a schematic structural diagram of an embodiment corresponding to step S12 in fig. 3, in which a first metal layer 22 is formed on the first surface of the semiconductor substrate 21, and the first metal layer 22 is electrically connected to the conductive pad 211. Preferably, the first metal layer 22 is made of titanium-tungsten alloy, and can be formed by sputtering, so as to increase the adhesion of the second metal bump 23 formed subsequently on the semiconductor substrate 21, and make it not easy to fall off.
And S13, forming a plurality of second metal bumps on the surface of the first metal layer on the side far away from the semiconductor substrate, wherein one second metal bump is arranged at each conductive pad position.
Referring to fig. 4c, fig. 4c is a schematic structural diagram of an embodiment corresponding to step S13 in fig. 3, after the first metal layer 22 is formed, a plurality of second metal bumps 23 are formed on a surface of the first metal layer 22 away from the semiconductor substrate 21, and one second metal bump 23 is disposed at each conductive pad 211. Preferably, the heights of the second metal bumps 23 are the same in this embodiment, and the material of the second metal bumps 23 is gold, and the second metal bumps can be formed by a single electroplating process.
And S14, etching to remove part of the first metal layer, and reserving the first metal layer under each second metal bump and reserving the first metal layer bridging between at least two adjacent second metal bumps.
With reference to fig. 2a, based on the structure shown in fig. 4c, a portion of the first metal layer 22 is removed by etching, and the first metal layer 22 under each second metal bump 23 and the first metal layer 22 bridging between at least two adjacent second metal bumps 23 are remained. Specifically, in the present embodiment, as shown in fig. 2a, the first metal layer 22 spans between every two of the three second metal bumps 23 on the left, and the first metal layer 22 spans between two adjacent second metal bumps 23 on the right, that is, the first metal layer 22 below and between the three second metal bumps 23 on the left, the first metal layer 22 below and between the two second metal bumps 23 on the right, and the first metal layer 22 below the middle second metal bump 23 are all retained, and the rest of the first metal layers 22 are removed by etching, so as to form the patterned first metal layer 22.
In the embodiment, the first metal layer 22 in fig. 4c is bridged between every two of the three second metal bumps 23 on the left side and between the two second metal bumps 23 on the right side, so that interconnection between the three second metal bumps 23 on the left side and the two second metal bumps 23 on the right side is respectively realized, and thus, the rewiring requirement of the semiconductor device is realized, and the rewiring requirement can be realized in the manufacturing process of the patterned first metal layer 22 without introducing an additional rewiring process, so that the process is simple, and the cost is low.
Referring to fig. 5, fig. 5 is a flowchart illustrating an embodiment of the step S13 in fig. 3, in which the step of forming a plurality of second metal bumps 23 on a surface of the first metal layer 22 away from the semiconductor substrate 21, and disposing one second metal bump 23 at each conductive pad 211 position includes:
s131, forming a patterned second photoresist coating on the surface of one side, away from the semiconductor substrate, of the first metal layer, wherein the second photoresist coating comprises a plurality of through holes, and the through holes correspond to the conductive bonding pads one to one.
Specifically, referring to fig. 6a, fig. 6a is a schematic structural diagram of an embodiment corresponding to step S131 in fig. 5. On the basis of the structure shown in fig. 4b, a patterned second photoresist layer 24 is formed on the surface of the first metal layer 22 away from the semiconductor substrate 21, the second photoresist layer 24 includes a plurality of through holes 241, and the through holes 241 are in one-to-one correspondence with the conductive pads 211. Specifically, the patterned second photoresist coating 24 can be obtained by coating a photoresist on the semiconductor substrate 21, transferring the pattern on the mask to the photoresist coating by an exposure process, and forming a through hole 241 at a position of the second photoresist coating 24 corresponding to the conductive pad 211 by a development process. The photoresist possibly remaining in the via 241 may be removed by a deionized water rinse, an oxygen rinse, or the like, so as to sufficiently expose the first metal layer 22 in the via 241.
And S132, forming a second metal bump in each through hole.
Specifically, please refer to fig. 6b, wherein fig. 6b is a schematic structural diagram of an embodiment corresponding to step S132 in fig. 5. After the patterned second photoresist 24 is formed, a second metal bump 23 is formed in each via 241. The second metal bump 23 is preferably formed by an electroplating process, so as to obtain a plurality of second metal bumps 23 with uniform height, wherein the material of the second metal bump 23 is preferably gold.
S133, removing the second photoresist coating.
Specifically, with reference to fig. 4c, after forming the second metal bump 23 in the via 241, the second photoresist coating 24 is removed by a photoresist stripping process to form the structure shown in fig. 4c, and a second metal bump 23 is formed on a side surface of the first metal layer 22 away from the semiconductor substrate 21 corresponding to each conductive pad 211.
In the embodiment, the plurality of second metal bumps 23 are formed on the surface of the first metal layer 22 away from the semiconductor substrate 21 by an electroplating process, so that the second metal bumps 23 can be conducted with the conductive bonding pads through the first metal layer 22, the semiconductor device is electrically connected with other devices, and the process is simple and easy to implement.
Referring to fig. 7, fig. 7 is a schematic flowchart illustrating an embodiment of the step S14 in fig. 3, in which the step of removing a portion of the first metal layer 22 by etching, retaining the first metal layer 22 under each second metal bump 23, and retaining the first metal layer 22 bridging between at least two adjacent second metal bumps 23 includes:
s141, a patterned first photoresist coating is formed on a surface of the first metal layer away from the semiconductor substrate, wherein each second metal bump and the first metal layer bridging between at least two adjacent second metal bumps are covered by the first photoresist coating.
Specifically, referring to fig. 8a, fig. 8a is a schematic structural diagram of an embodiment corresponding to step S141 in fig. 7. On the basis of the structure shown in fig. 4c, a patterned first photoresist layer 25 is formed on a surface of the first metal layer 22 away from the semiconductor substrate 21, wherein each second metal bump 23 and the first metal layer 22 bridging between at least two adjacent second metal bumps 23 are covered by the first photoresist layer 23. In this embodiment, the first metal layer 22 bridging between every two of the three second metal bumps 23 on the left side of fig. 8a, the first metal layer 22 bridging between the two second metal bumps 23 on the right side, and each second metal bump 23 are covered by the first photoresist coating 25.
S142, the first metal layer uncovered by the second metal bump or the first photoresist coating is removed by etching.
Specifically, please refer to fig. 8b, wherein fig. 8b is a schematic structural diagram of an embodiment corresponding to step S142 in fig. 7. After the patterned first photoresist layer 25 is formed, as described in step S141, a portion of the first metal layer 22 is not covered by the first photoresist layer 25 and is not covered by the second metal bump 23, and at this time, the portion of the first metal layer 22 that is not covered by the second metal bump 23 or the first photoresist layer 25 is removed by an etching process. The specific etching process can be dry etching or wet etching. After etching, the etching effect of the first metal layer 22 can be confirmed in a microscope inspection mode, and the phenomenon that the performance of the semiconductor device is influenced due to unnecessary conduction caused by the first metal layer 22 which is not etched cleanly is avoided.
S143, removing the first photoresist coating.
Specifically, with reference to fig. 2a, after the first metal layer 22 not covered by the second metal bump 23 and the first photoresist coating 25 is removed by etching, the first photoresist coating 25 is removed by a photoresist stripping process, so as to form the structure shown in fig. 2a, i.e., the semiconductor device provided in the present application.
In the embodiment, the etching process is adopted to reserve part of the first metal layer 22 between the adjacent second metal bumps 23, so that the part of the adjacent second metal bumps 23 is electrically interconnected through the first metal layer 22, the rewiring requirement of the semiconductor device is realized, the rewiring requirement can be realized in the manufacturing process of the patterned first metal layer 22, an additional rewiring process is not required to be introduced, the process is simple, and the cost is low.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (9)
1. A semiconductor device, comprising:
a semiconductor substrate, a first surface of which has a plurality of conductive pads;
the patterned first metal layer is arranged above each conductive bonding pad, and the first metal layer is bridged between at least two adjacent conductive bonding pads; the orthographic projection of the first metal layer bridged between two adjacent conductive bonding pads on the semiconductor substrate is in a bent or unbent strip shape;
the second metal bumps are arranged on the surface of one side, away from the semiconductor substrate, of the first metal layer and correspond to the conductive bonding pads one to one.
2. The semiconductor device according to claim 1, wherein heights of the plurality of second metal bumps are the same.
3. The semiconductor device according to claim 1,
the radial dimension of the strip is a fixed value.
4. The semiconductor device according to claim 3,
the radial size of the strip is smaller than or equal to the size of the orthographic projection of the second metal bump on the semiconductor substrate.
5. The semiconductor device according to claim 1, wherein a material of the first metal layer comprises a titanium tungsten alloy.
6. The semiconductor device of claim 1, wherein the material of the second metal bump comprises gold.
7. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein a first surface of the semiconductor substrate is provided with a plurality of conductive pads;
forming a first metal layer on the first surface, wherein the first metal layer is electrically connected with the conductive bonding pad;
forming a plurality of second metal bumps on the surface of one side, away from the semiconductor substrate, of the first metal layer, wherein one second metal bump is arranged at each conductive pad;
etching to remove part of the first metal layer, reserving the first metal layer below each second metal bump and reserving the first metal layer bridged between at least two adjacent second metal bumps; the orthographic projection of the first metal layer bridged between two adjacent second metal bumps on the semiconductor substrate is in a bent or unbent strip shape.
8. The method of claim 7, wherein the etching step of removing a portion of the first metal layer, leaving the first metal layer under each of the second metal bumps, and leaving the first metal layer bridging between at least two adjacent second metal bumps comprises:
forming a patterned first photoresist coating on the surface of one side of the first metal layer, which is far away from the semiconductor substrate, wherein each second metal bump and the first metal layer bridging between at least two adjacent second metal bumps are covered by the first photoresist coating;
etching to remove the first metal layer which is not covered by the second metal bump or the first photoresist coating;
and removing the first photoresist coating.
9. The method according to claim 7, wherein the step of forming a plurality of second metal bumps on a surface of the first metal layer away from the semiconductor substrate, one second metal bump being disposed at each conductive pad position comprises:
forming a patterned second light resistance coating on the surface of one side, far away from the semiconductor substrate, of the first metal layer, wherein the second light resistance coating comprises a plurality of through holes, and the through holes correspond to the conductive bonding pads one to one;
forming a second metal bump in each through hole;
and removing the second photoresist coating.
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| TWI246135B (en) * | 2005-01-18 | 2005-12-21 | Siliconware Precision Industries Co Ltd | Semiconductor element with under bump metallurgy structure and fabrication method thereof |
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|---|---|---|---|---|
| CN1753176A (en) * | 2004-09-22 | 2006-03-29 | 日月光半导体制造股份有限公司 | Inversion packaging structure, semiconductor chip having convex block and its manufacturing method |
| CN101442016A (en) * | 2007-11-23 | 2009-05-27 | 日月光半导体制造股份有限公司 | Silicon wafer projection structure and manufacturing method thereof |
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