TWI548049B - Semiconductor structure and method of manufacture - Google Patents

Semiconductor structure and method of manufacture Download PDF

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Publication number
TWI548049B
TWI548049B TW103132405A TW103132405A TWI548049B TW I548049 B TWI548049 B TW I548049B TW 103132405 A TW103132405 A TW 103132405A TW 103132405 A TW103132405 A TW 103132405A TW I548049 B TWI548049 B TW I548049B
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layer
metal
semiconductor structure
active surface
semiconductor wafer
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TW103132405A
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Chinese (zh)
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TW201613046A (en
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蔣靜雯
陳光欣
陳賢文
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矽品精密工業股份有限公司
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Priority to TW103132405A priority Critical patent/TWI548049B/en
Priority to CN201410540181.7A priority patent/CN105428328A/en
Priority to US14/672,268 priority patent/US20160086903A1/en
Publication of TW201613046A publication Critical patent/TW201613046A/en
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Publication of TWI548049B publication Critical patent/TWI548049B/en

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

半導體結構及其製法 Semiconductor structure and its manufacturing method

本發明係有關於一種半導體結構及其製法，尤指一種於半導體晶片上具有金屬柱的半導體結構及其製法。 The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having a metal pillar on a semiconductor wafer and a method of fabricating the same.

隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能與微型化(miniaturization)的趨勢。為了滿足半導體封裝件微型化的封裝需求，遂發展出許多封裝技術。 With the booming electronics industry, electronic products are gradually moving toward versatility, high performance and miniaturization. In order to meet the packaging requirements for miniaturization of semiconductor packages, many packaging technologies have been developed.

第1A至1G圖所示者，係習知封裝結構之製法的剖視圖。 The drawings shown in Figs. 1A to 1G are cross-sectional views showing a method of manufacturing a conventional package structure.

如第1A圖所示，提供具有相對之作用面10a與非作用面10b的半導體晶片10，該作用面10a上具有複數電極墊101，於該電極墊101與作用面10a上形成具有複數鈍化層開孔110的鈍化層11，各該鈍化層開孔110對應外露各該電極墊101，於該鈍化層11與電極墊101上依序形成做為凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)12的鈦層121與銅層122，於該銅層122上形成具有複數阻層開孔130的阻層13，各該阻層開孔130之位置對應各該鈍化層開孔110及其周緣。 As shown in FIG. 1A, a semiconductor wafer 10 having an opposite active surface 10a and a non-active surface 10b is provided. The active surface 10a has a plurality of electrode pads 101, and a plurality of passivation layers are formed on the electrode pads 101 and the active surface 10a. The passivation layer 11 of the opening 110, each of the passivation layer openings 110 correspondingly exposes the electrode pads 101, and the passivation layer 11 and the electrode pads 101 are sequentially formed as a under bump metal layer (Under Bump Metallurgy, referred to as UBM). a titanium layer 121 and a copper layer 122 are formed on the copper layer 122, and a resist layer 13 having a plurality of resistive opening 130 is formed on the copper layer 122, and each of the resist layer openings 130 corresponds to each of the passivation layer openings 110 and its periphery. .

如第1B圖所示，於各該阻層開孔130中電鍍形成銅凸塊14。 As shown in FIG. 1B, copper bumps 14 are formed by electroplating in each of the barrier layer openings 130.

如第1C圖所示，移除該阻層13及其所覆蓋的該鈦層121與銅層122。 As shown in FIG. 1C, the resist layer 13 and the titanium layer 121 and the copper layer 122 covered by the resist layer 13 are removed.

如第1D圖所示，藉由黏著層15將該半導體晶片10以其非作用面10b接置於一承載板16的凹槽160的底面上。 As shown in FIG. 1D, the semiconductor wafer 10 is attached to the bottom surface of the recess 160 of a carrier plate 16 with its inactive surface 10b by an adhesive layer 15.

如第1E圖所示，於該承載板16上形成包覆該半導體晶片10與銅凸塊14的封裝膠體17。 As shown in FIG. 1E, an encapsulant 17 covering the semiconductor wafer 10 and the copper bumps 14 is formed on the carrier 16.

如第1F圖所示，形成複數封裝膠體開孔170，各該封裝膠體開孔170對應外露各該銅凸塊14。 As shown in FIG. 1F, a plurality of package encapsulation openings 170 are formed, and each of the encapsulation colloids 170 correspondingly exposes each of the copper bumps 14.

如第1G圖所示，於各該封裝膠體開孔170中的銅凸塊14上形成導電盲孔18，後續再於該封裝膠體17與導電盲孔18上形成電性連接該半導體晶片10的線路重佈層(未圖示)。 As shown in FIG. 1G, conductive vias 18 are formed on the copper bumps 14 in the package encapsulation openings 170, and subsequently formed on the encapsulant 17 and the conductive vias 18 to electrically connect the semiconductor wafer 10. Line redistribution layer (not shown).

惟，由於習知係於阻層開孔中電鍍形成複數銅凸塊，而此製作方法所形成之銅凸塊容易高度不一，導致後續連接該銅凸塊時發生電性接觸不良現象；再者，形成對應外露該銅凸塊的封裝膠體開孔時亦容易發生對位有所偏差，進而使後續對於該銅凸塊之電性接觸不良，並降低產品良率。 However, since it is known to form a plurality of copper bumps in the opening of the resist layer, the copper bumps formed by the manufacturing method are easily different in height, resulting in electrical contact failure when the copper bumps are subsequently connected; When the encapsulation opening corresponding to the copper bump is formed, the alignment is likely to be deviated, thereby making subsequent electrical contact with the copper bump poor, and reducing the product yield.

因此，如何避免上述習知技術中之種種問題，實為目前業界所急需解決的課題。 Therefore, how to avoid various problems in the above-mentioned prior art is an urgent problem to be solved in the industry.

有鑒於上述習知技術之缺失，本發明提供一種半導體結構，係包括：半導體晶片，具有非作用面與相對該非作用面的作用面；複數形成於該作用面上之金屬柱；以及形成於該金屬柱與作用面之間及該金屬柱之側表面上之凸塊底下金屬層。 In view of the above-mentioned shortcomings of the prior art, the present invention provides a semiconductor structure including: a semiconductor wafer having an inactive surface and an active surface opposite to the non-active surface; a plurality of metal pillars formed on the active surface; and A metal layer under the bump between the metal post and the active surface and on the side surface of the metal post.

本發明復提供一種半導體結構之製法，係包括：於承載板上接置具有相對之作用面與非作用面的半導體晶片，令該非作用面連接該承載板，該作用面上形成有複數金屬柱，該金屬柱與作用面之間及該金屬柱之側表面上係形成有凸塊底下金屬層；以及於該承載板上形成封裝膠體，以包覆該半導體晶片，該封裝膠體之表面係齊平於該金屬柱之端面。 The invention provides a method for fabricating a semiconductor structure, comprising: connecting a semiconductor wafer having opposite active and non-active surfaces on a carrier plate, and connecting the non-active surface to the carrier plate, wherein the working surface is formed with a plurality of metal pillars Forming a under bump metal layer between the metal pillar and the active surface and the side surface of the metal pillar; and forming an encapsulant on the carrier plate to cover the semiconductor wafer, the surface of the encapsulant is tied Flat on the end of the metal column.

本發明復提供一種半導體結構之製法，係包括：於半導體晶片之作用面上形成具有開孔的介電層，並令該作用面外露於該介電層之開孔；於該介電層、開孔孔壁與外露於該開孔中的作用面上形成凸塊底下金屬層；於該凸塊底下金屬層上形成金屬層；移除高於該介電層之金屬層與凸塊底下金屬層，以於該作用面上形成複數金屬柱；令該半導體晶片之相對於該作用面之非作用面連接承載板；以及於該承載板上形成封裝膠體，以包覆該半導體晶片，該封裝膠體之表面係齊平於該金屬柱之端面。 The invention provides a method for fabricating a semiconductor structure, comprising: forming a dielectric layer having an opening on an active surface of a semiconductor wafer, and exposing the active surface to an opening of the dielectric layer; Forming a metal layer under the bump on the working surface exposed in the opening; forming a metal layer on the metal layer under the bump; removing the metal layer higher than the dielectric layer and the metal under the bump a layer for forming a plurality of metal pillars on the active surface; connecting the non-active surface of the semiconductor wafer with respect to the active surface; and forming an encapsulant on the carrier substrate to encapsulate the semiconductor wafer, the package The surface of the colloid is flush with the end face of the metal post.

由上可知，本發明係先形成外露電極墊的介電層，接著形成凸塊底下金屬層與金屬層，再移除該凸塊底下金屬層與金屬層之部分厚度，所以能避免習知金屬柱高度不均 之情況；再者，本發明係將半導體晶片接置於承載板上後，再形成包覆該半導體晶片與金屬柱的封裝膠體，然後研磨移除該封裝膠體與金屬柱的部分厚度以外露該金屬柱，因此本發明無需如習知般形成外露該金屬柱的封裝膠體開孔，故可避免習知之對位偏差問題，且不會受到半導體晶片的厚度不一致及黏著層的厚度不一致的影響。 As can be seen from the above, the present invention first forms a dielectric layer of the exposed electrode pad, and then forms a metal layer and a metal layer under the bump, and then removes a part of the thickness of the metal layer and the metal layer under the bump, so that the conventional metal can be avoided. Uneven height of the column In the case of the present invention, after the semiconductor wafer is placed on the carrier board, the encapsulant covering the semiconductor wafer and the metal post is formed, and then the thickness of the part of the encapsulant and the metal post is removed by grinding. Since the present invention eliminates the need for conventionally forming the encapsulation opening of the metal post, the conventional alignment deviation problem can be avoided without being affected by the inconsistent thickness of the semiconductor wafer and the inconsistent thickness of the adhesive layer.

10、20‧‧‧半導體晶片 10, 20‧‧‧ semiconductor wafer

10a、20a‧‧‧作用面 10a, 20a‧‧‧ action surface

10b、20b‧‧‧非作用面 10b, 20b‧‧‧ non-active surface

101、201‧‧‧電極墊 101, 201‧‧‧electrode pads

11、21‧‧‧鈍化層 11, 21‧‧‧ Passivation layer

110、210‧‧‧鈍化層開孔 110, 210‧‧‧ Passivation layer opening

12、23‧‧‧凸塊底下金屬層 12, 23‧‧‧ Metal layer under the bump

121、231‧‧‧鈦層 121, 231‧‧‧ Titanium

122、232‧‧‧銅層 122, 232‧‧‧ copper layer

13‧‧‧阻層 13‧‧‧resist

130‧‧‧阻層開孔 130‧‧‧Resistance opening

14‧‧‧銅凸塊 14‧‧‧ copper bumps

15、25‧‧‧黏著層 15, 25‧‧ ‧ adhesive layer

16、26‧‧‧承載板 16, 26‧‧‧ carrying board

160、260‧‧‧凹槽 160, 260‧‧‧ grooves

17、27‧‧‧封裝膠體 17, 27‧‧‧Package colloid

170‧‧‧封裝膠體開孔 170‧‧‧Package colloid opening

18‧‧‧導電盲孔 18‧‧‧ Conductive blind holes

22‧‧‧介電層 22‧‧‧Dielectric layer

220‧‧‧開孔 220‧‧‧ openings

24‧‧‧金屬層 24‧‧‧metal layer

24’‧‧‧金屬柱 24’‧‧‧Metal column

28‧‧‧線路重佈層 28‧‧‧Line redistribution

29‧‧‧絕緣保護層 29‧‧‧Insulation protective layer

30‧‧‧銲球 30‧‧‧ solder balls

第1A至1G圖所示者係習知封裝結構之製法的剖視圖；第2A至2I圖所示者係本發明之半導體結構之製法之第一實施例的剖視圖；以及第3A至3D圖所示者係本發明之半導體結構之製法之第二實施例的剖視圖。 1A to 1G are cross-sectional views showing a method of fabricating a conventional package structure; FIGS. 2A to 2I are cross-sectional views showing a first embodiment of the method of fabricating the semiconductor structure of the present invention; and FIGS. 3A to 3D. A cross-sectional view of a second embodiment of the method of fabricating a semiconductor structure of the present invention.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之用語 亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, the terms quoted in this manual The scope of the present invention is also considered to be within the scope of the invention, and is not intended to limit the scope of the invention.

第一實施例 First embodiment

第2A至2I圖所示者，係本發明之半導體結構之製法之第一實施例的剖視圖。 2A to 2I are cross-sectional views showing a first embodiment of the method of fabricating the semiconductor structure of the present invention.

如第2A圖所示，提供具有相對之作用面20a與非作用面20b的半導體晶片20，該作用面20a上具有複數電極墊201，於該電極墊201與作用面20a上形成具有複數鈍化層開孔210的鈍化層21，各該鈍化層開孔210對應外露各該電極墊201，於該鈍化層21上形成具有複數開孔220的介電層22，令各該開孔220對應外露各該電極墊201，該介電層22可為感光性絕緣層或光阻。 As shown in FIG. 2A, a semiconductor wafer 20 having an opposite active surface 20a and a non-active surface 20b is provided. The active surface 20a has a plurality of electrode pads 201, and a plurality of passivation layers are formed on the electrode pads 201 and the active surface 20a. The passivation layer 21 of the opening 210, each of the passivation layer openings 210 correspondingly exposes the electrode pads 201, and a dielectric layer 22 having a plurality of openings 220 is formed on the passivation layer 21, so that the openings 220 are respectively exposed The electrode pad 201, the dielectric layer 22 can be a photosensitive insulating layer or a photoresist.

如第2B圖所示，於該介電層22、開孔220孔壁與開孔220中的電極墊201上依序形成做為凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)23的鈦層231與銅層232。 As shown in FIG. 2B, titanium as an under bump metallurgy (UBM) 23 is sequentially formed on the dielectric layer 22, the opening of the hole 220, and the electrode pad 201 in the opening 220. Layer 231 and copper layer 232.

如第2C圖所示，於該銅層232上形成金屬層24，形成該金屬層24之材質可為銅。 As shown in FIG. 2C, a metal layer 24 is formed on the copper layer 232, and the material of the metal layer 24 may be copper.

如第2D圖所示，以例如研磨方式移除高於該介電層22之金屬層24與凸塊底下金屬層23，而於該電極墊201上留下金屬柱24’，且該金屬柱24’與作用面20a之間及該金屬柱24’之側表面上係形成有該凸塊底下金屬層23，該介電層22包覆該金屬柱24’與凸塊底下金屬層23，且齊平 於該金屬柱24’之端面；此時可視需要移除該介電層22(未圖示此情況)。 As shown in FIG. 2D, the metal layer 24 and the under bump metal layer 23 are removed from the dielectric layer 22 by, for example, grinding, leaving a metal pillar 24' on the electrode pad 201, and the metal pillar The under bump metal layer 23 is formed on the side surface between the 24' and the active surface 20a and the metal pillar 24'. The dielectric layer 22 covers the metal pillar 24' and the under bump metal layer 23, and Qiping The end face of the metal post 24'; at this time, the dielectric layer 22 may be removed as needed (this is not shown).

如第2E圖所示，藉由黏著層25將該半導體晶片20以其非作用面20b接置於一承載板26的凹槽260的底面上；於其他實施例中，該承載板26亦可不具有該凹槽260。承載板26之材質例如為晶圓、玻璃板或金屬板。 As shown in FIG. 2E, the semiconductor wafer 20 is attached to the bottom surface of the recess 260 of a carrier plate 26 by the adhesive layer 25; in other embodiments, the carrier board 26 may not be There is the groove 260. The material of the carrier plate 26 is, for example, a wafer, a glass plate or a metal plate.

於另一實施例中，亦可提供具有複數半導體晶片之晶圓，進行上述第2A-2D圖之製程後，可進行切單製程(singulation)，以將該晶圓切割為複數如第2E圖所示之半導體晶片20，此時即可將該些半導體晶片20接置於該承載板26上並進行後續製程。 In another embodiment, a wafer having a plurality of semiconductor wafers may be provided. After performing the process of the second A-2D process, a singulation process may be performed to cut the wafer into a plurality of images as shown in FIG. The semiconductor wafer 20 is shown, and the semiconductor wafers 20 can be placed on the carrier plate 26 for subsequent processing.

如第2F圖所示，於該承載板26上形成封裝膠體27，以包覆該半導體晶片20與金屬柱24’，且該封裝膠體27復形成於該凹槽260中。 As shown in FIG. 2F, an encapsulant 27 is formed on the carrier 26 to cover the semiconductor wafer 20 and the metal post 24', and the encapsulant 27 is formed in the recess 260.

如第2G圖所示，以例如研磨方式移除該封裝膠體27與金屬柱24’的部分厚度，並視需要一併移除該承載板26與該介電層22的部分厚度，以令該封裝膠體27之表面齊平於該金屬柱24’之端面。 As shown in FIG. 2G, a portion of the thickness of the encapsulant 27 and the metal post 24' is removed by, for example, grinding, and a portion of the thickness of the carrier 26 and the dielectric layer 22 is removed as needed. The surface of the encapsulant 27 is flush with the end face of the metal post 24'.

如第2H圖所示，於該封裝膠體27與金屬柱24’上形成電性連接該半導體晶片20的線路重佈層28，並於該線路重佈層28上形成外露部分該線路重佈層28的絕緣保護層29。 As shown in FIG. 2H, a circuit redistribution layer 28 electrically connecting the semiconductor wafer 20 is formed on the encapsulant 27 and the metal post 24', and an exposed portion of the circuit redistribution layer is formed on the circuit redistribution layer 28. 28 insulation protection layer 29.

如第2I圖所示，於該線路重佈層28上設置複數銲球30。 As shown in Fig. 2I, a plurality of solder balls 30 are provided on the line redistribution layer 28.

第二實施例 Second embodiment

第3A至3D圖所示者，係本發明之半導體結構之製法之第二實施例的剖視圖。 3A to 3D are cross-sectional views showing a second embodiment of the method of fabricating the semiconductor structure of the present invention.

本實施例大致上相同於前一實施例，主要不同之處在於，本實施例之複數該半導體晶片20的厚度或其非作用面20b上的黏著層25的厚度與前一實施例並不相同，使得該半導體晶片20與金屬柱24’位在不同高度，但本發明之實施並不因此受到影響。 This embodiment is substantially the same as the previous embodiment, and the main difference is that the thickness of the plurality of semiconductor wafers 20 or the thickness of the adhesive layer 25 on the non-active surface 20b of the present embodiment is not the same as that of the previous embodiment. The semiconductor wafer 20 and the metal post 24' are positioned at different heights, but the implementation of the present invention is not affected thereby.

本發明提供一種半導體結構，係包括：承載板26；半導體晶片20，係設於該承載板26上，且具有連接該承載板26之非作用面20b與相對該非作用面20b的作用面20a，該作用面20a上形成有複數金屬柱24’，該金屬柱24’與作用面20a之間及該金屬柱24’之側表面上係形成有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)23；以及封裝膠體27，係形成於該承載板26上，以包覆該半導體晶片20，該封裝膠體27之表面係齊平於該金屬柱24’之端面。 The present invention provides a semiconductor structure, comprising: a carrier plate 26; a semiconductor wafer 20 is disposed on the carrier plate 26, and has an inactive surface 20b connecting the carrier plate 26 and an active surface 20a opposite to the non-active surface 20b. A plurality of metal pillars 24 ′ are formed on the active surface 20 a , and an under bump metallurgy (UBM) is formed on the side surface of the metal pillar 24 ′ and the active surface 20 a and the side surface of the metal pillar 24 ′. 23; and an encapsulant 27 is formed on the carrier plate 26 to cover the semiconductor wafer 20. The surface of the encapsulant 27 is flush with the end surface of the metal post 24'.

於前述之半導體結構中，該半導體晶片20之作用面20a上復形成有介電層22，該介電層22並包覆該金屬柱24’與凸塊底下金屬層23，且齊平於該金屬柱24’之端面，該介電層22係為感光性絕緣層或光阻。 In the foregoing semiconductor structure, a dielectric layer 22 is formed on the active surface 20a of the semiconductor wafer 20, and the dielectric layer 22 covers the metal pillar 24' and the under bump metal layer 23, and is flush with the The end face of the metal post 24' is a photosensitive insulating layer or photoresist.

於本實施例之半導體結構中，該承載板26復具有凹槽260，該半導體晶片20係設於該凹槽260的底面上，且該封裝膠體27係形成於該凹槽260中。 In the semiconductor structure of the embodiment, the carrier plate 26 has a recess 260. The semiconductor wafer 20 is disposed on the bottom surface of the recess 260, and the encapsulant 27 is formed in the recess 260.

於本發明之半導體結構中，該凸塊底下金屬層23係包括層疊之鈦層231與銅層232，且該銅層232係位於該金屬柱24’與該鈦層231之間，且復包括線路重佈層28，係形成於該封裝膠體27與金屬柱24’上，以電性連接該半導體晶片20。 In the semiconductor structure of the present invention, the under bump metal layer 23 includes a stacked titanium layer 231 and a copper layer 232, and the copper layer 232 is located between the metal pillar 24' and the titanium layer 231, and includes The circuit redistribution layer 28 is formed on the encapsulant 27 and the metal post 24' to electrically connect the semiconductor wafer 20.

綜上所述，相較於習知技術，由於本發明係先形成外露電極墊的介電層，接著形成凸塊底下金屬層與金屬層，再移除該凸塊底下金屬層與金屬層之部分厚度，所以能避免習知金屬柱高度不均之情況；此外，本發明係將半導體晶片接置於承載板上後，再形成包覆該半導體晶片與金屬柱的封裝膠體，然後研磨移除該封裝膠體與金屬柱的部分厚度以外露該金屬柱，因此本發明無需如習知般形成外露該金屬柱的封裝膠體開孔，故可避免習知之對位偏差問題，且不會受到半導體晶片的厚度不一致及黏著層的厚度不一致的影響。 In summary, compared with the prior art, the present invention first forms a dielectric layer of the exposed electrode pad, then forms a metal layer and a metal layer under the bump, and then removes the metal layer and the metal layer under the bump. Partial thickness, so that the height of the metal pillar is not uniform; in addition, the invention is to attach the semiconductor wafer to the carrier plate, and then form the encapsulant covering the semiconductor wafer and the metal post, and then remove the grinding. The portion of the encapsulant colloid and the metal pillar is exposed to the metal pillar. Therefore, the present invention does not need to form an encapsulation colloid that exposes the metal pillar as in the prior art, so that the conventional alignment deviation problem can be avoided and the semiconductor wafer is not affected. The thickness is inconsistent and the thickness of the adhesive layer is inconsistent.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

20‧‧‧半導體晶片 20‧‧‧Semiconductor wafer

201‧‧‧電極墊 201‧‧‧electrode pads

22‧‧‧介電層 22‧‧‧Dielectric layer

24’‧‧‧金屬柱 24’‧‧‧Metal column

25‧‧‧黏著層 25‧‧‧Adhesive layer

26‧‧‧承載板 26‧‧‧Loading board

260‧‧‧凹槽 260‧‧‧ Groove

27‧‧‧封裝膠體 27‧‧‧Package colloid

Claims (18)

一種半導體結構，係包括：半導體晶片，具有非作用面與相對該非作用面的作用面；複數形成於該作用面上之金屬柱；以及形成於該金屬柱與作用面之間及該金屬柱之側表面上之凸塊底下金屬層。 A semiconductor structure comprising: a semiconductor wafer having an inactive surface and an active surface opposite to the non-active surface; a plurality of metal pillars formed on the active surface; and a metal pillar and the active surface formed between the metal pillar and the metal pillar a metal layer under the bump on the side surface. 如申請專利範圍第1項所述之半導體結構，其中，該半導體晶片之作用面上復形成有介電層，該介電層並包覆該金屬柱與凸塊底下金屬層，且齊平於該金屬柱之端面。 The semiconductor structure of claim 1, wherein a dielectric layer is formed on the active surface of the semiconductor wafer, and the dielectric layer covers the metal pillar and the underlying metal layer of the bump, and is flush with The end face of the metal post. 如申請專利範圍第2項所述之半導體結構，其中，該介電層係為感光性絕緣層或光阻。 The semiconductor structure of claim 2, wherein the dielectric layer is a photosensitive insulating layer or a photoresist. 如申請專利範圍第1項所述之半導體結構，其中，該凸塊底下金屬層係包括層疊之鈦層與銅層，且該銅層係位於該金屬柱與該鈦層之間。 The semiconductor structure of claim 1, wherein the under bump metal layer comprises a stacked titanium layer and a copper layer, and the copper layer is between the metal pillar and the titanium layer. 如申請專利範圍第1項所述之半導體結構，復包括：承載板，係連接該半導體晶片之非作用面；以及封裝膠體，係形成於該承載板上，以包覆該半導體晶片，該封裝膠體之表面係齊平於該金屬柱之端面。 The semiconductor structure of claim 1, further comprising: a carrier plate connecting the inactive surface of the semiconductor wafer; and an encapsulant formed on the carrier plate to encapsulate the semiconductor wafer, the package The surface of the colloid is flush with the end face of the metal post. 如申請專利範圍第5項所述之半導體結構，其中，該承載板復具有凹槽，該半導體晶片係設於該凹槽的底面上，且該封裝膠體係形成於該凹槽中。 The semiconductor structure of claim 5, wherein the carrier plate has a recess, the semiconductor wafer is disposed on a bottom surface of the recess, and the encapsulant system is formed in the recess. 如申請專利範圍第5項所述之半導體結構，復包括線 路重佈層，係形成於該封裝膠體與金屬柱上，以電性連接該半導體晶片。 Such as the semiconductor structure described in claim 5, including the line A road redistribution layer is formed on the encapsulant and the metal post to electrically connect the semiconductor wafer. 一種半導體結構之製法，係包括：於承載板上接置具有相對之作用面與非作用面的半導體晶片，令該非作用面連接該承載板，該作用面上形成有複數金屬柱，該金屬柱與作用面之間及該金屬柱之側表面上係形成有凸塊底下金屬層；以及於該承載板上形成封裝膠體，以包覆該半導體晶片，該封裝膠體之表面係齊平於該金屬柱之端面。 The invention relates to a method for manufacturing a semiconductor structure, comprising: connecting a semiconductor wafer having an opposite active surface and an inactive surface on a carrier plate, and connecting the non-active surface to the carrier plate, wherein the working surface is formed with a plurality of metal pillars, the metal pillar Forming a under bump metal layer between the active surface and the side surface of the metal pillar; and forming an encapsulant on the carrier to cover the semiconductor wafer, the surface of the encapsulant being flush with the metal The end of the column. 如申請專利範圍第8項所述之半導體結構之製法，其中，形成該封裝膠體之步驟復包括研磨移除該封裝膠體與金屬柱的部分厚度。 The method of fabricating the semiconductor structure of claim 8, wherein the step of forming the encapsulant comprises grinding to remove a portion of the thickness of the encapsulant and the metal post. 如申請專利範圍第8項所述之半導體結構之製法，其中，該承載板復具有凹槽，該半導體晶片係設於該凹槽的底面上，且該封裝膠體係形成於該凹槽中。 The method of fabricating a semiconductor structure according to claim 8, wherein the carrier plate has a recess, the semiconductor wafer is disposed on a bottom surface of the recess, and the encapsulant system is formed in the recess. 如申請專利範圍第8項所述之半導體結構之製法，其中，該半導體晶片之作用面上復形成有介電層，該介電層並包覆該金屬柱與凸塊底下金屬層，且齊平於該金屬柱之端面。 The method of fabricating a semiconductor structure according to claim 8 , wherein a dielectric layer is formed on the active surface of the semiconductor wafer, and the dielectric layer covers the metal pillar and the underlying metal layer of the bump, and is Flat on the end of the metal column. 如申請專利範圍第11項所述之半導體結構之製法，其中，該介電層係為感光性絕緣層或光阻。 The method of fabricating a semiconductor structure according to claim 11, wherein the dielectric layer is a photosensitive insulating layer or a photoresist. 如申請專利範圍第8項所述之半導體結構之製法，其中，該凸塊底下金屬層係包括層疊之鈦層與銅層，該銅層係位於該金屬柱與該鈦層之間。 The method of fabricating a semiconductor structure according to claim 8, wherein the under bump metal layer comprises a stacked titanium layer and a copper layer, the copper layer being located between the metal pillar and the titanium layer. 如申請專利範圍第8項所述之半導體結構之製法，復包括於該封裝膠體與金屬柱上形成電性連接該半導體晶片的線路重佈層。 The method for fabricating a semiconductor structure according to claim 8 further comprises forming a circuit redistribution layer electrically connected to the semiconductor wafer on the encapsulant and the metal pillar. 一種半導體結構之製法，係包括：於半導體晶片之作用面上形成具有開孔的介電層，並令該作用面外露於該介電層之開孔；於該介電層、開孔孔壁與外露於該開孔中的作用面上形成凸塊底下金屬層；於該凸塊底下金屬層上形成金屬層；以及移除高於該介電層之部分金屬層與凸塊底下金屬層，以於該作用面上形成複數金屬柱。 A method for fabricating a semiconductor structure includes: forming a dielectric layer having an opening on an active surface of a semiconductor wafer, and exposing the active surface to an opening of the dielectric layer; and the dielectric layer and the opening hole wall Forming a metal layer under the bump on the active surface exposed in the opening; forming a metal layer on the metal layer under the bump; and removing a portion of the metal layer above the dielectric layer and the underlying metal layer of the bump, A plurality of metal pillars are formed on the active surface. 如申請專利範圍第15項所述之半導體結構之製法，其中，該凸塊底下金屬層係包括層疊之鈦層與銅層，該銅層係位於該金屬柱與該鈦層之間。 The method of fabricating a semiconductor structure according to claim 15, wherein the under bump metal layer comprises a stacked titanium layer and a copper layer, the copper layer being located between the metal pillar and the titanium layer. 如申請專利範圍第15項所述之半導體結構之製法，其中，移除該金屬層與凸塊底下金屬層之方式係為研磨。 The method of fabricating a semiconductor structure according to claim 15, wherein the metal layer and the underlying metal layer of the bump are removed by grinding. 如申請專利範圍第15項所述之半導體結構之製法，其中，於移除高於該介電層之金屬層與凸塊底下金屬層之步驟後，復包括移除該介電層。 The method of fabricating a semiconductor structure according to claim 15, wherein the step of removing the metal layer above the dielectric layer and the underlying metal layer of the bump includes removing the dielectric layer.
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