TWM462947U - Package substrate - Google Patents

Abstract

Disclosed is a package substrate, comprising a substrate body having electrical contact pads formed thereon, an insulating protection layer disposed on the substrate body and the electrical contact pads, and conductive bumps formed on the insulating protection layer for corresponding to the electrical contact pads, wherein each of the conductive bumps is electrically connected to a respective electrical contact pads by two or more conductive pillars which are formed on conductive bumps, thereby preventing the top central area of the conductive bumps from collapsing and caving in and thus resulting in defective electrical contact between the bumps and electronic components.

Description

Package substrate

The present invention relates to a package substrate, and more particularly to a package substrate having conductive bumps.

FIG. 1 is a schematic cross-sectional view of a package substrate 1 for carrying a semiconductor wafer. The package substrate 1 includes a substrate body 10, a plurality of electrical contact pads 11, an insulating protective layer 12, and a plurality of conductive layers. Bump 13.

The substrate body 10 has at least one dielectric layer 100 , a circuit layer 101 disposed on the dielectric layer 100 , and a plurality of conductive vias 102 disposed in the dielectric layer 100 . The electrical contact pad 11 is disposed on the dielectric layer 100 of the outermost layer, and the circuit layer 101 and the electrical contact pad 11 are electrically connected by the conductive via hole 102. The insulating protective layer 12 is formed on the outermost layer of the dielectric layer 100 and each of the electrical contact pads 11, and an opening 120 is formed at a position corresponding to each of the electrical contact pads 11 to make each of the electrical properties. The contact pads 11 are correspondingly exposed to the openings 120. The conductive bumps 13 are formed in the openings 120 to electrically connect the electrical contact pads 11 , and the conductive bumps 13 have the pillars 130 in the openings 120 . The single conductive bumps 13 are electrically connected to the single one of the electrical contact pads 11 by a single pillar 130.

However, in the conventional package substrate 1, since each of the electrical contact pads 11 corresponds to only one opening 120, and due to the process characteristics of the electroplated copper material, when the conductive bumps 13 are formed by electroplating, the openings 120 and Around the opening due to the height drop The problem is that when the pillar 130 is plated, the height of the side of the pillar 130 is higher than the center of the pillar 130, so that a recess K is formed in the middle of the top surface of the conductive bump 13, so that the conductive bump 13 The top surface cannot be flattened, so that the conductive bumps 13 cannot effectively combine electronic components such as wafers or carrier boards in subsequent processes, thereby affecting the quality of the electrical connections.

However, how to overcome the problem of the top surface depression of the conductive bumps of the prior art is an important issue.

In order to solve the above problems in the prior art, the present invention provides a package substrate, wherein a plurality of openings are formed on the insulating protection layer, so that a single electrical contact pad corresponds to at least two of the openings, and the conductive bumps The conductive pillars are located in each of the openings, so that a single conductive bump is electrically connected to the single electrical contact pad by at least two conductive pillars.

It can be seen from the above that in the process of electroplating conductive bumps, when the conductive pillars are plated, part of the intermediate metal material of the conductive bumps is plated together, that is, when the sides of the conductive bumps begin to form. In the case of a metal material, a part of the metal material is plated in the middle of the conductive bump, and then the characteristics of the electroplating process are used to make the top surface of the conductive bump have a flat surface. Therefore, compared with the prior art, the present invention can avoid the formation of a depression in the middle of the top surface of the conductive bump, so that in the subsequent process, the conductive bump can effectively combine the electronic components and improve the quality of the electrical connection.

The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easily understand the contents disclosed in the present specification. Other advantages and effects of this creation.

It is to be understood that the structure, the proportions, the size and the like of the drawings are only used in conjunction with the disclosure of the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effectiveness and the purpose of the creation. The technical content revealed by the creation can be covered. In the meantime, the terms "upper", "three" and "one" as used in this specification are for convenience of description only, and are not intended to limit the scope of the creation of the creation, or the relative relationship may be changed or Adjustments, if there is no material change in the content of the technology, are also considered to be the scope of implementation of this creation.

The method of manufacturing the package substrate 2 of the present invention will be described in detail below with reference to FIGS. 2A to 2C.

As shown in FIG. 2A, a substrate body 20 having a plurality of electrical contact pads 21 is provided, and at least one dielectric layer 200 and a circuit disposed on the dielectric layer 200 are disposed on opposite sides of the substrate body 20. The layer 201 and the plurality of conductive vias 202 disposed in the dielectric layer 200 and electrically connected to the circuit layer 201 and the electrical contact pads 21 are disposed.

In the present embodiment, the structures on the opposite sides of the substrate body 20 are substantially the same as the process, and therefore only one side will be described below.

Then, an insulating protective layer 22 is formed on the outermost dielectric layer 200 of the substrate body 20 and the electrical contact pads 21, and a plurality of openings 220 are formed on the insulating protective layer 22 to make the electrical contacts. Part of the mat 21 The surface is exposed to the openings 220, and the single electrical contact pads 21 correspond to at least two of the openings 220.

In the embodiment, the insulating protective layer 22 is a solder resist or a dielectric material.

As shown in FIG. 2B, a resist layer 24 is formed on the insulating protective layer 22, and the resist layer has an opening region 240 corresponding to the electrical contact pad 21, and the openings 220 are exposed.

Then, the conductive bumps 23 are formed in the opening region 240 by electroplating, and the conductive pillars 230 are formed in each of the openings 220, so that the single conductive bumps 23 are electrically connected by at least two of the conductive pillars 230. A single one of the electrical contact pads 21 is connected.

In the embodiment, the conductive bumps 23 and the conductive pillars 230 are made of copper.

As shown in FIG. 2C, the resist layer 24 is removed to complete the process of fabricating the conductive bumps 23.

In this embodiment, as shown in FIG. 2C', a single one of the conductive bumps 23 is electrically connected to the single one of the electrical contact pads 21 by three conductive pillars 230. However, the number of the conductive posts 230 connected to the electrical contact pads 21 is not limited to the above.

The present invention utilizes the characteristics of the electroplating process, and the conductive pillars 230 are formed on the electrical contact pads 21, so that when the conductive pillars 230 are plated, a part of the intermediate metal materials of the conductive bumps 23 are collectively plated, that is, When the metal bump is formed on the side of the conductive bump 23, a part of the metal material is plated in the middle of the conductive bump 23. Therefore, the edge and the middle of the conductive bump 23 can be predetermined When the height is flush, the design of the conductive pillar 230 can effectively solve the problem of the recession of the prior art.

Moreover, by the design of the conductive pillar 230, the conductive bump 23 can be flat at a predetermined height (ie, maintaining a predetermined bump strength), so that the conductive bump 23 can be formed in a subsequent process. It can effectively combine electronic components such as chips or carrier boards to improve the quality of electrical connections.

The package substrate 2 of the present invention comprises: a substrate body 20 having a plurality of electrical contact pads 21, an insulating protective layer 22 disposed on the substrate body 20 and the electrical contact pads 21, and correspondingly disposed on the substrate The plurality of conductive bumps 23 on the insulating protective layer 22 of the contact pads 21.

The substrate body 20 has at least one dielectric layer 200, a circuit layer 201 disposed on the dielectric layer 200, and a plurality of conductive blind vias disposed in the dielectric layer 200 and electrically connected to the circuit layer 201. 202, and the electrical contact pad 21 and the insulating protective layer 22 are disposed on the dielectric layer 200 of the outermost layer.

The insulating protective layer 22 is a solder resist layer, and a plurality of openings 220 are formed thereon to expose the electrical contact pads 21 to the openings 220, and the single one of the electrical contact pads 21 corresponds to At least two of the openings 220.

The conductive bumps 23 have the conductive pillars 230 in the openings 220 such that the conductive bumps 23 are electrically connected to the single one of the electrical contact pads 21 by at least two of the conductive pillars 230. The conductive pillar 230 is a metal pillar, such as a copper pillar.

The other way of forming the conductive pillars 230, as in the process of FIG. 2B', can form the conductive bumps by filling the openings 220 with the conductive paste and the surface of the conductive paste is flush with the insulating protective layer 22. 23 process and above The process is similar and will not be described in detail. The conductive paste may be a conductive material such as a copper paste, a solder paste or a silver paste.

In summary, the package substrate of the present invention is mainly designed by the conductive pillars, so that a single conductive bump is electrically connected to a single electrical contact pad by at least two conductive pillars to form a conductive bump. The formation of the recess on the top surface of the conductive bump can prevent the problem that the conductive bump and the electronic component are in poor contact, thereby effectively reducing the risk of electrical defects and improving the reliability of the product.

The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention. Any person skilled in the art can implement the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. Moreover, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of this creation should be as listed in the scope of patent application described later.

1,2‧‧‧Package substrate

10,20‧‧‧Substrate body

100,200‧‧‧ dielectric layer

101, 201‧‧‧ circuit layer

102,202‧‧‧ conductive blind holes

11,21‧‧‧Electrical contact pads

12,22‧‧‧Insulating protective layer

120,220‧‧‧ openings

13,23‧‧‧Electrical bumps

130‧‧‧Cylinder

230‧‧‧conductive column

24‧‧‧resist

240‧‧‧Open area

K‧‧‧ recess

1 is a schematic cross-sectional view showing a conventional package substrate; FIGS. 2A to 2C are schematic cross-sectional views showing a method of fabricating a package substrate; FIG. 2B' is a view showing another embodiment of the conductive pillar of the present invention; and 2C 'The figure is a three-dimensional schematic diagram of the electrical contact pads, conductive bumps and conductive columns of the creation.

2‧‧‧Package substrate

20‧‧‧Substrate body

21‧‧‧Electrical contact pads

22‧‧‧Insulating protective layer

23‧‧‧Electrical bumps

230‧‧‧conductive column

Claims (6)

A package substrate includes: a substrate body having a plurality of electrical contact pads; an insulating protective layer disposed on the substrate body and the electrical contact pads; and a plurality of openings are formed on the insulating protective layer to Exposing the electrical contact pads to the openings, and the one of the electrical contact pads corresponds to at least two of the openings; and the conductive bumps are disposed on the insulating protective layer corresponding to the electrical contact pads And the conductive bumps have conductive pillars in each of the openings, such that a single one of the conductive bumps is electrically connected to the single one of the electrical contact pads by at least two of the conductive pillars. The package substrate of claim 1, wherein the substrate body has at least one dielectric layer, a circuit layer disposed on the dielectric layer, and is disposed in the dielectric layer and electrically connected to the circuit A plurality of conductive blind holes of the layer. The package substrate of claim 2, wherein the electrical contact pad and the insulating protective layer are disposed on the dielectric layer of the outermost layer. The package substrate of claim 1 or 3, wherein the insulating protective layer is a solder resist material or a dielectric material. The package substrate of claim 1, wherein the conductive pillar is a metal pillar. The package substrate of claim 5, wherein the metal pillar is a copper pillar.