TW201701419A - Package structure and the manufacture thereof - Google Patents

Abstract

Provided is a package structure, comprising: a dielectric layer, a first circuit layer embedded in the dielectric layer while being exposed from the surface of the dielectric layer, a plurality of conductive bumps disposed on the first circuit layer, and a first insulating protective layer formed on the dielectric layer, conductive bumps and the first circuit layer, wherein partial surfaces of the conductive bumps are exposed from the first insulating protective layer such that the conductive bumps are exposed from the first insulating protective layer while the first circuit layer is still covered by the first insulating protective layer to thereby prevent bridging between the solder material and the first circuit layer when disposing electronic elements thereon and thus increase good yield. This invention further provides a method for fabricating the package structure as described above.

Description

Package structure and its manufacturing method

The invention relates to a package structure, in particular to a package structure capable of improving product yield and a preparation method thereof.

With the rapid development of the electronics industry, many high-end electronic products are gradually moving toward light, thin, short, and small high integration. With the evolution of packaging technology, the packaging technology of wafers is becoming more and more diversified. The size or volume of the package is also shrinking, so that the semiconductor package is light, thin and short.

1 is a cross-sectional view of a conventional package structure 1. As shown in FIG. 1 , the package structure 1 includes a package substrate 10 , a circuit layer 11 embedded in the package substrate 10 , and a package layer 10 disposed on the package substrate 10 and electrically connected by a plurality of solder bumps 13 . The semiconductor wafer 12 of the wiring layer 11.

However, in the conventional package structure 1, since the line pitch of the circuit layer 11 is getting smaller and smaller, the pitch of the solder bumps 13 is also increasingly reduced. Therefore, after the package substrate 10 is attached to the semiconductor wafer 12, the solder bumps are formed. The solder of block 13 is easily bridged with the lines or contact pads of adjacent circuit layers 11 after reflow, resulting in a short circuit, resulting in a decrease in product yield.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned prior art, the present invention provides a package structure comprising: a dielectric layer having opposite first and second surfaces; and a first circuit layer embedded in the dielectric layer and exposed On the first surface; a plurality of conductive bumps are disposed on the first circuit layer; and a first insulating protective layer is formed on the first surface of the dielectric layer, the conductive bumps and the first circuit layer And a part of the surface of the conductive bump is exposed to the first insulating protective layer.

In the foregoing package structure, the second circuit layer is formed on the second surface of the dielectric layer and electrically connected to the first circuit layer.

The invention provides a method for manufacturing a package structure, comprising: providing a carrier; forming a first circuit layer on the carrier; forming a dielectric layer on the carrier, so that the dielectric layer covers the first a circuit layer; a second circuit layer is formed on the dielectric layer, and the second circuit layer is electrically connected to the first circuit layer; the carrier is removed, and a plurality of conductive bumps are formed on the first circuit layer; And forming a first insulating protective layer on the dielectric layer, the conductive bump and the first circuit layer, and exposing a portion of the surface of the conductive bump to the first insulating protective layer.

In the above method, the conductive bump is formed by electroplating.

In the above method, a part of the material of the first insulating protective layer is removed by development, and a part of the surface of the conductive bump is exposed to the first insulating protective layer.

In the foregoing package structure and method of manufacturing the same, the conductive bump protrudes from the first insulating protective layer.

In the foregoing package structure and method of manufacturing the same, the first insulating protective layer is formed with a recess, and the conductive bumps are located in the recess. The method further includes disposing at least one electronic component on the first insulating protective layer, and forming a primer between the first insulating protective layer and the electronic component, so that the underfill is filled in the recess.

In the foregoing package structure and method of fabricating the same, the second insulating protective layer is formed on the dielectric layer and the second circuit layer. For example, the second insulating protective layer is a solder resist layer, and a part of the surface of the second wiring layer is exposed to the second insulating protective layer. Also included is the formation of a plurality of conductive elements on the second circuit layer.

In the above package structure and method of manufacturing the same, the material forming the dielectric layer is a molded resin, a prepreg, an ABF or a photosensitive dielectric.

In the foregoing package structure and method of manufacturing the same, the first insulating protective layer is a solder resist layer.

In the above package structure and method of manufacturing the same, at least one electronic component is disposed on the first insulating protective layer, and the electronic component is electrically connected to the conductive bumps. The method further includes forming an encapsulant on the first insulating protective layer to encapsulate the encapsulant to the electronic component, or comprising forming a primer between the first insulating protective layer and the electronic component.

The present invention further provides a package structure, comprising: a dielectric layer having a first surface and a second surface opposite to each other, wherein the material forming the dielectric layer is ABF; and the first circuit layer is embedded in the The dielectric layer is exposed to the first surface.

In the foregoing package structure, the second circuit layer is formed on the second surface of the dielectric layer and electrically connected to the first circuit layer.

In the foregoing package structure, a carrier is included to form the first circuit layer and the dielectric layer thereon.

In the foregoing package structure, a plurality of conductive bumps are included on the first circuit layer.

It can be seen that, in the package structure of the present invention, the conductive bump is formed on the first circuit layer, and the conductive bump is exposed to the first insulating protective layer, and the first circuit layer is formed. Still covered by the first insulating protective layer, after the electronic component is connected, the problem that the solder is bridged with the first circuit layer can be avoided, thereby avoiding a short circuit and thereby improving product yield.

1,2,2',2",2a,2a',2a"‧‧‧Package structure

10‧‧‧Package substrate

11‧‧‧Line layer

12‧‧‧Semiconductor wafer

13,260‧‧‧ solder bumps

20‧‧‧Dielectric layer

20a‧‧‧ first surface

20b‧‧‧second surface

200‧‧ ‧ blind hole

21‧‧‧First line layer

22‧‧‧Second circuit layer

23‧‧‧Electrical bumps

220‧‧‧Electrical conductor

24,24’‧‧‧first insulating coating

240‧‧‧ recess

25‧‧‧Second insulation protection layer

250‧‧‧ openings

26‧‧‧Electronic components

27‧‧‧Package colloid

28‧‧‧Conductive components

29‧‧‧Bottom glue

9‧‧‧Carrier

9a, 9b‧‧‧ surface

90‧‧‧ board

91‧‧‧metal layer

T, t‧‧‧ thickness

1 is a schematic cross-sectional view of a conventional package structure; and 2A to 2H are schematic cross-sectional views showing a method of fabricating the package structure of the present invention; wherein the 2G' image is another aspect of the 2Gth image, 2H' and 2H" are other aspects of the 2H diagram.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention.

It is to be understood that the structure, the proportions, the size and the like of the drawings are only used in conjunction with the disclosure of the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effectiveness and the purpose of the creation. The technical content revealed by the creation can be covered. In the meantime, the terms "upper", "one", "first" and "second" as used in this specification are for convenience only, and are not intended to limit the scope of the creation. Changes or adjustments in their relative relationship are considered to be within the scope of the creation of the creation of the product without substantial changes.

Please refer to FIGS. 2A to 2H for a schematic cross-sectional view showing the manufacturing method of the package structure 2 of the present invention.

As shown in Fig. 2A, a carrier member 9 having opposite surfaces 9a, 9b is provided and a first wiring layer 21 is formed on both surfaces 9a, 9b of the carrier member 9.

In this embodiment, the two surfaces 9a, 9b of the carrier 9 are metal surfaces. Specifically, the carrier member 9 has a plate body 90 such as a metal plate, a semiconductor wafer or a glass plate, and a metal layer 91 disposed on both sides of the plate body 90, such as a copper foil, and the plate body 90 and the metal layer. A bonding layer such as a release film, an adhesive material or an insulating material may be provided between the 91s (not shown). Furthermore, the first wiring layer 21 is formed by electroplating or deposition.

As shown in FIG. 2B, a dielectric layer 20 is formed on both surfaces 9a, 9b of the carrier 9 such that the dielectric layer 20 covers the first wiring layer 21.

In the present embodiment, the material of the dielectric layer 20 is formed, for example, a molding compound, a prepreg, an ABF (Ajinomoto Build-up Film) or a photosensitive dielectric material, but is not limited thereto.

Moreover, the dielectric layer 20 has opposite first and second surfaces 20a, 20b, and the dielectric layer 20 is bonded to the two surfaces 9a, 9b of the carrier 9 with its first surface 20a.

Moreover, corresponding to the second surface 20b, a plurality of blind holes 200 are formed in the dielectric layer 20 to expose a part of the surface of the first circuit layer 21 to the blind holes 200. For example, the blind vias 200 are formed by laser, exposure development, etching, or the like.

As shown in FIG. 2C, a patterned conductive material is formed on the second surface 20b of the dielectric layer 20 such that the conductive material is used as the second wiring layer 22, and the conductive material is formed in the blind via 200. The second circuit layer 22 has the electrical conductors 220 extending in the dielectric layer 20 such that the second circuit layer 22 is electrically connected to the first circuit layer 21 by the electrical conductors 220.

As shown in FIG. 2D, the first wiring layer 21 is exposed except for the removal of the carrier 9.

In the embodiment, the first circuit layer 21 is flush with the first surface 20a of the dielectric layer 20.

As shown in FIG. 2E, a plurality of conductive bumps 23 are formed on the first wiring layer 21.

In the embodiment, the conductive bumps 23 are formed by electroplating copper.

Forming a first insulating protective layer 24 on the dielectric layer as shown in FIG. 2F a first surface 20a, a conductive bump 23 and the first wiring layer 21, such that the first insulating protective layer 24 covers the first wiring layer 21 and the conductive bump 23, and forms a second insulating protective layer 25 on the second surface 20b of the dielectric layer 20 and the second wiring layer 22 such that the second insulating protective layer 25 covers the second wiring layer 22.

In the embodiment, the first insulating protective layer 24 and the second insulating protective layer 25 are solder resist layers.

As shown in FIG. 2G, a portion of the first and second insulating protective layers 24, 25 are removed, such that a portion of the surface of the conductive bump 23 is exposed to the first insulating protective layer 24, and the first circuit layer 21 is not exposed to the first insulating protective layer 24, and part of the surface of the second wiring layer 22 is exposed to the second insulating protective layer 25.

In this embodiment, a portion of the material of the first insulating protective layer 24 is removed by a developing method, so that the conductive bumps 23 protrude from the first insulating protective layer 24 (ie, the top surface of the conductive bumps 23 and A portion of the side is exposed to the first insulating protective layer 24), and the first insulating protective layer 24 still covers the first wiring layer 21.

Furthermore, the second insulating protective layer 25 is formed with a plurality of openings 250 for exposing a portion of the surface of the second wiring layer 22; or, by the surface of the second insulating protective layer 25, the second wiring layer is flushed The top surface of the second circuit layer 22 is exposed to the second insulating protective layer 25.

In another embodiment, as shown in FIG. 2G′, the first insulating protective layer 24 ′ around the conductive bumps 23 may be retained, so that the first insulating protective layer 24 ′ is formed with the concave portion 240 , and The conductive bumps 23 are located in the recess The first insulating protective layer 24' is exposed to the first insulating protective layer 24', so that the first insulating protective layer 24' has a structure having different thicknesses T, t.

As shown in FIG. 2H, at least one electronic component 26 is disposed on the first insulating protective layer 24, and the electronic component 26 is electrically connected to the conductive bumps 23, and the encapsulant 27 is formed on the first insulating layer. The encapsulant 27 covers the electronic component 26 on the protective layer 24. Thereafter, a plurality of conductive elements 28, such as solder balls, are formed on the second wiring layer 22 in the opening 250.

In this embodiment, the electronic component 26 is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.

Moreover, the electronic component 26 is electrically connected to the conductive bump 23 by a plurality of solder bumps 260, and the encapsulant 27 covers the conductive bumps 23 and the solder bumps 260. In other manners, the electronic component 26 can be electrically connected to the conductive bump 23 by wire bonding as needed, which is not shown.

In addition, as shown in FIG. 2H', a primer 29 may be formed between the first insulating protective layer 24 and the electronic component 26, so that the primer 29 covers the conductive bumps 23 and the solder bumps. The electronic component 26 is fixed 260, and the encapsulant 27 is formed on the first insulating protective layer 24, so that the encapsulant 27 covers the electronic component 26 and the primer 29.

Further, as shown in Fig. 2H", if the process of the 2G' drawing is continued, the primer 29 is formed in the recess 240 to restrict the flow of the primer 29.

The method of the present invention forms the conductive bump 23 on the first circuit layer 21, and then forms the first insulating protective layer 24, and then removes the first portion. The insulating protective layer 24 exposes the conductive bumps 23, and the first circuit layer 21 is still covered by the first insulating protective layer 24. Therefore, after the electronic component 26 is attached, the solder of the solder bumps 260 can be avoided. The problem of bridging with the first circuit layer 21 can avoid short circuits and improve product yield.

The present invention provides a package structure 2, 2', 2", comprising: a dielectric layer 20, a first circuit layer 21, a plurality of conductive bumps 23, a first insulating protective layer 24, 24', a second The circuit layer 22 and a second insulating protective layer 25.

The dielectric layer 20 has a first surface 20a and a second surface 20b opposite to each other, and the material forming the dielectric layer 20 is a molded resin, a prepreg, an ABF or a photosensitive dielectric.

The first circuit layer 21 is embedded in the dielectric layer 20 and exposed on the first surface 20a, and the first circuit layer 21 is flush with the first surface 20a of the dielectric layer 20.

The conductive bumps 23 are located on the first surface 20a of the dielectric layer 20 and bonded to the first circuit layer 21.

The first insulating protective layer 24, 24' is a solder resist layer formed on the first surface 20a of the dielectric layer 20, the conductive bump 23 and the first wiring layer 21, and the conductive bump A portion of the surface of the portion 23 is exposed to the first insulating protective layer 24, 24'.

The second circuit layer 22 is formed on the second surface 20b of the dielectric layer 20 and electrically connected to the first circuit layer 21.

The second insulating protective layer 25 is a solder resist layer formed on the second surface 20b of the dielectric layer 20 and the second wiring layer 22, and the second A portion of the surface of the wiring layer 22 is exposed to the second insulating protective layer 25.

In one embodiment, the conductive bumps 23 protrude from the first insulating protective layer 24, 24'.

In one embodiment, the first insulating protective layer 24' is formed with a recess 240, and the conductive bumps 23 are located in the recess 240. For example, the package structure 2 ′′ may include at least one electronic component 26 disposed on the first insulating protective layer 24 ′ and a primer 29 formed between the first insulating protective layer 24 ′ and the electronic component 26 . And the primer 29 is formed in the recess 240.

In one embodiment, the package structure 2, 2', 2" includes a plurality of conductive elements 28 formed on the second circuit layer 22.

In one embodiment, the package structure 2, 2' includes at least one electronic component 26 disposed on the first insulating protective layer 24, and the electronic component 26 is electrically connected to the conductive bumps 23. For example, the package structure 2 may include an encapsulant 27 formed on the first insulating protective layer 24, and the encapsulant 27 covers the electronic component 26. Alternatively, the package structure 2' may include a primer 29 formed between the first insulating protective layer 24 and the electronic component 26.

The present invention further provides a package structure 2a, 2a', 2a", as shown in Figures 2C through 2E, comprising a dielectric layer 20 and a first wiring layer 21.

The dielectric layer 20 has a first surface 20a and a second surface 20b opposite to each other, and the material forming the dielectric layer 20 is ABF.

The first circuit layer 21 is embedded in the dielectric layer 20 and exposed to the first surface 20a.

In an embodiment, the package structure 2a, 2a', 2a" includes a second line The layer 22 is formed on the second surface 20b of the dielectric layer 20 and electrically connected to the first circuit layer 21.

In one embodiment, the package structure 2a' includes a carrier member 9 on which the first circuit layer 21 and the dielectric layer 20 are formed.

In one embodiment, the package structure 2a" includes a plurality of conductive bumps 23 disposed on the first circuit layer 21.

In summary, the package structure of the present invention is formed by forming the conductive bump on the first circuit layer, and then forming the first insulating protective layer to expose the conductive bump, and the first The circuit layer is still covered by the first insulating protective layer, so that after the electronic component is connected, the solder of the solder bump can be prevented from bridging with the first circuit layer, thereby avoiding a short circuit and improving the product. rate.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

2‧‧‧Package structure

20‧‧‧Dielectric layer

21‧‧‧First line layer

22‧‧‧Second circuit layer

23‧‧‧Electrical bumps

24‧‧‧First insulation protection layer

25‧‧‧Second insulation protection layer

250‧‧‧ openings

26‧‧‧Electronic components

260‧‧‧ solder bumps

27‧‧‧Package colloid

28‧‧‧Conductive components

Claims (32)

A package structure includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed on the first surface; a plurality of conductive bumps, The first insulating layer is formed on the first surface of the dielectric layer, the conductive bump and the first circuit layer, and a part of the surface of the conductive bump is exposed The first insulating protective layer. The package structure of claim 1, wherein the conductive bump protrudes from the first insulating protective layer. The package structure of claim 1, wherein the first insulating protective layer is formed with a recess, and the conductive bumps are located in the recess. The package structure of claim 3, further comprising at least one electronic component disposed on the first insulating protective layer, and a primer formed between the first insulating protective layer and the electronic component, and The primer is filled in the recess. The package structure of claim 1, further comprising a second circuit layer formed on the second surface of the dielectric layer and electrically connected to the first circuit layer. The package structure of claim 5, further comprising a second insulating protective layer formed on the second surface of the dielectric layer and the second circuit layer, and a portion of the surface of the second circuit layer is exposed In the second Insulation protection layer. The package structure of claim 6, wherein the second insulating protective layer is a solder resist layer. The package structure of claim 5, comprising a plurality of conductive elements formed on the second circuit layer. The package structure of claim 1, further comprising at least one electronic component disposed on the first insulating protective layer, and the electronic component is electrically connected to the conductive bumps. The package structure as claimed in claim 9 further comprising an encapsulant formed on the first insulating protective layer, and the encapsulant encapsulates the electronic component. The package structure of claim 9, comprising a primer formed between the first insulating protective layer and the electronic component. The package structure according to claim 1, wherein the material for forming the dielectric layer is a molded resin, a prepreg, an ABF or a photosensitive dielectric. The package structure of claim 1, wherein the first insulating protective layer is a solder resist layer. A method for fabricating a package structure includes: providing a carrier member; forming a first circuit layer on the carrier member; forming a dielectric layer on the carrier member to allow the dielectric layer to cover the first circuit layer; forming a second circuit layer on the dielectric layer, and the second circuit layer Electrically connecting the first circuit layer; removing the carrier and forming a plurality of conductive bumps on the first circuit layer; and forming a first insulating protective layer on the dielectric layer, the conductive bumps, and the first line And forming a portion of the surface of the conductive bump exposed to the first insulating protective layer. The method of fabricating a package structure according to claim 14, wherein the conductive bump protrudes from the first insulating protective layer. The method of fabricating a package structure according to claim 14, wherein the conductive bump is formed by electroplating. The method of fabricating a package structure according to claim 14, wherein the first insulating protective layer is formed with a recess, and the conductive bumps are located in the recess. The method for manufacturing a package structure according to claim 17 further comprising: providing at least one electronic component on the first insulating protective layer, and forming a primer between the first insulating protective layer and the electronic component; The primer is filled in the recess. The method for manufacturing a package structure according to claim 14, further comprising removing a portion of the material of the first insulating protective layer by developing, exposing a portion of the surface of the conductive bump to the first insulating protective layer. The method of fabricating the package structure of claim 14, further comprising forming a second insulating protective layer on the dielectric layer and the second wiring layer. The method for manufacturing a package structure as described in claim 20, A portion of the surface of the second circuit layer is exposed to the second insulating protective layer. The method of fabricating the package structure of claim 21, comprising forming a plurality of conductive elements on the second circuit layer. The method of manufacturing a package structure according to claim 20, wherein the second insulating protective layer is a solder resist layer. The method of fabricating the package structure of claim 14, further comprising providing at least one electronic component on the first insulating protective layer, and the electronic component is electrically connected to the conductive bumps. The method for manufacturing a package structure according to claim 24, further comprising forming an encapsulant on the first insulating protective layer, so that the encapsulant encapsulates the electronic component. The method for fabricating a package structure according to claim 24, further comprising forming a primer between the first insulating protective layer and the electronic component. The method for fabricating a package structure according to claim 14, wherein the material for forming the dielectric layer is a molded resin, a prepreg, an ABF or a photosensitive dielectric. The method of fabricating a package structure according to claim 14, wherein the first insulating protective layer is a solder resist layer. A package structure includes: a dielectric layer having opposite first and second surfaces, and the material forming the dielectric layer is ABF; and a first circuit layer embedded in the dielectric layer And exposed to the first surface. The package structure of claim 29, further comprising a second circuit layer formed on the second surface of the dielectric layer and electrically connected to the first circuit layer. The package structure of claim 29, further comprising a carrier for forming the first circuit layer and the dielectric layer thereon. The package structure as claimed in claim 29, further comprising a plurality of conductive bumps disposed on the first circuit layer.