CN109326569A - Potted element and preparation method thereof - Google Patents
Potted element and preparation method thereof Download PDFInfo
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- CN109326569A CN109326569A CN201711433952.2A CN201711433952A CN109326569A CN 109326569 A CN109326569 A CN 109326569A CN 201711433952 A CN201711433952 A CN 201711433952A CN 109326569 A CN109326569 A CN 109326569A
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- layer
- conductive pad
- protective layer
- potted element
- conductive
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000010410 layer Substances 0.000 claims description 238
- 239000011241 protective layer Substances 0.000 claims description 83
- 238000004519 manufacturing process Methods 0.000 claims description 56
- 239000000463 material Substances 0.000 claims description 40
- 238000004140 cleaning Methods 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 44
- 230000008569 process Effects 0.000 description 24
- 238000012545 processing Methods 0.000 description 17
- 238000005520 cutting process Methods 0.000 description 16
- 239000012790 adhesive layer Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 7
- 239000007769 metal material Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000006378 damage Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000012797 qualification Methods 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 229920000139 polyethylene terephthalate Polymers 0.000 description 3
- 239000005020 polyethylene terephthalate Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KKEYFWRCBNTPAC-UHFFFAOYSA-N Terephthalic acid Chemical compound OC(=O)C1=CC=C(C(O)=O)C=C1 KKEYFWRCBNTPAC-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- -1 for example Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 241000931526 Acer campestre Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229920000297 Rayon Polymers 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002471 indium Chemical class 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of potted element and preparation method thereof, which includes conductive pad, protection block and rewiring layer.Protection block is set on conductive pad.It reroutes layer to be set on protection block, and conductive pad is by protecting block to be electrically connected to rewiring layer.
Description
Technical field
The present invention relates to a kind of potted element with and preparation method thereof, more particularly to it is a kind of using panel grade fan-out-type seal
Fill (fan-out panel level package, FOPLP) technology potted element with and preparation method thereof.
Background technique
In electronic package technology, wafer scale fan-out package (fan-out wafer level package,
FOWLP) technology is by fabrication of electronic components on wafer, being packaged and cut.However, since large scale common now is brilliant
Only about 300 millimeters (mm) of diameter of a circle, therefore the number of electronic components that can make on wafer encapsulation simultaneously is limited, industry thus
It develops panel grade fan-out package (FOPLP) technology and replaces Wafer level packaging.
In existing panel grade fan-out package technology, layer (redistribution layer) system can will be generally rerouted
Make on hard support plate, then electronic component is set to and is rerouted on layer, then just removes hard support plate from rewiring layer.
However, reroute layer lower surface other than conductive pad also have reroute layer dielectric layer expose, therefore cleaning with
Etching process dielectric layer will be easy that the structure in rewiring layer is caused to be destroyed by over etching relative to conductive pad,
Influence the characteristic of entire potted element.In view of this, traditional panel grade fan-out package method remains to be further improved.
Summary of the invention
One embodiment of the invention provides a kind of potted element, including conductive pad, protection block and rewiring layer.Protection
Block is set on conductive pad.It reroutes layer to be set on protection block, and conductive pad is by protecting block to be electrically connected to weight cloth
Line layer.
The embodiment of the present invention also provides a kind of production method of potted element.Firstly, in forming release layer on support plate.So
Afterwards, in forming protective layer and conductive pad on release layer, wherein conductive pad is set on the side of protective layer.Then, in protective layer
Layer is rerouted with being formed on conductive pad.Then, release layer and support plate, and etch protection layer are removed.
Potted element provided by the invention with and preparation method thereof be formed release layer and formed reroute layer between into
One step forms the protective layer of whole face covering, is formed by with protection and reroutes layer from being damaged in manufacturing process for cleaning or etch process
It is bad, and then make manufacturing process for cleaning that can effectively clean the lower surface of protective layer or conductive pad.Whereby, it can help to stick together conducting sphere
In the lower surface of conductive pad, to avoid the engagement because of conducting sphere and conductive pad it is bad caused by high value or because conducting sphere is from leading
Electrical pad falls off generated open circuit, and then improves product qualification rate.
Detailed description of the invention
Fig. 1, Fig. 2 are the schematic diagram of manufacturing method of the potted element of first embodiment of the invention；
Fig. 3~Fig. 5 is the schematic diagram of manufacturing method of the potted element of second embodiment of the invention；
Fig. 6, Fig. 7 are the schematic diagram of manufacturing method of the potted element of third embodiment of the invention；
Fig. 8, Fig. 9 are the schematic diagram of manufacturing method of the potted element of fourth embodiment of the invention；
Figure 10 is the schematic diagram for the example that potted element of the invention is applied to electronic equipment.
Description of symbols: 100,300,600- potted element；102- support plate；104- release layer；106,306,426b- is led
Electrical pad；108,308,426a, 508- protective layer；108a, 508a- protect block；110- reroutes layer；The first dielectric layer of 112a-；
The second dielectric layer of 112b-；112c- third dielectric layer；112v- through-hole；The first patterned conductive layer of 114a-；The second pattern of 114b-
Change conductive layer；114c- third patterned conductive layer；1141- conducting wire；1142- connection pad；116- grafting material；118- electronic component；
118a- chip connecting pad；120- adhesive layer；124- conducting sphere；426- conductive layer；D1- cutting line；Z- overlook direction；EA- electronics is set
It is standby.
Specific embodiment
To enable those skilled in the art to be further understood that the present invention, following spy enumerates the embodiment of the present invention, and matches
Close the attached drawing constitution content that the present invention will be described in detail and it is to be reached the effect of.It is noted that attached drawing is simplified signal
Therefore figure only shows the element and syntagmatic related with the present invention, to basic framework of the invention or implementation method offer
Clearer description, and actual element and layout are likely more complexity.In addition, for convenience of explanation, each attached drawing of the invention
Shown in element equal proportion drafting not done with the number, shape, size of actual implementation, detailed ratio can be according to design
Demand be adjusted.
In addition, when in the present specification use term " including " and/or " having " when, which specify the feature, region,
Step, operation and/or the presence of element, but be not precluded other one or more features, region, step, operation, element and/
Or combinations thereof presence or increase.When the element of such as layer or region is referred to as in another element (or its modification) " upper " or extends
To when another element " upper ", it can be directly on another element or between extending directly on another element, or both also
There may be the element of insertion (indirect).On the other hand, when claim an element " directly existing " another element (or its modification) on or
When person " direct " extends to another element " upper ", insertion element is not present between the two.Also, it is arrived when an element is referred to as " coupling "
When another element (or its modification), it can be directly connected to another element or by one or more interelement grounding connection (example
Such as, it is electrically connected) arrive another element.
Notice is known, below for several embodiments can without departing from the spirit of the present invention, by multiple implementations
Feature in example is replaced, recombinates, mixing to complete other embodiments.
Fig. 1 to Fig. 2 show the schematic diagram of manufacturing method of the potted element of first embodiment of the invention, and in a cutaway
Indicate the component structure of each step.The production method of the potted element of first embodiment of the invention includes the following steps.It please refers to
Fig. 1 provides a support plate 102 first, is formed by element to carry subsequent step, support plate 102 may be, for example, hard support plate, example
For example glass substrate can also be soft support plate, for example, polyimides (polyimide, PI) or poly terephthalic acid
(polyethyleneterephthalate, PET), and be set on hard carrier, but not limited to this.In this present embodiment, it carries
Width of the plate 102 in either direction can be at least 400 millimeters, 102 shape of support plate be a rectangle, it is one rectangular, one round,
One polygon or an any shape (free-shape), but not limited to this.For example, support plate 102 can be for 650 millimeters of length extremely
The glass support plate that 2500 millimeters and width are 550 millimeters to 2200 millimeters, such as: the load of 550 millimeters of (length) × 650 millimeter (width)
Plate or the support plate of 600 millimeters of (length) × 720 millimeter (width), but not limited to this.Then, in forming release layer on support plate 102
104.Release layer 104 includes the separated type material with release ability, to continue step in the completed later for support plate 102 and institute's shape
At element separation, the release layer 104 press different substrate materials, can divide into PE release film, PET release film, OPP release film,
Compound release film (i.e. substrate be there are two types of or two or more materials be combined) etc., but not limited to this.Then, in release
At least one conductive pad 106 is formed on layer 104.In this present embodiment, the quantity of conductive pad 106 be it is multiple, and conductive pad 106 that
This separates, so that conductive pad 106 can be used for being electrically connected different signals, but not limited to this.Specifically, conductive pad 106 is formed
Mode lithographic and erosion then can be carried out to conductive layer for example by forming conductive layer (not shown) comprehensively on release layer 104
The patterning process such as quarter.The conductive pad 106 of the present embodiment can be for example including metal material, for example, iron, aluminium, copper or composition metal
Material, to help the impedance for reducing signal transmitting.
Then in formation protective layer 108 on release layer 104 and conductive pad 106.In this present embodiment, protective layer 108 is comprehensive
Cover conductive pad 106 and release layer 104, and protective layer 108 includes conductive material, such as metal material or such as tin indium oxide is thoroughly
Bright conductive material, but not limited to this.Protective layer 108 can be formed for example by same material with conductive pad 106, but not limited to this.
In order to facilitate subsequent etch protective layer 108, the thickness of conductive pad 106 can be greater than the thickness of protective layer 108, be greater than protection
10 times of the thickness of layer 108.The thickness of conductive pad 106 can for example, about tens of thousands of angstroms (angstrom) Dao hundreds of thousands of angstroms, and protective layer
108 thickness for example can arrive thousands of angstroms by approximate number angstrom.In addition, conductive pad 106 can also be adopted with protective layer 108 in other embodiments
With the big material of etch-rate difference, then 106 thickness of conductive pad can be equal to 108 thickness of protective layer, or according to etch-rate difference
And design different thickness.In an embodiment, 106 material etch rate of conductive pad is greater than 108 material etch rate of protective layer,
106 thickness of conductive pad can be greater than 108 thickness of protective layer.In another embodiment, protected if 106 material etch rate of conductive pad is less than
108 material etch rate of sheath, 106 thickness of conductive pad are smaller than 108 thickness of protective layer, but not limited to this.
Then, layer 110 is rerouted in formation on protective layer 108.Wherein, rerouting layer 110 includes at least one layer of dielectric layer
With at least one layer of patterned conductive layer.In this present embodiment, rerouting layer 110 may include that multilayer dielectric layer is led with multi-layered patterned
Electric layer, but not limited to this.Each dielectric layer can sequentially replace with each patterned conductive layer to be stacked on protective layer 108, wherein each be situated between
There can be multiple through-hole 112v in electric layer, through wherein, and each patterned conductive layer can insert the logical of dielectric layer below
In the 112v of hole so that patterned conductive layer on each dielectric layer can with below patterned conductive layer or conductive pad 106 be electrically connected
The patterned conductive layer for connecing, therefore being located at rewiring 110 upper surface of layer, which may be electrically connected to be located at, reroutes leading for 110 lower surface of layer
Electrical pad 106, and then achieve the purpose that route weight cloth.For example, dielectric layer may include the first dielectric layer 112a, the second dielectric layer
112b and third dielectric layer 112c, and patterned conductive layer may include the first patterned conductive layer 114a, the second pattern conductive
Layer 114b and third patterned conductive layer 114c.The mode for forming dielectric layer and patterned conductive layer may include in protective layer 108
Then the first dielectric layer 112a of upper formation forms through-hole 112v by lithographic and etch process, cruelly in the first dielectric layer 112a
Expose corresponding conductive pad 106.Then in forming conductive layer (not shown) on the first dielectric layer 112a, and through-hole 112v is inserted.
Then, it by another lithographic and etch process patterned conductive layer, is led with forming the first patterning including a plurality of conducting wire 1141
Electric layer 114a.Then with the similar processing procedure for forming the first dielectric layer 112a and the first patterned conductive layer 114a, the is sequentially formed
Two dielectric layer 112b, the second patterned conductive layer 114b, third dielectric layer 112c and third patterned conductive layer 114c, wherein the
Two patterned conductive layer 114b may include a plurality of conducting wire 1141, and third patterned conductive layer 114c may include multiple connection pads
1142, it is exposed to the upper surface for rerouting layer 110.Pass through the through-hole 112v of third dielectric layer 112c, the second patterned conductive layer
The conducting wire 1141 and first of the conducting wire 1141 of 114b, the through-hole 112v of the second dielectric layer 112b, the first patterned conductive layer 114a
The through-hole 112v of dielectric layer 112a, the connection pad 1142 of third patterned conductive layer 114c may be electrically connected to corresponding conductive pad 106.
The material of dielectric layer may include organic insulating material, as plastics, polyimides, acryl material or photoresist or it is inorganic absolutely
Edge material, such as silicon oxide or silicon nitride, but not limited to this.In the present embodiment, at least one conductive pad 106 is electrically connected to wherein
One connection pad 1142.In addition, grafting material can be formed on the connection pad 1142 of the third patterned conductive layer 114c of the present embodiment
116, it is engaged to help with the electronic component of subsequent setting.Grafting material is not limited to for example including tin, nickel gold or NiPdAu
This.
After forming rewiring layer 110, the production method alternative of the present embodiment is electric in rerouting setting on layer 110
Subcomponent 118, but not limited to this.Specifically, an at least chip connecting pad 118a for electronic component 118 can be with grafting material 116
It engages (such as in a manner of eutectic bonding), and then is electrically connected to corresponding connection pad 1142, so that electronic component 118 can pass through weight cloth
Line layer 110 is electrically connected to conductive pad 106.Electronic component 118 may be, for example, semiconductor chip (semiconductor chip), place
Device (processor), crystal grain (die), integrated circuit (IC) or the relevant element of other active/passive elements are managed, but not limited to this.
Chip connecting pad 118a can be for example including materials such as tin, nickel, gold or alloys, and but not limited to this.Also, the present embodiment is in rewiring
The electronic component 118 being arranged on layer 110 is not limited to single or single kind, and can need to engage one kind in this step according to product
Or a variety of electronic components 118 or any number of electronic component 118.After having engaged electronic component 118, in rewiring layer
Adhesive layer 120 is formed on 110.In the present embodiment, adhesive layer 120 is mainly located in the outside of electronic component 118, generally without
The upper surface of overlay electronic element 118, but invention is not limited thereto, and in alternate embodiment, adhesive layer 120 can also cover electricity
The upper surface of subcomponent 118.Thermosetting plastics of the adhesive layer 120 for example including such as epoxy resin (epoxy resin), but it is unlimited
In this.
Referring to FIG. 2, then removing release layer 104 and support plate 102.In this present embodiment, release layer 104 and support plate 102
It is that self-insurance sheath 108 is separated with the lower surface of conductive pad 106.The mode for removing release layer 104 can shine for example including utilization laser
Release layer 104 is penetrated, to remove the stickiness of release layer 104, and arranges in pairs or groups and lifts off (lift-off) processing procedure, by support plate 102 and release layer
104 remove from the lower surface of protective layer 108 and conductive pad 106.The optical maser wavelength for removing stickiness may be, for example, 308 nanometers
(nm), 352 nanometers or 532 nanometers, but not limited to this.In another embodiment, machine is can also be used in the mode for removing release layer 104
The mode of tool release (mechanical release) is directly by the lower surface of 104 self-insurance sheath 108 and conductive pad 106 of release layer
Separation.It is noted that the present invention can according to product demand by electronic component 118 with reroute layer 110 engage, or selection not into
Row either step is such as not provided with electronic component 118.
After removing release layer 104 and support plate 102, a manufacturing process for cleaning is carried out, release layer 104 is being removed to remove and is carrying
The carbide or remaining viscose left during plate 102.Since protective layer 108 is the upper surface for being covered in conductive pad 106
On, that is, conductive pad 106 is located at the lower surface of protective layer 108, therefore 106 meeting of a part of protective layer 108 and conductive pad
It is in contact with release layer 104, so that after removing release layer 104 and support plate 102 under a part of meeting matcoveredn 108
Surface and the lower surface of conductive pad 106 are exposed.The manufacturing process for cleaning of the present embodiment is this part for protective layer 108
Lower surface and the lower surface of conductive pad 106 are cleaned, to facilitate between subsequent conductive pad 106 and conducting sphere 124
Testing impedance or conductive pad 106 are electrically connected conducting sphere 124.Manufacturing process for cleaning may include plasma-based manufacturing process for cleaning or wet etch process,
But not limited to this.It is worth noting that the material for being hardly damaged conductive pad 106 Yu protective layer 108 can be used in manufacturing process for cleaning, with
Make when carrying out manufacturing process for cleaning, manufacturing process for cleaning will not damage exposed protective layer 108 and conductive pad 106.Also, due to protecting
Sheath 108 covers conductive pad 106 and release layer 104 comprehensively, therefore in manufacturing process for cleaning, protective layer 108 can protect rewiring layer
Undermost first dielectric layer 112a is protected from the plasma-based or cleaning solution damage of manufacturing process for cleaning in 110.For example, due to
The material of one dielectric layer 112a, such as organic insulating material, different from the metal material of conductive pad 106, therefore manufacturing process for cleaning is to containing
The the first dielectric layer 112a and conductive pad 106 for having organic insulating material have apparent etching selectivity, that is to say, that if not having
In the case where protective layer 108, the rate that manufacturing process for cleaning etches the first dielectric layer 112a can be faster than conductive pad 106, so that in order to
The lower surface effective cleaning for reaching conductive pad 106 will receive manufacturing process for cleaning containing the first dielectric layer of organic insulating material 112a
Damage, or even expose the first patterned conductive layer 114a, cause to reroute layer 110 unqualified.Include through this embodiment
There is a protection of the protective layer 108 of conductive material, the first dielectric layer 112a can be from the destruction of manufacturing process for cleaning, and conductive pad 106
Lower surface also can reach effective cleaning, to reduce the resistance value contacted with conductive pad 106.
After manufacturing process for cleaning, it is etched processing procedure, with etch protection layer 108, and exposes and reroutes layer 110.Yu Ben
In embodiment, protective layer 108 is that part is covered on the upper surface of multiple conductive pads 106 and another part protective layer 108 is arranged
Between multiple conductive pads 106, therefore etch process can only etch and remove the part being set between multiple conductive pads 106 and protect
Sheath 108, and remain in conductive pad 106 and reroute the partial protection layer 108 between layer 110 and form at least one protection zone
Block 108a.Due to the quantity of the conductive pad 106 of the present embodiment be it is multiple, protect block 108a quantity can also to be multiple,
But not limited to this.Also, protect block 108a can be separated from one another, and each protection block 108a can be covered on overlook direction Z
Corresponding conductive pad 106.For example, when protective layer 108 and conductive pad 106 it is formed by same material when, conductive pad 106 and
Protective layer 108 can etching selectivity having the same, due to protective layer 108 thickness be much smaller than conductive pad 106 thickness,
Etch process can still retain most after removing completely the partial protection layer 108 being set between multiple conductive pads 106
Conductive pad 106.In other words, when rewiring layer 110 is exposed, can stop etching processing procedure.The erosion of etch protection layer 108
Scribing journey may be, for example, dry etch process (dry etching process) or wet etch process (wet etching
process)。
After removing the partial protection layer 108 between multiple conductive pads 106, alternative is formed on conductive pad 106
Conducting sphere 124 (solder ball), conducting sphere 124 generally have five big types: (melting range is 180 DEG C to common solder ball
~316 DEG C), low temperature solder ball (bismuth-containing or indium class, melting temperature are 95 DEG C~135 DEG C), (fusing point is 186 DEG C to high temperature solder ball
~309 DEG C), endurance high-purity solder ball (fusing point be 178 DEG C and 183 DEG C), (lead content in ingredient wants small to Pb-free solder ball
In 0.1%), but not limited to this.Then cutting processing procedure is carried out, to form an at least potted element 100, wherein cutting processing procedure can example
It is for example cut by laser (laser cutting), flywheel knife cutting (wheel cutting) or impact cutting (punch) processing procedure, but not
It is limited to this.Cutting processing procedure can select cutting position according to product demand, such as cut along cutting line D1, make potted element
100 may include at least one electronic component 118, and but not limited to this.By cutting processing procedure, potted element 100 can have arbitrarily
The electronic component 118 of quantity or the storehouse of multiple electronic components 118, and the number of the electronic component 118 in different potted elements 100
Amount can be mutually the same or not identical, but not limited to this.In an embodiment, in etch process and formed between conducting sphere 124
Alternative carries out a detecting step, to carry out open test, short-circuit test and functional test to packaging body.It is worth explanation
Be, compared to manufacturing process for cleaning in order to avoid damage dielectric layer and the case where reduce the cleannes of conductive pad 106, the present embodiment it is clear
The lower surface of conductive pad 106 can effectively be cleaned by washing processing procedure and etch process, therefore in detecting step due to resistance value is unqualified
The faulty goods detected can be lowered, and then promote product qualification rate.In addition, being led by manufacturing process for cleaning and etch process cleaning
The lower surface of electrical pad 106 can help to the lower surface that conducting sphere 124 is attached to conductive pad 106, and then avoid because of conducting sphere 124
With the engagement of conductive pad 106 it is bad caused by high value or because conducting sphere 124 from conductive pad 106 fall off caused by open circuit,
To improve product qualification rate.
In another embodiment, potted element may be, for example, flexible circuit board.That is, potted element may not include electricity
Subcomponent, but to reroute layer 110 as circuit board, the production method for implying that potted element, which can be omitted in first embodiment, to be schemed
1 is shown in the step of rerouting setting electronic component 118 on layer 110, but not limited to this.And after forming rewiring layer 110,
Release layer 104 and support plate 102 are removed, and carries out manufacturing process for cleaning.Then, etch protection layer 108, and selectively formed conducting sphere
124, on the lower surface of conductive pad 106, then carry out cutting processing procedure, to form potted element.It is worth noting that compared to
Traditional circuit-board forms the conducting wire of patterned conductive layer using printing process, and the rewiring layer 110 of the present embodiment is due to by micro-
Shadow and etch process can produce that width is smaller and small-pitch conducting wire, can reach the rewiring layer compared with high density whereby
110。
Potted element provided by the invention and preparation method thereof is not limited with above-described embodiment.It will hereafter continue to disclose this
The other embodiments or variation shape of invention, and mix and match can be used mutually between each embodiment, so to simplify the explanation simultaneously
It highlights each embodiment or changes the difference between shape, hereinafter mark similar elements using identical label, and no longer counterweight answers portion
It is allocated as repeating.
Fig. 3 to Fig. 5 show the schematic diagram of manufacturing method of the potted element of second embodiment of the invention, and in a cutaway
Indicate the component structure of corresponding step.The production method different from the first embodiment of the potted element of second embodiment of the invention
It is, the protective layer 308 of the present embodiment is formed between conductive pad 306 and release layer 104.Specifically, referring to FIG. 3,
The present embodiment forms release layer 104 and is identical with the first embodiment in the step on support plate 102, therefore details are not described herein.Thereafter,
In formation protective layer 308 on release layer 104.Then, in forming conductive layer (not shown) on protective layer 308, and by lithographic and
Etch process etches conductive layer, in forming conductive pad 306 on protective layer 308.
Referring to FIG. 4, rerouting layer 110 in being formed on conductive pad 306 after forming conductive pad 306.The present embodiment can
Further in setting electronic component 118 on rewiring layer 110, and in formation adhesive layer 120 on rewiring layer 110.Then, it moves
Except release layer 104 and support plate 102, to expose the lower surface of protective layer 308.Then, the lower surface of protective layer 308 is carried out clear
Wash processing procedure.Since 308 whole face of protective layer of the present embodiment covers release layer 104 and is located on the lower surface of conductive pad 306, also
It is the lower surface that protective layer 308 also covers conductive pad 306 in addition to the lower surface that covering reroutes layer 110, therefore manufacturing process for cleaning is only
It can be cleaned for the lower surface of protective layer 308, without being cleaned for two kinds of materials.Therefore, protective layer 308 can wrap
Any material for keeping out manufacturing process for cleaning is included, such as the material or insulating materials that are identical with the first embodiment, but not limited to this.In
In another embodiment, after forming rewiring layer 110, setting electronic component 118 can be not required to and form adhesive layer 120, and
It directly carries out removing release layer 104 and support plate 102.
Referring to FIG. 5, after manufacturing process for cleaning, etch protection layer 308 to remove entire protective layer 308, and then exposes
Conductive pad 306.Then, alternative in formation conducting sphere 124 on conductive pad 306, and cutting processing procedure is then carried out, to be formed extremely
Few one potted element 300.
Fig. 6 to Fig. 7 show the schematic diagram of manufacturing method of the potted element of third embodiment of the invention, and in a cutaway
Indicate the component structure of corresponding step.The production method of the potted element of third embodiment of the invention and the difference of second embodiment
It is, the protective layer 426a and conductive pad 426b of the present embodiment are formed by same conductive layer 426.Specifically, please referring to
Fig. 6, it is identical as second embodiment in the step on support plate 102 that the present embodiment forms release layer 104, therefore details are not described herein.
Thereafter, in forming conductive layer 426 on release layer 104, wherein conductive layer 426 can have uniform thickness, but not limited to this.It connects
, in forming photoresist pattern (not shown) on conductive layer 426, to define the position of conductive pad 426b.It is screen with photoresist pattern
It covers, is etched processing procedure from the upper surface of conductive layer 426, to remove a part for the conductive layer 426 not covered by photoresist pattern,
And then form protective layer 426a and conductive pad 426b.Then, photoresist pattern is removed.In the etch process of the present embodiment, by light
The thickness for hindering the part of the conductive layer 426 of pattern masking (can pass through erosion than the part for the conductive layer 426 not covered by photoresist pattern
Carve) thickness it is thick, in other words etch process is by 426 eating thrown of conductive layer, but when the depth of etching reaches conductive layer 426
Certain proportion when can stop.In this present embodiment, protective layer 426a is a part for the conductive layer 426 being left behind, conductive
Pad 426b is the another part for the conductive layer 426 being left behind, and protective layer 426a be located at conductive pad 426b and release layer 104 it
Between, layer 110 is rerouted from being destroyed in manufacturing process for cleaning or etch process to protect.Due to the protective layer of the present embodiment
426a and conductive pad 426b is formed by same conductive layer 426, therefore can be formed by same material, such as by metal material institute
It is formed, but not limited to this.
Referring to FIG. 7, the production method of the present embodiment can be identical to after forming protective layer 426a and conductive pad 426b
Second embodiment reroutes layer 110 in being formed on protective layer 426a and conductive pad 426b.Then, it is arranged on rewiring layer 110
Electronic component 118, and adhesive layer 120 is formed on layer 110 in rerouting.Then, release layer 104 and support plate 102 are removed, with sudden and violent
Expose the lower surface of protective layer 426a, and manufacturing process for cleaning then is carried out to the lower surface of protective layer 426a.Then, it is etched system
Journey reroutes layer 110 and conductive pad 426b until exposing.Later, alternative in forming conducting sphere on conductive pad 426b
124, and cutting processing procedure is then carried out, to form potted element 300 identical with second embodiment, as shown in Figure 5.In another reality
Apply in example, in formed reroute layer 110 after, can be not required to setting electronic component 118 and formed adhesive layer 120, and directly into
Row removes release layer 104 and support plate 102.
Fig. 8 to Fig. 9 show the schematic diagram of manufacturing method of the potted element of fourth embodiment of the invention, and in a cutaway
Indicate the component structure of corresponding step.The production method of the potted element of fourth embodiment of the invention and the difference of second embodiment
It is, the protective layer 508 of the present embodiment includes that multiple be formed by by insulating materials protects block 508a, and protects block 508a
Between conductive pad 306 and release layer 104.Specifically, as shown in figure 8, the present embodiment forms release layer 104 in support plate
Step on 102 is identical as second embodiment, therefore details are not described herein.Thereafter, in the formation protected material bed of material on release layer 104
(not shown).Then, the protected material bed of material is patterned by lithographic and etch process, includes multiple protection block 508a to be formed
Protective layer 508, and expose part release layer 104, wherein protection block 508a can be separated from one another.Then, in protection block
Conductive layer (not shown) is formed on 508a and release layer 104, and conductive layer is etched by lithographic and etch process, in protection zone
Conductive pad 306 is formed on block 508a.In another embodiment, in protection materials of the formation including insulating materials on release layer 104
Layer (not shown) and conductive layer (not shown), the protected material bed of material are set between conductive layer and release layer 104, later protection materials
Layer also can be patterned to form multiple protection block 508a and conductive pad with the lithographic with along with and etch process simultaneously with conductive layer
306, and expose part release layer 104.
As shown in figure 8, rerouting layer in being formed on conductive pad 306 and release layer 104 after forming conductive pad 306
110, that is, the present embodiment reroute layer 110 the first dielectric layer 112a can be in contact with release layer 104.Then, Yu Chongbu
Electronic component 118 is set on line layer 110, and forms adhesive layer 120 on layer 110 in rerouting.
As shown in figure 9, removing release layer 104 and support plate 102, then to expose protection block 508a and the first dielectric layer
The lower surface of 112a.Then, manufacturing process for cleaning is carried out to the lower surface of protection block 508a and the first dielectric layer 112a.It is worth explanation
, protection block 508a can be formed by identical material from the first dielectric layer 112a or the different materials close by etch-rate
Material is formed, so that in manufacturing process for cleaning, etching solution does not have apparent erosion to protecting block 508a and the first dielectric layer 112a
Etching speed difference can avoid protection one of block 508a and the first dielectric layer 112a person whereby and is damaged by over etching.
In addition, the material of protection block 508a may include metal material such as Al, Mo, Ti, W, Cu, Au, Cr etc., or such as compound-material
AlNd, MoN, CrO, ITO, IZO etc., or be inorganic material such as SiO, SiN etc., or be organic material such as polyimide etc., but not
It is limited to this.And etching mode can be wet etching or dry ecthing, if potassium hydroxide can be used in the etching solution of wet etching, and dry ecthing can
It is etched using CF4/O2 gas electric pulp, but not limited to this.In another embodiment, after forming rewiring layer 110, it can be not required to
Electronic component 118 is set and forms adhesive layer 120, and directly carries out removing release layer 104 and support plate 102.In the present embodiment
In, to make etching solution not encounter conductive pad 306, protection block 508a covers entire conductive pad 306 on overlook direction Z, because
After removing release layer 104, conductive pad 306 will not be exposed for this.For example, protect the area of block 508a that can be greater than
Or the area equal to conductive pad 306.
After manufacturing process for cleaning, etching protection block 508a and the first dielectric layer 112a, with remove protection block 508a and
Part of first dielectric layer 112a, and then expose conductive pad 306.Then, alternative in forming conducting sphere on conductive pad 306
124.In another embodiment, the big material of rate of etch difference is can be used in protection block 508a and the first dielectric layer 112a, wherein
It protects the rate of etch of block 508a to be greater than the first dielectric layer 112a, protection block 508a can be fully etched in etching, but the
One dielectric layer 112a then will not over etching, keep conductive pad 306 exposed and with the first dielectric layer 112a not in same plane,
And in forming conducting sphere on conductive pad 306, and the present embodiment will be helpful to be promoted the stability of conducting sphere and conductive pad 306.Afterwards
It is continuous, and cutting processing procedure is then carried out, to form an at least potted element 300, as shown in Figure 5.
Potted element produced by the various embodiments described above can be further applied in electronic equipment.That is, encapsulation
Element can in such a way that die bond engages in electronic equipment either circuit plate or element engage and be electrically connected.Figure 10 is shown
Potted element of the invention is applied to the schematic diagram of an example of electronic equipment.As shown in Figure 10, via cutting processing procedure along cutting
The potted element 600 that line D1 is cut into can be further disposed upon in any electronic equipment EA, such as be set to mobile device
In, however, the present invention is not limited thereto.Also, the potted element 600 of this example can be the potted element of any of the above-described embodiment.
In conclusion potted element provided by the invention with and preparation method thereof be formed release layer and formed reroute
It is further formed the protective layer of whole face covering between layer, is formed by with protection and reroutes layer from manufacturing process for cleaning or etching system
Journey is damaged, and then makes manufacturing process for cleaning that can effectively clean the lower surface of protective layer or conductive pad.Whereby, it can help to lead
Electric ball is attached to the lower surface of conductive pad, to avoid the engagement because of conducting sphere and conductive pad it is bad caused by high value or because leading
Electric ball falls off generated open circuit from conductive pad, and then improves product qualification rate.
The above description is only an embodiment of the present invention, is not intended to restrict the invention, for those skilled in the art
For member, the invention may be variously modified and varied.All within the spirits and principles of the present invention, it is made it is any modification,
Equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (18)
1. a kind of potted element characterized by comprising
One conductive pad；
One protection block, is set on the conductive pad；And
One reroutes layer, is set on the protection block, and the conductive pad is electrically connected to the rewiring layer by the protection block.
2. potted element as described in claim 1, which is characterized in that the conductive pad directly contacts the protection block.
3. potted element as described in claim 1, which is characterized in that the protection block is in the overlook direction of the potted element
Cover the conductive pad.
4. potted element as described in claim 1, which is characterized in that the conductive pad is with the protection block by an identical material institute
It is formed.
5. potted element as described in claim 1, which is characterized in that the protection block includes a conductive material.
6. potted element as described in claim 1, which is characterized in that the conductive pad has different thickness from the protection block
Degree.
7. potted element as described in claim 1, which is characterized in that further include an electronic component, be set to the rewiring layer
On, and the conductive pad is electrically connected the electronic component with the rewiring layer by the protection block.
8. potted element as claimed in claim 7, which is characterized in that the rewiring layer includes an at least dielectric layer and at least one
Patterned conductive layer, and the conductive pad is electrically connected the electronic component by the patterned conductive layer.
9. potted element as described in claim 1, which is characterized in that further include a conducting sphere, be in contact with the conductive pad.
10. a kind of production method of potted element, which comprises the following steps:
In forming a release layer on a support plate；
In forming a protective layer and a conductive pad on the release layer, wherein the protective layer contacts the conductive pad；
Layer is rerouted in forming one on the protective layer and the conductive pad；
Remove the release layer and the support plate；And
Etch the protective layer.
11. the production method of potted element as claimed in claim 10, which is characterized in that further comprising the steps of: removing
Before the release layer and the support plate, an electronic component is set on the rewiring layer.
12. the production method of potted element as claimed in claim 10, which is characterized in that the conductive pad is with the protective layer by same
One material is formed.
13. the production method of potted element as claimed in claim 10, which is characterized in that the conductive pad has with the protective layer
Different thickness.
14. the production method of potted element as claimed in claim 10, which is characterized in that further comprising the steps of: in removal
It the release layer and etches between the protective layer, a manufacturing process for cleaning is carried out to the protective layer.
15. the production method of potted element as claimed in claim 10, which is characterized in that form the conduction by following steps
Pad and the protective layer:
In forming the conductive pad on the release layer；And
In forming the protective layer on the conductive pad and the release layer,
Wherein etching the protective layer includes a part for removing the protective layer, to expose the rewiring layer.
16. the production method of potted element as claimed in claim 10, which is characterized in that form the conduction by following steps
Pad and the protective layer:
In forming the protective layer on the release layer；And
In forming the conductive pad on the protective layer,
Wherein etching the protective layer includes removing the protective layer, to expose the conductive pad.
17. the production method of potted element as claimed in claim 10, which is characterized in that form the conduction by following steps
Pad and the protective layer:
In forming a conductive layer on the release layer；And
The conductive layer is etched, to form the conductive pad and the protective layer,
Wherein the thickness of the conductive pad is greater than the thickness of the protective layer, and etching the protective layer includes removing the protective layer.
18. the production method of potted element as claimed in claim 10, which is characterized in that further comprising the steps of: in etching
After the protective layer, in forming a conducting sphere on the conductive pad.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/018,003 US20190035715A1 (en) | 2017-07-31 | 2018-06-25 | Package device and manufacturing method thereof |
| US16/941,516 US11488899B2 (en) | 2017-07-31 | 2020-07-28 | Package device |
| US17/960,816 US20230027220A1 (en) | 2017-07-31 | 2022-10-05 | Package device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762538808P | 2017-07-31 | 2017-07-31 | |
| US62/538,808 | 2017-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109326569A true CN109326569A (en) | 2019-02-12 |
Family
ID=65245309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711433952.2A Pending CN109326569A (en) | 2017-07-31 | 2017-12-26 | Potted element and preparation method thereof |
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| CN (1) | CN109326569A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110047820A (en) * | 2019-05-24 | 2019-07-23 | 中芯长电半导体（江阴）有限公司 | Antenna packages structure and packaging method with air chamber |
| CN110164852A (en) * | 2019-05-24 | 2019-08-23 | 中芯长电半导体（江阴）有限公司 | Antenna packages structure and packaging method with air chamber |
| CN110047820B (en) * | 2019-05-24 | 2024-10-29 | 盛合晶微半导体(江阴)有限公司 | Antenna packaging structure with air cavity and packaging method |
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Application publication date: 20190212 |