TWI474452B - Substrate, semiconductor package and manufacturing method thereof - Google Patents

Substrate, semiconductor package and manufacturing method thereof Download PDF

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Publication number
TWI474452B
TWI474452B TW100134080A TW100134080A TWI474452B TW I474452 B TWI474452 B TW I474452B TW 100134080 A TW100134080 A TW 100134080A TW 100134080 A TW100134080 A TW 100134080A TW I474452 B TWI474452 B TW I474452B
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TW
Taiwan
Prior art keywords
layer
semiconductor package
surface
dielectric layer
circuit layer
Prior art date
Application number
TW100134080A
Other languages
Chinese (zh)
Other versions
TW201314852A (en
Inventor
Ming Chen Sun
Wei Chung Hsiao
Yu Cheng Pai
Liang Yi Hung
Chun Hsien Lin
Fengming Kuo
Don Son Jiang
Original Assignee
Siliconware Prec Ind Co Ltd
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Application filed by Siliconware Prec Ind Co Ltd filed Critical Siliconware Prec Ind Co Ltd
Priority to TW100134080A priority Critical patent/TWI474452B/en
Publication of TW201314852A publication Critical patent/TW201314852A/en
Application granted granted Critical
Publication of TWI474452B publication Critical patent/TWI474452B/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73257Bump and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

Substrate, semiconductor package and method of manufacturing same

The present invention relates to a semiconductor package, and more particularly to a thin semiconductor package and a method of fabricating the same.

Traditionally, there are many types and types of semiconductor packages in which lead frames are used as wafer carriers. For example, in a conventional Quad Flat package (QFP) semiconductor package, the external lead is electrically connected to the outside. When the pitch of the foot is less than 0.65 mm, the outer guide leg is easily bent. Therefore, in order to solve the problem of deformation of the outer guide leg, a new quad flat non-leaded (QFN) package structure has been developed, and thus, the size of the semiconductor package will be reduced.

Please refer to FIG. 1A, which is a QFN semiconductor package 1 disclosed in US Pat. No. 6,281,568. The wafer 14 is mainly disposed on the lead frame 11 and electrically connected to the upper side of the wafer 14 and the lead 112 through the bonding wire 15. A package molding process is performed to form the encapsulant 16 and then solder balls 17 are implanted on the underside of the pin 112.

However, with the trend of thin and light semiconductor products, the conventional QFN semiconductor package 1 has the thickness of the package colloid 16 due to the lead frame 11, which makes it impossible to further reduce the overall height of the package, and the conventional QFN is easy to fall. The problem, therefore, has led to the development of a semiconductor package that reduces the thickness of conventional leadframes to make their overall thickness thinner and more reliable than conventional leadframe packages.

Please refer to FIG. 1B, which is a QFN semiconductor package 1 ′ disclosed in US Pat. No. 2011/0057301, which mainly performs a patterning process on the metal foil layer 11 ′ so that the metal foil layer 11 ′ has a wafer holder 110 and The lead line 111 is further covered with the dielectric layer 10 to cover the metal foil layer 11', and a plurality of openings 100 are formed on the dielectric layer 10 to expose portions of the upper and lower surfaces of the line 111. The pad 111a is next, and the wafer 14 is disposed on the surface of the dielectric layer 10 above the wafer holder 110, and the wafer 14 and the pad 111a are electrically connected through the bonding wire 15, and the encapsulant 16 is formed to cover the wafer 14. The number of the pads 111a is substantially corresponding to the number of electrical connection pads (not shown) disposed on the active surface of the wafer 14.

However, in the conventional QFN semiconductor package 1', since the line 111 serves as a guide pin and the opening 100 is used to define the position of the pad 111a, the design flexibility of the line 111 is limited, and The layout of the line 111 is arbitrarily designed.

Furthermore, when a wafer has developed a higher number or higher density of electrical connection pads, a highly integrated wafer is used, and since the area of the line 111 is limited, sufficient openings cannot be formed. 100, so that the demand for highly integrated chips cannot be met, resulting in the inability to make semiconductor packages meet the needs of high pin count, high density lines.

Therefore, how to overcome various problems of the prior art is an important issue.

In order to overcome the trend of the prior art to develop a high pin count, a high-density line, the present invention provides a semiconductor package comprising: a dielectric layer having a first surface and a second surface opposite to each other; The first and second surfaces respectively have a plurality of first and second openings; a patterned circuit layer is wrapped in the dielectric layer, and a portion of the surface of the patterned circuit layer exposes the first and the first a first re-wiring circuit layer disposed on the first surface of the dielectric layer and connected to the patterned circuit layer in the first opening, and having a plurality of first connection pads; disposed on the dielectric a wafer on the first surface of the layer and electrically connected to the first connection pad; and an encapsulant formed on the first surface of the dielectric layer to cover a portion of the first redistribution circuit layer.

The invention provides a method for fabricating a semiconductor package, comprising: providing a metal plate; patterning the metal plate to form a patterned circuit layer; forming a dielectric layer to encapsulate the patterned circuit layer, and the dielectric The layer has opposite first and second surfaces; forming a plurality of first openings and second openings on the first surface and the second surface of the dielectric layer to expose a portion of the surface of the patterned circuit layer The first and second openings; forming a first redistribution circuit layer on the first surface of the dielectric layer and connecting the patterned circuit layer in the first opening, the first redistribution circuit layer having a plurality of a connection pad; disposing a wafer on the first surface of the dielectric layer, and electrically connecting the wafer to the first connection pad; and forming an encapsulant on the first surface of the dielectric layer to cover a portion of the A layer of wiring.

The semiconductor package and the method of manufacturing the same may include a second redistribution circuit layer and a conductive element, the second redistribution circuit layer being formed on the second surface of the dielectric layer and connected to the second opening The patterned circuit layer has a second connection pad, and the conductive element is disposed on the second connection pad. Wherein the conductive element can be a solder ball.

In the above semiconductor package and the method of manufacturing the same, the metal plate may be a copper plate, so the material of the patterned circuit layer may be steel.

In the foregoing semiconductor package and method of fabricating the same, the dielectric layer is a solder resist layer.

In the foregoing semiconductor package and method of manufacturing the same, the first or second redistribution circuit layer may be formed by electroplating, and the material of the first or second redistribution circuit layer may be nickel palladium gold (Ni/Pd/Au) .

In the foregoing semiconductor package and the method of manufacturing the same, the wafer may be electrically connected to the first connection pad by wire bonding or flip chip.

It can be seen that the semiconductor package of the present invention and the manufacturing method thereof are designed by the first redistribution circuit layer, so that the patterned circuit does not need to be used as a guide pin, and thus the number of electrical connection pads of the wafer does not need to be matched, thereby improving The flexibility of the line design.

Moreover, by the design of the first redistribution circuit layer, the number of the first connection pads can be arbitrarily adjusted to meet the requirement of the highly integrated wafer, so as to achieve a high pin count of the semiconductor package. The purpose of high-density lines.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "in" and "the" are used in the description, and are not intended to limit the scope of the invention, and the relative relationship may be changed or Adjustments, where there is no material change, are considered to be within the scope of the invention.

Please refer to FIGS. 2A to 2G for a cross-sectional view showing the manufacturing method of the semiconductor package 2 of the present invention. In the embodiment, the semiconductor package 2 is a carrierless carrierless.

As shown in FIG. 2A, a first dielectric member 201 is formed on a metal plate 21a. In the embodiment, the metal plate 21a is a copper plate. In other embodiments, the metal plate 21a may be other metal materials.

As shown in FIG. 2B, the metal plate 21a is formed into a patterned wiring layer 21 by a patterning process. In this embodiment, the patterning process may be formed by photoresist exposure, development, etching, etc. to form the patterned circuit layer 21, or other embodiments having the same effect, and the patterned circuit layer 21 does not have a crystal. Pad, but other embodiments may have a pad (not shown).

As shown in FIG. 2C, a second dielectric material (not shown) is formed on the first dielectric material 201, and the first dielectric material 201 and the second dielectric material are processed to form a dielectric layer 20 to The patterned wiring layer 21 is covered, and the dielectric layer 20 has a first surface 20a and a second surface 20b opposite to each other. In this embodiment, the dielectric layer 20 is a solder resist layer (commonly known as green paint in the industry, which is a preferred embodiment), and may also be other materials that can achieve the same effect, such as photoresist, ink or tape. .

As shown in FIG. 2D, a plurality of first openings 200a and a plurality of second openings 200b are formed on the first surface 20a and the second surface 20b of the dielectric layer 20 to form portions of the patterned circuit layer 21. The first and second openings 200a, 200b are exposed outside the surface, and the openings are formed by exposure development, etching, laser drilling or by mask printing.

As shown in FIG. 2E, a first redistribution wiring layer 22 is formed on the first surface 20a of the dielectric layer 20, and the first redistribution wiring layer 22 has a plurality of first connection pads 220, 200', and a portion thereof The first connection pad 220 is connected to the patterned circuit layer 21 located in the first openings 200a by the first redistribution circuit layer 22 and extends to a soldering position to be connected to the wafer, and a portion of the first connection pad 220' is located on the patterned circuit layer 21 in the first openings 200a. And forming a second redistribution circuit layer 23 on the second surface 20b of the dielectric layer 20, and the second redistribution circuit layer 23 has a plurality of second connection pads 230, and the second connection pad 230 is The second redistribution wiring layer 23 is connected to the patterned wiring layer 21 located in the second openings 200b and extends to a soldering position which is intended to be connected to the circuit board. The first and second redistribution wiring layers may also be formed by electroless plating, sputtering, plating, or the like.

In this embodiment, the first and second redistribution circuit layers 22, 23 are made of a metal layer of nickel-palladium gold (Ni/Pd/Au), and may also have better connectivity and reliability according to the solder material. Choose a different metal layer.

As shown in FIG. 2F, a wafer 24 is disposed on the first surface 20a of the dielectric layer 20, and a wire bonding process is performed to electrically connect the wafer 24 to the first connection pad 220, 220' by a plurality of bonding wires 25. An encapsulant 26 is formed on the first redistribution wiring layer 22 and the first surface 20a of the dielectric layer 20 to cover the wafer 24, the bonding wires 25 and the first redistribution wiring layer 22.

In this embodiment, the dielectric layer 20 under the wafer 24 has no crystal pad, so the patterned circuit layer can be elastically arranged to improve the flexibility of the circuit design.

Moreover, by the design of the first redistribution circuit layer 22, the patterned circuit 21 is connected via the first redistribution circuit layer 22 as a line layout elastic design, thereby improving the flexibility of the circuit design.

As shown in FIG. 2G, a conductive member 27 is formed on the second connection pads 230 to connect an electronic device such as a circuit board (not shown). In this embodiment, the conductive elements 27 are solder balls (as shown) or solder pins (not shown).

In other embodiments, as shown in FIG. 2G′, the wafer 24 ′ is provided on the first surface 20 a of the dielectric layer 20 in a flip chip manner, so that the wafer 24 ′ is electrically connected by a plurality of solder balls 25 ′. Connecting the first connection pads 220, 220', and forming an encapsulant 26 on the first redistribution circuit layer 22 and the first surface 20a of the dielectric layer 20 to cover the wafer 24', the solder balls 25' and the first The wiring layer 22 is repeated.

Or, as shown in FIG. 2G", after the flip chip process, the encapsulant 26' can be used as a primer to be formed between the wafer 24' and the first surface 20a of the dielectric layer 20, and The solder ball 25' is covered with a portion of the first redistribution wiring layer 22.

When a highly integrated wafer is to be used, that is, the wafer 24, 24' has a large number or a higher density of electrical connection pads (not shown), by the first redistribution circuit layer 22 The design of the first connection pad 220 on the first surface 20a of the dielectric layer 20 is elastically increased, and is not limited to the first connection pad 220' at the first opening 200a, so that the height is integrated. The wafers 24, 24' can be effectively disposed such that the semiconductor package 2 has a high pin count, high density line.

The present invention further provides a semiconductor package 2 comprising: a dielectric layer 20 having a first surface 20a and a second surface 20b opposite thereto, and a patterned wiring layer 21 encapsulated in the dielectric layer 20; a first redistribution wiring layer 22 on the first surface 20a of the dielectric layer 20, a wafer 24, 24' disposed on the first surface 20a of the dielectric layer 20, and a first layer formed on the dielectric layer 20. Encapsulant 26 on surface 20a.

The first and second surfaces 20a, 20b of the dielectric layer 20 respectively have a plurality of first openings 200a and a plurality of second openings 200b. The dielectric layer 20 is a solder resist layer.

The first and second openings 200a, 200b are exposed on a part of the surface of the patterned circuit layer 21, and the material of the patterned circuit layer 21 is a steel material.

The first redistribution circuit layer 22 has a plurality of first connection pads 220, and a portion of the first connection pads 220' are located on the patterned circuit layer 21 in the first openings 200a. The material of the first redistribution wiring layer 22 is nickel palladium gold (Ni/Pd/Au).

The wafers 24, 24' are electrically connected to the first connection pads 220, 220' by solder wires 25, and the first connection pads 220, 220' may be electrically connected by solder balls 25'.

The encapsulant 26 covers a portion of the first redistribution wiring layer 22, and the wafer 24 and the bonding wires 25 (or solder balls 25') are coated as needed.

In addition, the semiconductor package 2 includes a second redistribution circuit layer 23 disposed on the second surface 20b of the dielectric layer 20, and has a plurality of patterned circuit layers 21 located in the second opening 200b. The second connection pad 230 is coupled to the conductive element 27 such as a solder ball. The material of the second redistribution wiring layer 23 is nickel palladium gold (Ni/Pd/Au).

In summary, the semiconductor package of the present invention and the method for manufacturing the same are not only elastically arranged in accordance with the degree of integration of the wafer, but also effectively reach the number of multi-leg and high-density lines by the design of the first redistribution circuit layer. Design requirements.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1,1’. . . QFN semiconductor package

10. . . Dielectric layer

100. . . Opening

11. . . Lead frame

11’. . . Metal foil layer

110. . . Wafer holder

111. . . line

111a. . . Solder pad

112. . . Guide pin

14,24,24’. . . Wafer

15,25. . . Welding wire

16,26,26’. . . Encapsulant

17. . . Solder ball

2,2’. . . Semiconductor package

20. . . Dielectric layer

20a. . . First surface

20b. . . Second surface

200a. . . First opening

200b. . . Second opening

201. . . First dielectric

twenty one. . . Patterned circuit layer

21a. . . Metal plate

twenty two. . . First redistribution layer

220,220’. . . First connection pad

twenty three. . . Second redistribution layer

230. . . Second connection pad

25’. . . Solder ball

27. . . Conductive component

1A is a schematic cross-sectional view of a QFN semiconductor package of US Patent No. 6,281,568;

1B is a schematic cross-sectional view of a non-carrier QFN semiconductor package of US Patent No. 2011/0057301;

2A to 2G are schematic cross-sectional views showing a method of fabricating a semiconductor package of the present invention; wherein the 2G' and 2G" diagrams are other embodiments of the 2Gth diagram.

2. . . Semiconductor package

20. . . Dielectric layer

20a. . . First surface

20b. . . Second surface

200a. . . First opening

200b. . . Second opening

twenty one. . . Patterned circuit layer

twenty two. . . First redistribution layer

220,220’. . . First connection pad

230. . . Second connection pad

twenty four. . . Wafer

25. . . Welding wire

26. . . Encapsulant

Claims (21)

  1. A semiconductor package comprising: a dielectric layer having opposite first and second surfaces, the first and second surfaces respectively having a plurality of first and second openings; a patterned circuit layer, a package Covering the dielectric layer, and partially exposing the first and second openings to a portion of the surface of the patterned circuit layer; the first redistribution circuit layer is disposed on the first surface of the dielectric layer and connected a patterned circuit layer in the first opening, and having a plurality of first connection pads; a wafer disposed on the first surface of the dielectric layer and electrically connected to the first connection pad; and an encapsulant Formed on the first surface of the dielectric layer to cover the first redistribution wiring layer.
  2. The semiconductor package of claim 1, wherein the dielectric layer is a solder resist layer.
  3. The semiconductor package of claim 1, wherein the patterned circuit layer is made of copper.
  4. The semiconductor package of claim 1, wherein the wafer is electrically connected to the first connection pad by wire bonding or flip chip.
  5. The semiconductor package of claim 1, further comprising a second redistribution circuit layer disposed on the second surface of the dielectric layer and connected to the patterned circuit layer in the second opening, And has a plurality of second connection pads.
  6. The semiconductor package of claim 5, further comprising a conductive element disposed on the second connection pad.
  7. The semiconductor package of claim 6, wherein the conductive element is a solder ball or a solder pin.
  8. The semiconductor package of claim 5, wherein the first or second redistribution layer is made of nickel palladium.
  9. A method of fabricating a semiconductor package, comprising: providing a metal plate; patterning the metal plate to form a patterned circuit layer; forming a dielectric layer to encapsulate the patterned circuit layer, and the dielectric layer has a relative a first surface and a second surface; forming a plurality of first openings and second openings on the first surface and the second surface of the dielectric layer to expose a portion of the surface of the patterned circuit layer to the first surface a second opening; forming a first redistribution circuit layer on the first surface of the dielectric layer, and connecting the patterned circuit layer in the first opening, the first redistribution circuit layer having a plurality of first connection pads Providing a wafer on the first surface of the dielectric layer, and electrically connecting the wafer to the first connection pad; and forming an encapsulant on the first surface of the dielectric layer to cover a portion of the first weight The wiring layer.
  10. The method of fabricating a semiconductor package according to claim 9, wherein the dielectric layer is a solder resist layer.
  11. The method of fabricating a semiconductor package according to claim 9, wherein the first redistribution circuit layer is formed by electroplating.
  12. The method of fabricating a semiconductor package according to claim 9, wherein the metal plate is a copper plate.
  13. The method of fabricating a semiconductor package according to claim 9, wherein the wafer is electrically connected to the first connection pad by wire bonding or flip chip.
  14. The method of fabricating a semiconductor package according to claim 9 further comprising: forming a second redistribution wiring layer on the second surface of the dielectric layer, and connecting the patterned circuit layer in the second opening The second redistribution circuit layer has a second connection pad.
  15. The method of fabricating a semiconductor package according to claim 14, wherein the second redistribution layer is formed by electroplating.
  16. The method of fabricating a semiconductor package according to claim 14, further comprising forming a conductive element on the second connection pad.
  17. The method of fabricating a semiconductor package according to claim 16, wherein the conductive component is a solder ball or a solder pin.
  18. The method of fabricating a semiconductor package according to claim 14, wherein the material of the first or second redistribution layer is nickel palladium.
  19. A substrate comprising: a dielectric layer having opposite first and second surfaces, wherein the first and second surfaces respectively have a plurality of first and second openings; and the patterned circuit layer is coated on The first and second openings are exposed in a part of the surface of the patterned circuit layer; the first redistribution circuit layer is disposed on the first surface of the dielectric layer, and is connected to the first a patterned circuit layer in an opening, and having a plurality of first connection pads; and a second redistribution circuit layer disposed on the second surface of the dielectric layer and connected to the patterning in the second opening The circuit layer has a plurality of second connection pads.
  20. The substrate of claim 19, wherein the dielectric layer is a solder resist layer.
  21. The substrate of claim 19, wherein the material of the first or second redistribution layer is nickel palladium.
TW100134080A 2011-09-22 2011-09-22 Substrate, semiconductor package and manufacturing method thereof TWI474452B (en)

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TW100134080A TWI474452B (en) 2011-09-22 2011-09-22 Substrate, semiconductor package and manufacturing method thereof

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TW100134080A TWI474452B (en) 2011-09-22 2011-09-22 Substrate, semiconductor package and manufacturing method thereof
CN201110319700.3A CN103021969B (en) 2011-09-22 2011-10-13 Substrate, semiconductor package and fabrication method thereof

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TW201314852A TW201314852A (en) 2013-04-01
TWI474452B true TWI474452B (en) 2015-02-21

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Cited By (1)

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TWI632665B (en) * 2015-06-17 2018-08-11 精材科技股份有限公司 Method for forming chip package

Families Citing this family (4)

* Cited by examiner, † Cited by third party
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