TWI394235B - Package substrate and method for fabricating the same - Google Patents
Package substrate and method for fabricating the same Download PDFInfo
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- TWI394235B TWI394235B TW97114982A TW97114982A TWI394235B TW I394235 B TWI394235 B TW I394235B TW 97114982 A TW97114982 A TW 97114982A TW 97114982 A TW97114982 A TW 97114982A TW I394235 B TWI394235 B TW I394235B
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- resist layer
- package substrate
- solder resist
- electrical contact
- plated metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
本發明係有關於一種半導體裝置及其製法，尤指一種封裝基板及其製法。The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a package substrate and a method of fabricating the same.
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態，傳統半導體裝置主要係在一封裝基板(Package Substrate)或導線架(Lead Frame)上先裝置一例如積體電路之半導體晶片，再將半導體晶片以打線方式電性連接在該封裝基板或導線架上，接著以膠體進行封裝。自從IBM公司在1960年早期引入覆晶封裝(Flip Chip Package)技術以來，相較於打線(Wire Bond)技術，覆晶技術之特徵在於採用一封裝基板來安置半導體晶片，並於該封裝基板表面植置多數個成陣列排列之錫球(Solder balls)與半導體晶片間電性連接，再於該封裝基板與該半導體晶片間填入底膠，以加強機械性之連接。由於兩者間之電性連接並非透過一般金線，且覆晶技術除可提高封裝結構佈線密度，使相同單位面積上可以容納更多輸入/輸出連接端(I/O connection)以達高度集積化(Integration)之效，亦可降低封裝結構整體尺寸，達到微型化(Miniaturization)的封裝需求，更因不需使用導電路徑較細長之金線，以降低阻抗，而可提高電性功能。With the development of the electronics industry, today's electronic products have been designed in a light, short, and versatile manner. Semiconductor packaging technology has also developed different package types. Traditional semiconductor devices are mainly packaged in a package (Substrate Substrate). Or a semiconductor wafer such as an integrated circuit is mounted on the lead frame, and then the semiconductor wafer is electrically connected to the package substrate or the lead frame by wire bonding, and then encapsulated by a colloid. Since the introduction of Flip Chip Package technology by IBM in the early 1960s, flip chip technology has been characterized by the use of a package substrate to mount a semiconductor wafer on the surface of the package substrate compared to Wire Bond technology. A plurality of arrayed solder balls are electrically connected to the semiconductor wafer, and a primer is filled between the package substrate and the semiconductor wafer to strengthen the mechanical connection. Since the electrical connection between the two is not through the ordinary gold wire, and the flip chip technology can increase the wiring density of the package structure, the I/O connection can be accommodated in the same unit area to achieve high concentration. The effect of integration can also reduce the overall size of the package structure, achieve the miniaturization packaging requirements, and reduce the impedance by using a thin gold wire with a conductive path to improve the electrical function.
請參閱第1A至1E圖，係顯示現行覆晶技術之半導體 封裝結構之製法剖面示意圖；首先，如第1A圖所示，係提供一基板本體11，其表面具有置晶區11a及非置晶區11b，於該置晶區11a中形成複數電性接觸墊110；如第1B圖所示，於該基板本體11及該些電性接觸墊110上形成防焊層12，且該防焊層12具有複數防焊層開孔120以對應顯露該電性接觸墊110；如第1C圖所示，接著於該防焊層開孔120中之電性接觸墊110上形成焊接材料13；如第1D圖所示，於該基板本體11上接置半導體晶片14，該半導體晶片14具有複數電極墊141，於該些電極墊141上各形成有凸塊142，俾使該半導體晶片14藉由該凸塊142及焊接材料13以電性連接該基板本體11；最後如第1E圖所示，於該半導體晶片14與該防焊層12之間填充底膠15，藉以包覆該焊接材料13，並使該半導體晶片14與基板本體11之間形成良好機械性連接。Please refer to Figures 1A to 1E for the semiconductors of the current flip chip technology. A schematic diagram of the manufacturing process of the package structure; first, as shown in FIG. 1A, a substrate body 11 is provided, the surface of which has a crystallizing region 11a and a non-crystallizing region 11b, and a plurality of electrical contact pads are formed in the crystallizing region 11a. a solder resist layer 12 is formed on the substrate body 11 and the electrical contact pads 110, and the solder resist layer 12 has a plurality of solder mask openings 120 to correspondingly expose the electrical contacts. Pad 110; as shown in FIG. 1C, a solder material 13 is formed on the electrical contact pad 110 in the solder mask opening 120; as shown in FIG. 1D, the semiconductor wafer 14 is mounted on the substrate body 11. The semiconductor wafer 14 has a plurality of electrode pads 141, and the bumps 142 are formed on the electrode pads 141, so that the semiconductor wafer 14 is electrically connected to the substrate body 11 by the bumps 142 and the solder material 13; Finally, as shown in FIG. 1E, a primer 15 is filled between the semiconductor wafer 14 and the solder resist layer 12 to cover the solder material 13 and form a good mechanical property between the semiconductor wafer 14 and the substrate body 11. connection.
然而，習知之封裝結構中，該底膠15之流動範圍往往控制不易，因而造成該底膠15流動範圍擴大而漫延至非置晶區11b；若是該半導體晶片14位於該基板本體11邊緣，或是該基板本體11尺寸接近該半導體晶片14尺寸時，例如晶片尺寸級封裝件(CSP,Chip size package)，往往因底膠15漫流過基板本體11之邊緣，而於製造過程中使該底膠15沾黏在生產設備上之情形，如此一來，輕者必須額外增加清潔生產設備之費用以及封裝結構不良品的產生外，重者可能導致該生產設備損毀，導致成本增加之缺失。However, in the conventional package structure, the flow range of the primer 15 is often difficult to control, thereby causing the flow range of the primer 15 to expand and diffuse to the non-crystallized region 11b; if the semiconductor wafer 14 is located at the edge of the substrate body 11, or When the size of the substrate body 11 is close to the size of the semiconductor wafer 14, for example, a chip size package (CSP), the primer 15 is caused to flow over the edge of the substrate body 11, and the primer is used in the manufacturing process. 15 In the case of sticking to the production equipment, in this case, the lighter must additionally increase the cost of the cleaning production equipment and the production of defective packaging materials, which may cause damage to the production equipment, resulting in a lack of cost increase.
因此，如何提供一種封裝基板得以防止溢膠情形發生，業已成為該產業界之重要課題。Therefore, how to provide a package substrate to prevent overflow occurs has become an important issue in the industry.
鑑於上述習知技術之缺失，本發明之一目的係在於提供一種封裝基板及其製法，以避免底膠溢膠情形發生。In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a package substrate and a method of manufacturing the same to avoid the occurrence of a primer overflow.
本發明又一目的係在於提供一種封裝基板及其製法，可避免底膠污染生產設備。Another object of the present invention is to provide a package substrate and a method for manufacturing the same, which can prevent the primer from contaminating the production equipment.
為達上述及其他目的，本發明揭露一種封裝基板，係包括：基板本體，其至少一表面具有一置晶區及非置晶區，該置晶區具有複數電性接觸墊；防焊層，係設於該基板本體表面上，該防焊層並顯露該些電性接觸墊；以及電鍍金屬阻障環，係設於該非置晶區之防焊層上，並包圍該置晶區。To achieve the above and other objects, the present invention discloses a package substrate, comprising: a substrate body having at least one surface having a crystal region and a non-crystal region; the crystal region having a plurality of electrical contact pads; a solder resist layer; The solder resist layer is disposed on the surface of the substrate body, and the electrical contact pads are exposed; and the metal-plated barrier ring is disposed on the solder resist layer of the non-crystallized region and surrounds the crystallized region.
依上述之封裝基板，該非置晶區之防焊層中復具有埋柱孔，並於該埋柱孔中設有電鍍金屬柱，該電鍍金屬柱並接置該電鍍金屬阻障環，該埋柱孔係為一環狀溝槽、複數圓形開孔或長條形開孔，該電鍍金屬柱係為對應之環體、複數圓形柱或長條塊。According to the above package substrate, the solder resist layer of the non-crystallized region has a buried pillar hole, and a plating metal column is disposed in the buried pillar hole, and the plating metal pillar is connected to the plating metal barrier ring, and the buried metal The column hole is an annular groove, a plurality of circular openings or a long opening, and the plated metal column is a corresponding ring body, a plurality of circular columns or a long block.
復包括電鍍金屬增高層，係設於該電鍍金屬阻障環上，並可於該非置晶區之基板本體上設有電鍍金屬墊，且對應設在該電鍍金屬柱之下。The electroplated metal upper layer is disposed on the electroplated metal barrier ring, and the electroplated metal pad is disposed on the substrate body of the non-crystallizing region, and is correspondingly disposed under the electroplated metal post.
依上述之結構，復包括複數電鍍金屬凸塊，係分別對應設於各該電性接觸墊上，於該電鍍金屬凸塊上對應設有複數焊接材料。According to the above structure, the plurality of plated metal bumps are respectively disposed on the respective electrical contact pads, and the plurality of solder materials are correspondingly disposed on the plated metal bumps.
又依上述之結構，該防焊層具有複數防焊層開孔以分別對應顯露該些電性接觸墊；或該防焊層具有一防焊層開口以顯露全部該些電性接觸墊。According to the above structure, the solder resist layer has a plurality of solder mask openings to respectively expose the electrical contact pads; or the solder resist layer has a solder mask opening to expose all of the electrical contact pads.
本發明復提供一種封裝基板製法，係包括：提供一基板本體，於該基板本體之至少一表面具有一置晶區及非置晶區，於該置晶區形成複數電性接觸墊；於該基板本體上形成有防焊層，且該防焊層顯露該些電性接觸墊；以及於該非置晶區之防焊層上形成有電鍍金屬阻障環，以包圍該置晶區。The present invention provides a method for manufacturing a package substrate, comprising: providing a substrate body having a crystallized region and a non-crystallized region on at least one surface of the substrate body, and forming a plurality of electrical contact pads in the crystallographic region; A solder resist layer is formed on the substrate body, and the solder resist layer exposes the electrical contact pads; and a plating metal barrier ring is formed on the solder resist layer of the non-crystallized region to surround the crystallizing region.
依上述之封裝基板製法，於該非置晶區之防焊層中形成有埋柱孔，並於該埋柱孔中形成與該電鍍金屬阻障環相對應連接之電鍍金屬柱，其中該埋柱孔係為一環狀溝槽、複數圓形開孔或長條形開孔，該電鍍金屬柱係為對應之環體、複數圓形柱或長條塊，於該非置晶區之基板本體表面並可形成電鍍金屬墊，且對應形成於該電鍍金屬柱之下。According to the above method for manufacturing a package substrate, a pillar hole is formed in the solder resist layer of the non-crystallized region, and a plated metal pillar corresponding to the plated metal barrier ring is formed in the pillar hole, wherein the pillar is buried The hole system is an annular groove, a plurality of circular openings or a long hole, and the plated metal column is a corresponding ring body, a plurality of circular columns or a long block, and the surface of the substrate body of the non-crystallized area An electroplated metal pad may be formed and formed correspondingly under the electroplated metal pillar.
依上述之製法，復包括於該電鍍金屬阻障環上形成電鍍金屬增高層，於該些電性接觸墊上對應形成複數電鍍金屬凸塊，於該電鍍金屬凸塊上形成焊接材料。According to the above method, the electroplated metal barrier layer is formed on the electroplated metal barrier ring, and a plurality of electroplated metal bumps are formed on the electrical contact pads to form a solder material on the electroplated metal bump.
又依上述之製法，該防焊層中係形成複數防焊層開孔以分別對應顯露該些電性接觸墊；或該防焊層中係形成一防焊層開口以顯露全部該些電性接觸墊。According to the above method, a plurality of solder mask openings are formed in the solder resist layer to respectively expose the electrical contact pads; or a solder mask opening is formed in the solder resist layer to expose all of the electrical properties. Contact pad.
因此，本發明之封裝基板及其製法，係於基板本體表面之防焊層上之非置晶區設置電鍍金屬阻障環，於後續半導體晶片接置於該基板本體之置晶區、並於半導體晶片與 基板本體之間填充底膠後，藉以將該底膠限制於該電鍍金屬阻障環所圍構之範圍內，以避免產生溢膠之情況；且該電鍍金屬阻障環可連接設於該防焊層中之電鍍金屬柱，亦可使該電鍍金屬柱連接至設於基板本體之電鍍金屬墊，俾提高該電鍍金屬阻障環與防焊層之間的結合性，以防止該電鍍金屬阻障環於封裝過程中脫落。Therefore, the package substrate of the present invention and the method for fabricating the same are disposed on a non-crystallizing region on a solder resist layer on a surface of the substrate body, and a subsequent metal wafer is placed in a crystal region of the substrate body, and Semiconductor wafer and After the primer is filled between the substrate bodies, the primer is limited to the range enclosed by the plated metal barrier ring to avoid the occurrence of overflow; and the plated metal barrier ring can be connected to the protection The plated metal column in the solder layer may also connect the plated metal column to the plated metal pad provided on the substrate body to improve the bonding between the plated metal barrier ring and the solder resist layer to prevent the plated metal resistance The barrier ring falls off during the packaging process.
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.
請參閱第2A至2G圖以及第2E’圖，係詳細說明本發明之封裝基板及其製法之第一實施例的剖視圖。Referring to Figures 2A to 2G and Figure 2E', a cross-sectional view of a first embodiment of a package substrate and a method of manufacturing the same according to the present invention will be described in detail.
如第2A圖所示，首先，提供一基板本體21，於該基板本體21之至少一表面具有一置晶區21a及非置晶區21b，且於該置晶區21a形成複數電性接觸墊210。As shown in FIG. 2A, first, a substrate body 21 is provided, and at least one surface of the substrate body 21 has a crystal region 21a and a non-crystal region 21b, and a plurality of electrical contact pads are formed in the crystal region 21a. 210.
如第2B圖所示，於該基板本體21及該些電性接觸墊210上形成防焊層22，且於該防焊層22中形成複數防焊層開孔221，以分別對應顯露該些電性接觸墊210，其中該些防焊層開孔221可用雷射或曝光顯影方式形成。As shown in FIG. 2B, a solder resist layer 22 is formed on the substrate body 21 and the electrical contact pads 210, and a plurality of solder resist openings 221 are formed in the solder resist layer 22 to respectively expose the corresponding portions. The electrical contact pads 210, wherein the solder mask openings 221 are formed by laser or exposure development.
如第2C圖所示，於該防焊層22及該些電性接觸墊210上形成導電層23；並於該導電層23上形成第一阻層24a，且對應該些電性接觸墊210之位置經圖案化之曝光顯影製程以形成複數開孔240a，以顯露該些電性接觸墊 210上之導電層23，並形成包圍該些置晶區21a中之電性接觸墊210的環形開口241a，以顯露部份導電層23。As shown in FIG. 2C, a conductive layer 23 is formed on the solder resist layer 22 and the electrical contact pads 210; and a first resist layer 24a is formed on the conductive layer 23, and corresponding to the electrical contact pads 210. The position is subjected to a patterned exposure and development process to form a plurality of openings 240a to expose the electrical contact pads The conductive layer 23 on 210 forms an annular opening 241a surrounding the electrical contact pads 210 in the seed regions 21a to expose a portion of the conductive layer 23.
如第2D圖所示，於該些開孔240a中之導電層23上電鍍形成複數電鍍金屬凸塊251，且於該環形開口241a中之導電層23上電鍍形成電鍍金屬阻障環252，並於該些電鍍金屬凸塊251上電鍍形成焊接材料26、及該電鍍金屬阻障環252上電鍍形成電鍍金屬增高層26’。As shown in FIG. 2D, a plurality of plated metal bumps 251 are plated on the conductive layer 23 of the openings 240a, and a plating metal barrier ring 252 is formed on the conductive layer 23 in the annular opening 241a. The electroplated metal bumps 251 are plated to form a solder material 26, and the plated metal barrier ring 252 is plated to form a plated metal raised layer 26'.
如第2E及2E’圖所示，移除該第一阻層24a及其所覆蓋之導電層23，以顯露該電鍍金屬凸塊251及其上之焊接材料26、與該電鍍金屬阻障環252及其上之電鍍金屬增高層26’，以完成本發明之封裝基板，其俯視圖如第2E’圖所示。As shown in FIGS. 2E and 2E', the first resistive layer 24a and the conductive layer 23 covered thereon are removed to expose the plated metal bump 251 and the solder material 26 thereon, and the plated metal barrier ring. 252 and the plated metal upper layer 26' thereon are used to complete the package substrate of the present invention, and the top view thereof is as shown in FIG. 2E'.
如第2F圖所示，係本發明之封裝基板之應用實例，於該基板本體21上設置半導體晶片27，該半導體晶片27具有複數電極墊271，於該些電極墊271上各形成凸塊272，並使該凸塊272藉由該焊接材料26以接置於該電鍍金屬凸塊251上，進而使該半導體晶片27電性連接該基板本體21，且該電鍍金屬增高層26’包覆該電鍍金屬阻障環252。As shown in FIG. 2F, in an application example of the package substrate of the present invention, a semiconductor wafer 27 is disposed on the substrate body 21. The semiconductor wafer 27 has a plurality of electrode pads 271, and bumps 272 are formed on the electrode pads 271. And the bump 272 is attached to the plating metal bump 251 by the solder material 26, thereby electrically connecting the semiconductor wafer 27 to the substrate body 21, and the plating metal high-rise layer 26' covers the A metal barrier ring 252 is plated.
最後，如第2G圖所示，於該半導體晶片27與該防焊層22之間、以及該電鍍金屬阻障環252所圍構之空間內填充底膠28，由於該防焊層22上形成電鍍金屬增高層26’與其所包覆之電鍍金屬阻障環252，俾將該底膠28限制在該電鍍金屬增高層26’與該電鍍金屬阻障環252所圍 構之範圍內，以達到防止溢膠之目的。Finally, as shown in FIG. 2G, a primer 28 is filled in the space surrounded by the semiconductor wafer 27 and the solder resist layer 22 and the metal-plated barrier ring 252, and formed on the solder resist layer 22. The plated metal raised layer 26' and the coated metal barrier ring 252 coated thereon are limited to the plating metal 28 and the plated metal barrier ring 252 Within the scope of the structure, in order to prevent the spill.
請參閱第3A至第3D’圖，係本實施例另一態樣之製法側面剖視流程圖以及俯視圖，其不同處係如第3A圖所示，該基板本體21及該些電性接觸墊210上形成防焊層22後，係於該防焊層22中形成一防焊層開口221’，以顯露全部該些電性接觸墊210，其中該防焊層開口221’可用曝光顯影方式形成。Please refer to FIGS. 3A to 3D', which are side cross-sectional views and top views of another embodiment of the embodiment, and the difference is as shown in FIG. 3A, the substrate body 21 and the electrical contact pads. After the solder resist layer 22 is formed on the 210, a solder mask opening 221 ′ is formed in the solder resist layer 22 to expose all of the electrical contact pads 210 , wherein the solder resist opening 221 ′ can be formed by exposure development. .
本發明復揭露一種封裝基板，如第2E圖及第3D圖所示，係包括：基板本體21，其至少一表面具有一置晶區21a及非置晶區21b，該置晶區21a具有複數電性接觸墊210；防焊層22，係設於該基板本體21表面上，該防焊層22並顯露該些電性接觸墊210；以及電鍍金屬阻障環252，係設於該非置晶區21b之防焊層22上，並包圍該置晶區21a。The present invention discloses a package substrate, as shown in FIGS. 2E and 3D, comprising: a substrate body 21 having at least one surface having a crystal region 21a and a non-crystal region 21b, the crystal region 21a having a plurality The electrical contact pad 210 is disposed on the surface of the substrate body 21, and the solder resist layer 22 exposes the electrical contact pads 210; and the plated metal barrier ring 252 is disposed on the non-crystallized layer The solder resist layer 22 of the region 21b surrounds the crystal region 21a.
上述結構中，復包括電鍍金屬增高層26’，係設於該電鍍金屬阻障環252上。In the above structure, the electroplated metal elevated layer 26' is provided on the electroplated metal barrier ring 252.
上述結構中，復包括複數電鍍金屬凸塊251，係對應設於該電性接觸墊210上；復包括複數焊接材料26，係對應設於該電鍍金屬凸塊251上。In the above structure, the plurality of plated metal bumps 251 are provided on the electrical contact pads 210, and the plurality of solder materials 26 are provided on the plated metal bumps 251.
上述結構中，該防焊層22具有複數防焊層開孔221以分別對應顯露該些電性接觸墊210，如第2E圖所示；或者，該防焊層22具有一防焊層開口221’以顯露全部該些電性接觸墊210，如第3D圖所示。In the above structure, the solder resist layer 22 has a plurality of solder resist openings 221 to respectively expose the electrical contact pads 210, as shown in FIG. 2E; or the solder resist layer 22 has a solder resist opening 221 'To reveal all of the electrical contact pads 210, as shown in Figure 3D.
請參閱第4A至4E圖，係詳細說明本發明之封裝基板及其製法第二實施例之側面剖視流程圖。Referring to Figures 4A to 4E, a side cross-sectional view of a second embodiment of a package substrate and a method of manufacturing the same according to the present invention will be described in detail.
如第4A圖所示，提供一係如第2C圖所示之結構，並於該第一阻層24a之開孔240a中的導電層23上電鍍形成複數電鍍金屬凸塊251，且於該環形開口241a中之導電層23上電鍍形成電鍍金屬阻障環252。As shown in FIG. 4A, a structure as shown in FIG. 2C is provided, and a plurality of plated metal bumps 251 are formed on the conductive layer 23 in the opening 240a of the first resist layer 24a, and the ring is formed in the ring. A plating metal barrier ring 252 is formed by electroplating on the conductive layer 23 in the opening 241a.
如第4B圖所示，再於該第一阻層24a上形成第二阻層24b，且形成有開口區240b以顯露該些電鍍金屬凸塊251。As shown in FIG. 4B, a second resist layer 24b is formed on the first resist layer 24a, and an opening region 240b is formed to expose the plated metal bumps 251.
如第4C圖所示，於該些電鍍金屬凸塊251上電鍍形成焊接材料26。As shown in FIG. 4C, solder materials 26 are formed by electroplating on the electroplated metal bumps 251.
如第4D圖所示，移除該第二阻層24b、第一阻層24a及為該第一阻層24a所覆蓋之導電層23，以顯露該電鍍金屬阻障環252、電鍍金屬凸塊251及其上之焊接材料26，以完成本發明之封裝基板；如第4D’圖所示，係本實施例之另一態樣，其不同處係於該防焊層22中形成一防焊層開口221’，以顯露全部該些電性接觸墊210。As shown in FIG. 4D, the second resistive layer 24b, the first resistive layer 24a, and the conductive layer 23 covered by the first resistive layer 24a are removed to expose the plated metal barrier ring 252 and the plated metal bumps. 251 and the solder material 26 thereon to complete the package substrate of the present invention; as shown in FIG. 4D', another aspect of the embodiment is different in the solder resist layer 22 to form a solder resist The layer openings 221' are used to expose all of the electrical contact pads 210.
如第4E圖所示，係本發明之封裝基板之應用實例，於該半導體晶片27與該防焊層22之間、以及該電鍍金屬阻障環252所圍構之空間內填充底膠28，由於該防焊層22上形成電鍍金屬阻障環252，藉由該電鍍金屬阻障環252將該底膠28限制在該電鍍金屬阻障環252所圍構之範圍內，以達到防止溢膠之目的。As shown in FIG. 4E, an application example of the package substrate of the present invention is filled with a primer 28 between the semiconductor wafer 27 and the solder resist layer 22 and the space surrounded by the plated metal barrier ring 252. Since the electroplated metal barrier ring 252 is formed on the solder resist layer 22, the underfill 28 is limited by the electroplated metal barrier ring 252 to the range enclosed by the electroplated metal barrier ring 252 to prevent overfilling. The purpose.
請參閱第5A至5D’圖以及第6A至6C’圖，係分別說明本發明之封裝基板及其製法之第三實施例，本實施例與第二實施例之主要差異處在於該防焊層復具有至少一埋柱孔貫通該防焊層且連接該電鍍金屬阻障環。Please refer to FIGS. 5A to 5D' and FIGS. 6A to 6C', which respectively illustrate a third embodiment of the package substrate and the method for manufacturing the same according to the present invention. The main difference between the embodiment and the second embodiment lies in the solder resist layer. The at least one buried pillar hole penetrates the solder resist layer and connects the plated metal barrier ring.
如第5A圖所示，於該防焊層22上形成複數防焊層開孔221，以對應顯露該電性接觸墊210，且於該防焊層22上預定形成上述之電鍍金屬阻障環形成有至少一貫穿該防焊層22之埋柱孔222，以顯露部份基板本體21。As shown in FIG. 5A, a plurality of solder mask openings 221 are formed on the solder resist layer 22 to correspondingly expose the electrical contact pads 210, and the above-mentioned plated metal barrier ring is predetermined to be formed on the solder resist layer 22. At least one of the pillar holes 222 penetrating the solder resist layer 22 is formed to expose a portion of the substrate body 21.
如第5B圖所示，於該防焊層22、顯露之電性接觸墊210及顯露之基板本體21表面形成導電層23，並於該導電層23上形成第一阻層24a，且對應該些電性接觸墊210形成複數開孔240a，以對應顯露該些電性接觸墊210上之導電層23，並形成包圍該置晶區21a中之電性接觸墊210的環形開口241a，且該環形開口241a對應該防焊層22上之埋柱孔222，以顯露該埋柱孔222中之導電層23；然後，於該第一阻層24a之開孔240a中的導電層23上電鍍形成複數電鍍金屬凸塊251，且於該防焊層22上之埋柱孔222及環形開口241a中之導電層23上電鍍形成電鍍金屬阻障環252，且於該防焊層22之埋柱孔222中形成連接在電鍍金屬阻障環252下方之電鍍金屬柱252a，俾以提高該電鍍金屬阻障環252與防焊層22之間的結合性。As shown in FIG. 5B, a conductive layer 23 is formed on the surface of the solder resist layer 22, the exposed electrical contact pad 210, and the exposed substrate body 21, and a first resist layer 24a is formed on the conductive layer 23, and corresponds to The electrical contact pads 210 are formed with a plurality of openings 240a to correspondingly expose the conductive layers 23 on the electrical contact pads 210, and form an annular opening 241a surrounding the electrical contact pads 210 in the crystallizing region 21a. The annular opening 241a corresponds to the buried hole 222 on the solder resist layer 22 to expose the conductive layer 23 in the buried via hole 222; then, is formed on the conductive layer 23 in the opening 240a of the first resistive layer 24a. The plurality of metal bumps 251 are plated, and the plated holes 222 on the solder resist layer 22 and the conductive layer 23 in the annular opening 241a are plated to form a plated metal barrier ring 252, and the pillar holes of the solder resist layer 22 are formed. A plated metal post 252a is formed 222 under the plated metal barrier ring 252 to improve the bond between the plated metal barrier ring 252 and the solder resist layer 22.
如第5C圖所示，再於該第一阻層24a上形成第二阻層24b，且形成有開口區240b以顯露該些電鍍金屬凸塊251，復於該些電鍍金屬凸塊251上電鍍形成焊接材料26。As shown in FIG. 5C, a second resist layer 24b is formed on the first resist layer 24a, and an opening region 240b is formed to expose the electroplated metal bumps 251, and plating is performed on the electroplated metal bumps 251. A solder material 26 is formed.
接著，如第5D及5D，圖所示，移除該第二阻層24b、第一阻層24a及為該第一阻層24a所覆蓋之導電層23，以顯露該電鍍金屬阻障環252、電鍍金屬凸塊251及其上之焊接材料26，以完成本發明之封裝基板，如第5D圖所示；或如第5D’圖所示，係本實施例之另一態樣，其不同處係於該防焊層22中形成一防焊層開口221’，以顯露全部該些電性接觸墊210。Next, as shown in FIGS. 5D and 5D, the second resist layer 24b, the first resist layer 24a, and the conductive layer 23 covered by the first resist layer 24a are removed to expose the plated metal barrier ring 252. And plating the metal bumps 251 and the solder material 26 thereon to complete the package substrate of the present invention, as shown in FIG. 5D; or as shown in FIG. 5D′, another aspect of the embodiment, different A solder mask opening 221 ′ is formed in the solder resist layer 22 to expose all of the electrical contact pads 210 .
另外，於本實施例之封裝基板，該電鍍金屬柱252a之平面形狀係為一環體、複數圓形柱或長條塊。In addition, in the package substrate of the embodiment, the planar shape of the plated metal pillar 252a is a ring body, a plurality of circular columns or a long block.
請配合參閱第6A至6C圖，係為第5A圖之俯視圖；該防焊層22之埋柱孔222係為單一環狀溝槽，使形成於該埋柱孔222中之電鍍金屬柱252a之平面形狀例如為一環體，如第6A圖所示；或該埋柱孔222係為複數圓形開孔，使該電鍍金屬柱252a例如為複數圓形柱，且設於該些電性接觸墊210周圍，如第6B圖所示；或該埋柱孔222係為複數長條形開孔，使該電鍍金屬柱252a例如為複數長條塊，且設於該些電性接觸墊210周圍，如第6C圖所示。Please refer to FIG. 6A to FIG. 6C as a top view of FIG. 5A; the pillar hole 222 of the solder resist layer 22 is a single annular trench, so that the plated metal pillar 252a formed in the pillar hole 222 is formed. The planar shape is, for example, a ring body, as shown in FIG. 6A; or the buried hole 222 is a plurality of circular openings, such that the plated metal posts 252a are, for example, a plurality of circular columns, and are disposed on the electrical contact pads. The galvanic metal post 252a is, for example, a plurality of elongated strips, and is disposed around the electrical contact pads 210, as shown in FIG. 6B. As shown in Figure 6C.
第6A’至6C’圖係第6A至6C圖之另一態樣，其不同處係於該防焊層22中形成一防焊層開口221’，以顯露全部該些電性接觸墊210。6A' to 6C' are another aspect of Figs. 6A to 6C, in which a solder resist opening 221' is formed in the solder resist layer 22 to expose all of the electrical contact pads 210.
本實施例中，主要係於該第一阻層24a之環形開口241a中電鍍形成電鍍金屬阻障環252，且於該防焊層22之埋柱孔222中形成電鍍金屬柱252a，俾以提高該電鍍 金屬阻障環252與防焊層22之間的結合性，以防止該電鍍金屬阻障環252於封裝過程中脫落，而可確保產品之可靠度。In this embodiment, the plated metal barrier 252 is formed by electroplating in the annular opening 241a of the first resistive layer 24a, and the plated metal pillar 252a is formed in the buried hole 222 of the solder resist layer 22 to improve The plating The bond between the metal barrier ring 252 and the solder resist layer 22 prevents the plated metal barrier ring 252 from falling off during the packaging process, thereby ensuring product reliability.
請參閱第7A至7D圖，係說明本發明之封裝基板及其製法之第四實施例之剖視圖，本實施例與前述各實施例主要差異之處在於基板本體上復形成電鍍金屬墊，並與形成於防焊層之埋柱孔中的電鍍金屬柱連接。7A to 7D are cross-sectional views illustrating a fourth embodiment of the package substrate and the method of fabricating the same according to the present invention. The main difference between the embodiment and the foregoing embodiments is that a plated metal pad is formed on the substrate body, and A plated metal post is formed in the buried hole of the solder resist layer.
如第7A圖所示，提供一基板本體21，於該基板本體21表面之置晶區21a中形成複數電性接觸墊210及於該非置晶區21b中形成至少一電鍍金屬墊211，且於該防焊層22形成複數防焊層開孔221，以對應顯露該些電性接觸墊210，且於該防焊層22中形成複數埋柱孔222，以對應顯露該些電鍍金屬墊211及基板本體21；該埋柱孔222之平面形狀可如第6A至6C圖所示之結構。As shown in FIG. 7A, a substrate body 21 is provided, a plurality of electrical contact pads 210 are formed in the crystal region 21a on the surface of the substrate body 21, and at least one plated metal pad 211 is formed in the non-crystallized region 21b. The solder resist layer 22 forms a plurality of solder mask openings 221 to correspondingly expose the electrical contact pads 210, and a plurality of buried via holes 222 are formed in the solder resist layer 22 to correspondingly expose the plating metal pads 211 and The substrate body 21; the planar shape of the buried hole 222 can be as shown in FIGS. 6A to 6C.
如第7B圖所示，於該防焊層22、顯露之電性接觸墊210、顯露之基板本體21、及該電鍍金屬墊211表面形成導電層23，且於該導電層23上形成第一阻層24a，其中該第一阻層24a對應該些電性接觸墊210形成複數開孔240a，以對應顯露該些電性接觸墊210上之導電層23，並形成包圍該置晶區21a中之電性接觸墊210的環形開口241a，以顯露部份防焊層22及該埋柱孔222中之導電層23；然後，於該第一阻層24a之開孔240a中的導電層23上電鍍形成複數電鍍金屬凸塊251，且於該防焊層22上 之埋柱孔222及環形開口241a中之導電層23上電鍍形成電鍍金屬阻障環252，並於該防焊層22之埋柱孔222中形成電鍍金屬柱252a以電性連接該電鍍金屬墊211，使該電鍍金屬阻障環252藉由電鍍金屬柱252a以電性連接該電鍍金屬墊211。As shown in FIG. 7B, a conductive layer 23 is formed on the surface of the solder resist layer 22, the exposed electrical contact pad 210, the exposed substrate body 21, and the plated metal pad 211, and the first layer is formed on the conductive layer 23. The resistive layer 24a, wherein the first resistive layer 24a forms a plurality of openings 240a corresponding to the electrical contact pads 210 to correspondingly expose the conductive layer 23 on the electrical contact pads 210, and is formed to surround the crystallizing region 21a. The annular opening 241a of the electrical contact pad 210 is formed to expose a portion of the solder resist layer 22 and the conductive layer 23 in the buried via hole 222; and then on the conductive layer 23 in the opening 240a of the first resist layer 24a. Electroplating forms a plurality of plated metal bumps 251 and is on the solder resist layer 22 A plated metal barrier 252 is formed on the conductive layer 23 of the buried via hole 222 and the annular opening 241a, and a plated metal pillar 252a is formed in the buried via hole 222 of the solder resist layer 22 to electrically connect the plated metal pad. 211, the plated metal barrier ring 252 is electrically connected to the plated metal pad 211 by plating the metal post 252a.
接著如第7C圖所示，於該第一阻層24a上形成第二阻層24b，且形成有開口區240b以顯露該些電鍍金屬凸塊251，復於該些電鍍金屬凸塊251上電鍍形成焊接材料26。Then, as shown in FIG. 7C, a second resist layer 24b is formed on the first resist layer 24a, and an opening region 240b is formed to expose the electroplated metal bumps 251, which are plated on the electroplated metal bumps 251. A solder material 26 is formed.
接著，如第7D及7D’圖所示，移除該第二阻層24b、第一阻層24a及為該第一阻層24a所覆蓋之導電層23，以顯露該電鍍金屬阻障環252、電鍍金屬凸塊251及其上之焊接材料26，以完成本發明之封裝基板，如第7D圖所示；或如第7D’圖所示，係本實施例之另一態樣，其不同處係於該防焊層22中形成一防焊層開口221’，以顯露全部該些電性接觸墊210。Next, as shown in FIGS. 7D and 7D', the second resist layer 24b, the first resist layer 24a, and the conductive layer 23 covered by the first resist layer 24a are removed to expose the plated metal barrier ring 252. And plating the metal bumps 251 and the solder material 26 thereon to complete the package substrate of the present invention, as shown in FIG. 7D; or as shown in FIG. 7D', another aspect of the embodiment is different A solder mask opening 221 ′ is formed in the solder resist layer 22 to expose all of the electrical contact pads 210 .
於本實施例中，主要係藉由該電鍍金屬阻障環252連接該埋柱孔222中之電鍍金屬柱252a，且該電鍍金屬柱252a連接設於該基板本體21之電鍍金屬墊211，以提高該電鍍金屬阻障環252與該防焊層22之間的結合性。In this embodiment, the plated metal post 252a is connected to the plated metal hole 252 by the plated metal barrier ring 252, and the plated metal post 252a is connected to the plated metal pad 211 of the substrate body 21 to The bond between the plated metal barrier ring 252 and the solder resist layer 22 is improved.
因此，本發明之封裝基板及其製法，係於基板本體表面之防焊層上的非置晶區設置電鍍金屬阻障環，於後續半導體晶片接置於該基板本體之置晶區、並於半導體晶片與基板本體之間填充底膠後，藉以將該底膠限制於該電鍍金 屬阻障環所圍構之範圍內，以避免產生溢膠之情況；且該電鍍金屬阻障環可連接設於該防焊層中之電鍍金屬柱，亦可使該電鍍金屬柱連接至設於基板本體之電鍍金屬墊，俾提高該電鍍金屬阻障環與防焊層之間的結合性，以防止該電鍍金屬阻障環於封裝過程中脫落。Therefore, the package substrate of the present invention and the method for fabricating the same are disposed on a non-crystallizing region on a solder resist layer on a surface of the substrate body, and a subsequent step of placing the semiconductor wafer on the substrate of the substrate body. After the primer is filled between the semiconductor wafer and the substrate body, the primer is limited to the plating gold It is within the range of the barrier ring to avoid overflowing; and the plated metal barrier ring can be connected to the plated metal column provided in the solder resist layer, and the plated metal column can be connected to the device. The metal pad on the substrate body increases the bond between the plated metal barrier ring and the solder resist layer to prevent the plated metal barrier ring from falling off during the packaging process.
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.
11、21‧‧‧基板本體11, 21‧‧‧ substrate body
11a、21a‧‧‧置晶區11a, 21a‧‧‧ crystal zone
11b、21b‧‧‧非置晶區11b, 21b‧‧‧ non-crystallized area
110、210‧‧‧電性接觸墊110, 210‧‧‧Electrical contact pads
12、22‧‧‧防焊層12, 22‧‧‧ solder mask
120、221‧‧‧防焊層開孔120, 221‧‧‧ solder mask opening
13、26‧‧‧焊接材料13, 26‧‧‧ welding materials
14、27‧‧‧半導體晶片14, 27‧‧‧ semiconductor wafer
141、271‧‧‧電極墊141, 271‧‧‧ electrode pads
142、272‧‧‧凸塊142, 272‧‧ ‧ bumps
15、28‧‧‧底膠15, 28‧‧ ‧ primer
211‧‧‧電鍍金屬墊211‧‧‧Electroplated metal mat
221’‧‧‧防焊層開口221'‧‧‧ solder mask opening
222‧‧‧埋柱孔222‧‧‧ buried hole
23‧‧‧導電層23‧‧‧ Conductive layer
24a‧‧‧第一阻層24a‧‧‧First resistance layer
240a‧‧‧開孔240a‧‧‧ opening
240b‧‧‧開口區240b‧‧‧Open area
241a‧‧‧環形開口241a‧‧‧Circular opening
24b‧‧‧第二阻層24b‧‧‧second barrier layer
251‧‧‧電鍍金屬凸塊251‧‧‧Electroplated metal bumps
252‧‧‧電鍍金屬阻障環252‧‧‧Electroplated metal barrier ring
252a‧‧‧電鍍金屬柱252a‧‧‧Electroplated metal column
26’‧‧‧電鍍金屬增高層26’‧‧‧Electrified metal
第1A至1E圖係習知封裝基板之剖視示意圖；第2A至2G圖係為本發明之封裝基板及其製法之第一實施例剖視示意圖；第2E’圖係為第2E圖之俯視圖；第3A至3D圖係為本發明之封裝基板及其製法第二實施例之剖視示意圖；第3D’圖係為第3D圖之俯視圖；第4A至4E圖係本發明之封裝基板及其製法之第三實施例剖視示意圖；第4D’圖係為第4D圖之另一態樣之剖視示意圖；第5A至5D圖係本發明之封裝基板及其製法之第四實施例之剖視示意圖；第5D’圖係為第5D圖之另一態樣之剖視示意圖； 第6A至6C圖係分別為第5A圖之俯視圖；第6A’至6C’圖係分別為第6A至6C圖之另一態樣；第7A至7D圖係本發明之封裝基板第四實施例之剖視示意圖；以及第7D’圖係為第7D圖之另一態樣之剖視示意圖。1A to 1E are schematic cross-sectional views of a conventional package substrate; FIGS. 2A to 2G are cross-sectional views showing a first embodiment of the package substrate and the method of manufacturing the same according to the present invention; and FIG. 2E' is a plan view of FIG. 2E 3A to 3D are schematic cross-sectional views showing a package substrate of the present invention and a second embodiment thereof; FIG. 3D' is a plan view of FIG. 3D; and FIGS. 4A to 4E are package substrates of the present invention; A cross-sectional view of a third embodiment of the method of manufacture; a 4D' diagram is a cross-sectional view of another aspect of the 4D diagram; and 5A to 5D are diagrams of a fourth embodiment of the package substrate of the present invention and the method of manufacturing the same Figure 5D is a schematic cross-sectional view of another aspect of Figure 5D; 6A to 6C are plan views of FIG. 5A, respectively; FIGS. 6A' to 6C' are another aspect of FIGS. 6A to 6C; and FIGS. 7A to 7D are drawings of the fourth embodiment of the package substrate of the present invention. A schematic cross-sectional view; and a 7D' diagram is a schematic cross-sectional view of another aspect of the 7D.
21‧‧‧基板本體21‧‧‧Substrate body
21a‧‧‧置晶區21a‧‧‧Setting area
21b‧‧‧非置晶區21b‧‧‧Non-crystal zone
210‧‧‧電性接觸墊210‧‧‧Electrical contact pads
22‧‧‧防焊層22‧‧‧ solder mask
26‧‧‧焊接材料26‧‧‧Welding materials
23‧‧‧導電層23‧‧‧ Conductive layer
251‧‧‧電鍍金屬凸塊251‧‧‧Electroplated metal bumps
252‧‧‧電鍍金屬阻障環252‧‧‧Electroplated metal barrier ring
26’‧‧‧電鍍金屬增高層26’‧‧‧Electrified metal
Claims (18)
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| TW97114982A TWI394235B (en) | 2008-04-24 | 2008-04-24 | Package substrate and method for fabricating the same |
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| TW97114982A TWI394235B (en) | 2008-04-24 | 2008-04-24 | Package substrate and method for fabricating the same |
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| TWI394235B true TWI394235B (en) | 2013-04-21 |
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| TWI736802B (en) * | 2018-10-23 | 2021-08-21 | 矽品精密工業股份有限公司 | Electronic package |
| US20230009495A1 (en) * | 2021-07-09 | 2023-01-12 | Innolux Corporation | Electronic device and manufacturing method thereof |
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| TWI223974B (en) * | 2003-11-20 | 2004-11-11 | Advanced Semiconductor Eng | Tiny memory card and method for manufacturing the same |
| TW200739703A (en) * | 2006-04-13 | 2007-10-16 | shi-jun Chen | Chip scale package |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI223974B (en) * | 2003-11-20 | 2004-11-11 | Advanced Semiconductor Eng | Tiny memory card and method for manufacturing the same |
| TW200739703A (en) * | 2006-04-13 | 2007-10-16 | shi-jun Chen | Chip scale package |
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