JP2007073808A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which forms an empty groove for preventing the delamination of the interlayer dielectric of a semiconductor device that a low dielectric-constant film is used as the interlayer dielectric, and uses no thick resist film so as to prevent dust from occurring; and to provide the semiconductor device which is formed through the manufacturing method and high in moisture-resistant properties. <P>SOLUTION: A hard mask for etching the interlayer dielectric is formed by patterning the uppermost metal layer 5 of a multilevel interconnection insulated by the interlayer dielectric 3, and the interlayer dielectric 3 is etched using the mask to form the empty groove 4 which is located in the periphery of the semiconductor substrate 1 to makes its surface exposed. A wiring pattern containing pads 2g is formed by patterning the metal layer 5 which has been used as a mask, at least a passivation film 6 is formed on the surface of the semiconductor substrate 1 where the empty groove 4 is formed, and an opening is provided to the passivation film 6 to make the pads 2g exposed. The passivation film 6 is embedded in the empty groove 4, so that the interface of the low dielectric-constant film is protected, and the semiconductor device can be improved in moisture-resistant properties. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device using an insulating film with a low dielectric constant (hereinafter referred to as a low dielectric constant film or a low-k film) as an interlayer insulating film, and a semiconductor device formed by this manufacturing method. It is.

  As semiconductor devices are highly integrated, further miniaturization of patterns has been demanded. In addition, attempts have been made to reduce wiring resistance and parasitic resistance in order to increase the response speed. In order to increase the speed of a semiconductor device, a reduction in wiring parasitic capacitance is required, and a reduction in dielectric constant of an interlayer insulating film is being studied. Examples of the low dielectric constant insulating film (Low-k film) include silk, flare, and other organic films such as CF-based Teflon (registered trademark), and porous and relatively brittle inorganic films such as inorganic silicon oxide films. An organic silicon oxide film having an organic component containing a carbon atom in a film or an inorganic film can be given. Whereas the relative dielectric constant of the conventional oxide film is about 4, these insulating films have a relative dielectric constant of 3 or less.

In a conventional semiconductor device having a multilayer wiring, a low dielectric constant film may be used as an interlayer insulating film having a wiring pattern that is particularly highly miniaturized with high integration. In particular, the lower wiring has a low wiring width of 130 nm, and a low dielectric constant film is used as the interlayer insulating film.
Such a low dielectric constant film is fragile and is likely to be subjected to thermal stress caused by a difference in thermal expansion coefficient between the semiconductor substrate and the interlayer insulating film, so that disconnection or the like often occurs. In order to prevent such problems as disconnection, a groove (hereinafter referred to as an empty trench) in which the silicon surface is exposed is formed in the interlayer insulating film in the vicinity of the periphery of a semiconductor chip such as silicon constituting the semiconductor device to prevent film peeling. It is known.

The manufacturing method of the semiconductor device having the empty moat is performed by the following steps.
First, (1) forming a multilayer wiring insulated with an interlayer insulating film on the surface of a semiconductor wafer such as silicon on which a semiconductor element is formed for each chip formation region, and a metal such as aluminum to be the uppermost layer wiring of this multilayer wiring The layer is formed by sputtering or the like. A low dielectric constant film (Low-k film) is used as the interlayer insulating film. (2) Next, this metal layer is etched using a patterned photoresist as a mask to form a wiring pattern including pads. (3) Next, after removing the photoresist, a passivation film made of at least one insulating film is formed on the multilayer wiring including the uppermost wiring pattern. (4) Next, a photoresist is formed on the passivation film, and this is patterned into a predetermined shape to form an empty moat forming mask.

  (5) Next, the passivation film and the underlying interlayer insulating film are etched by, for example, RIE using the mask for forming the cavity, thereby forming an cavity that reaches the surface of the semiconductor wafer. (6) Next, the pad is opened by etching away the passivation film formed on the pad using a pad opening mask made of polyimide or the like. (7) Finally, the wafer is diced along a dicing line to form a plurality of semiconductor chips. In such a chip-shaped semiconductor device, a hollow is formed in the passivation film as a measure for preventing film peeling of the low-k interlayer insulating film.

However, in such a semiconductor device having a low-k film, since the interlayer insulating film is thick, the photoresist is also etched during RIE, so that resist film thickness control and processing of generated dust are problematic. It has become.
Patent Document 1 discloses that an LSI using a low-k film as an interlayer insulating film prevents the interlayer insulating film from peeling off by forming a groove opening penetrating the low-k film on the outer periphery of the semiconductor chip. Has been. Patent Document 2 discloses that a high aspect ratio via is accurately formed by etching a barrier layer, an insulating layer, a stop layer, an insulating layer, and a cap layer stacked on a Cu wiring using an aluminum hard mask. It is described in.
JP 2004-172169 A US Pat. No. 6,620,727

  According to the present invention, an empty trench formed to prevent peeling of an interlayer insulating film of a semiconductor device using a low dielectric constant film (Low-k film) as an interlayer insulating film can be formed without using a thick film resist. A manufacturing method of a semiconductor device that suppresses generation of dust and a highly moisture-resistant semiconductor device formed by this manufacturing method are provided.

  According to one aspect of the method for manufacturing a semiconductor device of the present invention, a metal layer constituting the uppermost layer of a multilayer wiring in which semiconductor elements are insulated from each other by an interlayer insulating film is formed on a semiconductor wafer in which a semiconductor element is formed for each chip formation region. A step of patterning the metal layer to form a hard mask for etching the interlayer insulating film; and etching the interlayer insulating film using the hard mask as a mask to surround a chip formation region of the semiconductor wafer Forming a hollow in which the wafer surface is exposed at a portion; patterning a metal layer used as the mask to form a wiring pattern including a pad; and at least one semiconductor wafer surface on which the hollow is formed Forming a passivation film made of an insulating film, and opening the passivation film to form the passivation film. Exposing a, by dicing the semiconductor wafer for each of the chip formation region is characterized by comprising the step of forming a plurality of semiconductor chips.

  Since the metal constituting the uppermost wiring layer of the multilayer wiring structure is used as a hard mask, it is not necessary to use a thick film resist and generation of dust can be suppressed. Further, in the semiconductor device formed by this semiconductor device manufacturing method, since the passivation film is embedded in the hollow, the interface of the low dielectric constant film is protected and the moisture resistance is improved.

  Hereinafter, embodiments of the invention will be described with reference to examples.

First, Embodiment 1 will be described with reference to FIGS.
1 to 5 are cross-sectional views of a manufacturing process of a semiconductor device using a low dielectric constant film in a multilayer wiring structure described in this embodiment.
A semiconductor element or a semiconductor integrated circuit is formed on a surface region of a semiconductor substrate 1 (pointing to a chip formation region) constituting a semiconductor wafer such as silicon (FIG. 1A). Next, a multilayer wiring structure is formed on the semiconductor substrate 1 except for the uppermost wiring layer by a known technique. The multilayer wiring structure is composed of a plurality of interlayer insulating films 3 and the multilayer wiring 2 insulated by the interlayer insulating film 3 (FIG. 1B). A metal layer 5 made of, for example, aluminum or an aluminum alloy is formed on the interlayer insulating film 3 having a multilayer wiring structure by using a technique such as sputtering or vacuum deposition (FIG. 1C).

  Thereafter, a resist 7 is applied and patterned to form a mask for etching the metal layer 5 (FIG. 2A). Next, the metal layer 5 is etched using the patterned resist 7 as a mask to form a mask for etching the interlayer insulating film 3 (FIG. 2B). Thereafter, the resist 7 on the patterned metal layer 5 is removed (FIG. 2C).

  Next, the surface of the semiconductor substrate 1 is exposed using anisotropic etching such as RIE (Reactive Ion Etching) along the peripheral portion of the semiconductor substrate 1 with the patterned metal layer 5 as a mask. As shown in FIG. The hollow 4 is formed along the outer periphery of the semiconductor substrate 1 (FIG. 3A). Next, a resist 8 is applied on the patterned metal film 5, and this is patterned to form a mask having a wiring pattern constituting the uppermost wiring of the multilayer wiring structure (FIG. 3B). Then, using this as a mask, the metal film 5 is etched to form the uppermost wiring 2g. The wiring 2g shown in this figure represents a pad (FIG. 3C).

  Next, the resist 8 formed on the wiring 2g on the semiconductor substrate 1 is removed (FIG. 4A). Thereafter, a passivation film 6 such as a silicon nitride film is formed on the surface of the semiconductor substrate 1 from which the resist 8 has been removed. The passivation film 6 covers the uppermost wiring 2g and fills the hollow moat 4 as well. In the present invention, the passivation film 6 is not limited to a silicon nitride film, and a silicon oxide film, a laminated film composed of a TEOS film and a silicon nitride film thereon can be used (FIG. 4 ( b)). Next, a photosensitive polyimide is applied on the passivation film 6 to form a polyimide film 9 (FIG. 4C).

Next, the polyimide film 9 is patterned to form a mask for etching the passivation film 6 (FIG. 5A). Using the patterned polyimide film 9 as a mask, the passivation film 9 is etched by anisotropic etching such as RIE to expose the pads constituting the uppermost wiring 2g (FIG. 5B).
Next, although not shown in the drawing, the semiconductor wafer is diced according to a dicing line (see FIG. 6) and separated into chip formation regions. The separated semiconductor chip is then post-processed to form the semiconductor device of this embodiment.

  As described above, in this embodiment, since the metal layer constituting the uppermost wiring of the multilayer wiring structure is used as a hard mask for etching the interlayer insulating film (see FIG. 3B), it is not necessary to use a thick film resist. Occurrence can be suppressed.

Next, Embodiment 2 will be described with reference to FIGS.
In this example, a semiconductor device formed by the method of manufacturing a semiconductor device of Example 1 is described. FIG. 6 is a partial schematic plan view of a semiconductor wafer showing an empty moat formed in the chip formation region, and FIG. 7 is a schematic cross-sectional view showing one chip formation region of the semiconductor wafer of FIG. FIG. 7 schematically shows the wiring 2 having the multilayer wiring structure shown in FIGS. 1 to 5 (excluding the uppermost wiring 2g), and the schematic connection structure of these stacked wiring layers is shown in FIG. Has been.

  As shown in FIG. 6, a semiconductor wafer 10 such as silicon has semiconductor integrated circuits and semiconductor elements formed in a chip formation region 1 partitioned by dicing lines 11. In the semiconductor wafer 10, an empty trench 4 is formed along the peripheral portion of the chip formation region 1, which is formed in an interlayer insulating film and the surface of the semiconductor wafer 10 is exposed at the bottom. The empty moat 4 is provided to prevent film peeling of a low dielectric constant film (Low-k film) used as an interlayer insulating film, and has a width of about 5 μm. Due to the presence of this empty moat, even if stress due to thermal expansion is applied to the interlayer insulating film, it is relaxed and film peeling can be prevented. That is, the film peeling generated from the peripheral edge of the semiconductor substrate stops at the hollow 4 and does not proceed further into the interior.

In order to form a hollow in the interlayer insulating film formed on the semiconductor wafer, a dicing line 11 that partitions the chip formation region 1 is formed on the semiconductor wafer 10. Thereafter, for example, the empty moat 4 is formed along the dicing line 11 in the vicinity of both sides of the line by a laser or the like. When the empty moat 4 is formed in this way, the empty moat 4 is provided along the four sides of each chip forming region 1 as shown in FIG.
In addition, as a low dielectric constant film, carbon atoms are contained in organic films such as silk and flare, CF type Teflon (registered trademark), porous and relatively inorganic films such as inorganic silicon oxide films, and inorganic films. An organic silicon oxide film having an organic component is included. Whereas the relative dielectric constant of the conventional oxide film is about 4, these insulating films have a low relative dielectric constant of 3 or less.

  As shown in FIG. 7, the semiconductor wafer 10 has a multilayer wiring formed on a semiconductor substrate 1 constituting the semiconductor wafer. Interlayer insulating films 3a, 3b, 3c, 3d, 3e, 3f, and 3g are stacked on the semiconductor substrate 1, and a passivation film 6 such as a silicon nitride film is formed thereon. An empty trench 4 is formed in the laminated interlayer insulating films 3a to 3g, and a passivation film 6 formed on the interlayer insulating films 3a to 3g also enters the empty trench 4, and side surfaces of the interlayer insulating films 3a to 3g. Is configured to be shielded from the outside air.

  Wirings 2a, 2c, 2e, and 2g and vias 2b, 2d, and 2f are embedded in each of the interlayer insulating films 3a to 3g. A pad is displayed on the wiring 2g shown in the uppermost layer. The surface of the pad 2g is partially exposed from the passivation film 6 for electrical connection with the outside. The lowermost wiring 2a has a narrow wiring width of about 90 nm. The interlayer insulating film 3a in which this layer is embedded and the interlayer insulating film 3b in which the wiring 2a and the via 2b for electrically connecting the wiring 2c thereon are embedded are made of CF type Teflon (registered) A low dielectric constant film selected from an organic film such as a trademark, a porous and relatively fragile inorganic film such as an inorganic silicon oxide film, and an organic silicon oxide film having an organic component containing carbon atoms in the inorganic film. . The wiring 2c on the wiring 2a has a wiring width of about 130 nm, and the low dielectric constant film has the effect of reducing the wiring resistance and the parasitic resistance for high-speed response to the wiring having a width smaller than the wiring width. It works effectively. For the wiring above the wiring 2c, for example, the wiring 2e, for example, a wiring having a wiring width of 180 nm is used.

  As described above, in this embodiment, since the passivation film is formed after the empty moat is formed, the passivation film is filled in the empty moat formed in the interlayer insulating film, so that the interlayer insulating film is peeled off. It is possible to protect the interface of the low dielectric constant film, which is easy to perform, and to improve the moisture resistance.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a manufacturing process cross-sectional view of a semiconductor device using a low dielectric constant film in a multilayer wiring structure in Example 1 which is an example of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a manufacturing process cross-sectional view of a semiconductor device using a low dielectric constant film in a multilayer wiring structure in Example 1 which is an example of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a manufacturing process cross-sectional view of a semiconductor device using a low dielectric constant film in a multilayer wiring structure in Example 1 which is an example of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a manufacturing process cross-sectional view of a semiconductor device using a low dielectric constant film in a multilayer wiring structure in Example 1 which is an example of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a manufacturing process cross-sectional view of a semiconductor device using a low dielectric constant film in a multilayer wiring structure in Example 1 which is an example of the present invention. The partial schematic plan view of the semiconductor wafer which shows the empty moat formed in the chip | tip formation area which concerns on Example 2 which is one Example of this invention. FIG. 7 is a schematic cross-sectional view showing a one-chip formation region of the semiconductor wafer of FIG. 6.

Explanation of symbols

1 Semiconductor substrate (semiconductor wafer chip formation region)
2, 2a, 2c, 2e, 2g ... wiring 2b, 2d, 2f ... vias 3, 3a to 3g ... interlayer insulating film 4 ... empty moat (grooves for preventing film peeling)
5 ... Metal layer 6 ... Passivation film 7, 8 ... Resist 9 ... Photosensitive polyimide film 10 ... Semiconductor wafer 11 ... Dicing line

Claims (5)

Forming a metal layer that constitutes the uppermost layer of the multilayer wiring that is insulated from each other by an interlayer insulating film on a semiconductor wafer in which a semiconductor element is formed for each chip formation region;
Forming a hard mask for patterning the metal layer and etching the interlayer insulating film;
Etching the interlayer insulating film using the hard mask as a mask to form a groove in which the wafer surface is exposed in a peripheral portion of a chip formation region of the semiconductor wafer;
Patterning the metal layer used as the mask to form a wiring pattern including pads;
Forming a passivation film composed of at least one insulating film on the surface of the semiconductor wafer in which the groove is formed;
Opening the passivation film to expose the pad;
And a step of dicing the semiconductor wafer for each of the chip formation regions to form a plurality of semiconductor chips. The method for manufacturing a semiconductor device according to claim 1, wherein the passivation film is embedded in the groove. The method for manufacturing a semiconductor device according to claim 1, wherein the metal layer is formed by sputtering. 4. The insulating film of the first layer closest to the surface of the semiconductor wafer of the interlayer insulating film is made of an insulating film having a reduced dielectric constant. Semiconductor device manufacturing method. 5. The semiconductor device formed by the method for manufacturing a semiconductor device according to claim 1, wherein the passivation film is also embedded in the groove.

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