CN114551409A - Hybrid bonding structure and method for improving multi-die wafer integration reliability - Google Patents
Hybrid bonding structure and method for improving multi-die wafer integration reliability Download PDFInfo
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- CN114551409A CN114551409A CN202210455316.4A CN202210455316A CN114551409A CN 114551409 A CN114551409 A CN 114551409A CN 202210455316 A CN202210455316 A CN 202210455316A CN 114551409 A CN114551409 A CN 114551409A
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
Abstract
The invention discloses a mixed bonding structure and a method for improving the integration reliability of a multi-core grain wafer, wherein the structure comprises the following steps: photoetching and etching the dielectric layer of the upper surface of the wafer to be bonded, which corresponds to the core particle bonding area, and the dielectric layers of the lower surfaces of the n core particles to be bonded to respectively form a wafer groove and a core particle groove; depositing a TiN barrier layer and a seed crystal layer of copper in the groove, filling the groove with electroplating grown copper, and flattening the surface by CMP to form a wafer copper wall and a core grain copper wall; aligning and attaching the core particles to be bonded forming the copper wall and the wafer to be bonded, and then carrying out mixed bonding to obtain a pre-bonded wafer group; and carrying out annealing heat treatment on the pre-bonded wafer group to realize stable bonding of the wafer and the core particles. The invention can obstruct the interference of electric signals among the integrated core particles and in the core particles, greatly improves the heat dissipation of D2W integration, avoids the local accumulation of heat when the core particles work, and improves the reliability of bonding results.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a hybrid bonding structure and a method for improving the integration reliability of a multi-core wafer.
Background
As the integrated circuit industry has developed, the critical pitch and size of the chip have been continuously reduced, and new integrated packaging methods, such as Wafer to Wafer bonding (W2W) and Die to Wafer bonding (D2W), have been introduced accordingly.
Hybrid bonding is a technique for simultaneously bonding Cu electrodes and dielectric layers on a wafer/chip. Solder micro bumps (Solder μ bump) are omitted, so that hybrid bonding can further narrow the interconnection pitch of bonding to less than 10 μm. High-density integration can thus be achieved with hybrid bonding techniques, which play an irreplaceable role in 3D packaging.
In the bonding of D2W, a plurality of core particles need to be integrated onto a wafer, except for considering the optimization of bonding interface to obtain high-quality bonding, after the high-density core particles are integrated, the extremely short core particle distance can cause the mutual interference of electrical signals between heterogeneous core particles, and a large pressure difference exists between high pressure and low pressure to cause electromigration to the dielectric layer, which has a certain effect on the reliability of the bonding interface, thereby affecting the reliability of the whole bonding system; in addition, the same trouble exists between Cu electrodes with different functions in the core particles.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a hybrid bonding structure and a method for improving the integration reliability of a multi-core grain wafer, which can obstruct the interference of electric signals between integrated core grains and in the core grains, reduce the electromigration of bonding interfaces between the core grains and in the core grains, greatly improve the heat dissipation of the multi-core grain integration, and integrally improve the reliability of a bonding result, and the specific technical scheme is as follows:
a mixed bonding structure for improving the integration reliability of a multi-core grain wafer comprises a semiconductor wafer to be bonded and n core grains to be bonded, wherein the semiconductor wafer to be bonded and the n core grains to be bonded are aligned and attached to be subjected to mixed bonding, and annealing and heat treatment are carried out to form a bonding structure; the upper surface of the semiconductor wafer to be bonded and the lower surfaces of the n core particles to be bonded are respectively provided with a dielectric layer and a graphical Cu electrode; the dielectric layer of the upper surface of the semiconductor wafer to be bonded, which corresponds to the core grain bonding area, is etched with a wafer groove by photoetching, and the dielectric layers of the lower surfaces of the n core grains to be bonded are etched with core grain grooves by photoetching; and the wafer groove and the core grain groove are respectively provided with a wafer copper wall and a core grain copper wall.
Furthermore, the patterned Cu electrodes on the lower surfaces of the n core grains to be bonded correspond to the patterned Cu electrodes on the upper surface of the semiconductor wafer to be bonded in position.
Further, the wafer copper wall and the core grain copper wall are formed by depositing TiN barrier layers in a wafer groove and a core grain groove through a chemical vapor deposition method, forming a seed crystal layer of copper through sputtering, filling the wafer groove and the core grain groove with electroplating grown copper, and finally processing the surfaces of the wafer to be bonded and the core grain to be bonded, which are electroplated with copper, through Chemical Mechanical Polishing (CMP).
Furthermore, the core particle groove is square and surrounds the periphery of the internal Cu electrode of the surface to be bonded, so that the Cu electrode of the core particle is partitioned.
Furthermore, the groove width of the core particle is 1-20 μm, the depth is 5-50 μm, and the distance from the groove to the boundary of the core particle is 5-1000 μm.
Further, the wafer groove corresponds to the shape and size of the core particle groove and the position to be bonded.
Further, the core grain copper wall is connected with the core grain grounding signal, and the wafer copper wall is connected with the wafer grounding signal.
Further, the dielectric layer on the upper surface of the semiconductor wafer 101 to be bonded and the lower surfaces of the n core grains to be bonded may be an insulating material such as silicon dioxide, silicon nitride, or aluminum oxide.
A hybrid bonding method for improving the integration reliability of a multi-die wafer comprises the following steps:
providing a semiconductor wafer to be bonded and n core particles to be bonded, wherein the upper surface of the semiconductor wafer to be bonded and the lower surfaces of the n core particles to be bonded are respectively provided with a dielectric layer and a graphical Cu electrode, and the graphical Cu electrode on the lower surface of the core particle corresponds to the graphical Cu electrode on the upper surface of the wafer in position;
step two, photoetching and etching the dielectric layer corresponding to the core grain bonding area on the upper surface of the semiconductor wafer to be bonded to form a wafer groove, and photoetching and etching the dielectric layers on the lower surfaces of the n core grains to be bonded to form a core grain groove;
depositing TiN barrier layers in the wafer grooves and the core grain grooves, sputtering to form seed crystal layers of copper, electroplating to grow copper to fill the wafer grooves and the core grain grooves, and then processing the surfaces of the wafers to be bonded and the core grains to be bonded which are electroplated with copper by utilizing Chemical Mechanical Polishing (CMP) to respectively form wafer copper walls and core grain copper walls;
aligning and attaching the core particles to be bonded with the copper wall formed in the step three and the wafer to be bonded, and then carrying out mixed bonding to obtain a pre-bonded wafer group;
and fifthly, annealing heat treatment is carried out on the pre-bonded wafer group to realize stable bonding of the wafer and the core particles.
Has the advantages that:
compared with the prior art, the invention has the following advantages: the invention can obstruct the electric signal interference between the integrated core particles and in the core particles, reduce the high pressure difference, the coupling and the like between the core particles and in the core particles, and the extra copper wall greatly improves the heat dissipation of D2W integration, so that the heat can be dispersed below the wafer through the copper wall, the local accumulation of the heat when the core particles work is avoided, and the bonding method and the bonding structure can integrally improve the reliability of the bonding result.
Drawings
FIG. 1 is a schematic cross-sectional view of a wafer to be bonded and a core particle to be bonded according to the present invention;
FIG. 2 is a schematic cross-sectional view of a wafer to be bonded and a core particle to be bonded etching groove according to the present invention;
FIG. 3 is a schematic diagram of the bottom surface of a groove etched by a core particle to be bonded according to the present invention;
FIG. 4 is a three-dimensional schematic view of a bonded core etched groove of the present invention;
FIG. 5 is a schematic diagram of the top surface of a groove etched on a wafer to be bonded according to the present invention;
FIG. 6 is a schematic cross-sectional view of a wafer to be bonded and a copper wall of a core particle to be bonded according to the present invention;
FIG. 7 is a schematic view of the bottom surface of a copper wall of a core particle to be bonded according to the present invention;
FIG. 8 is a three-dimensional schematic view of a copper wall of a core particle to be bonded according to the present invention;
FIG. 9 is a schematic top view of a copper wall of a wafer to be bonded according to the present invention;
FIG. 10 is a cross-sectional view of a bonded wafer and core copper wall of the present invention;
FIG. 11 is a schematic cross-sectional view of a bonded wafer and core grain copper wall without high density integration with the copper wall separating the core grains;
FIG. 12 is a cross-sectional view of a wafer and a core of a bonding structure according to the present invention;
in the figure, a semiconductor wafer 101, core grains 102 to 10n, a wafer groove 201, a core grain groove 202, a wafer copper wall 301, and a core grain copper wall 302.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
The invention discloses a hybrid bonding structure and a method for improving the integration reliability of a multi-core grain wafer, wherein the method comprises the following steps: as shown in fig. 1, in a first step, a semiconductor wafer 101 to be bonded and n core particles 102 to 10n to be bonded are provided, where an upper surface of the semiconductor wafer 101 to be bonded and lower surfaces of the n core particles 102 to 10n to be bonded both have a dielectric layer and a patterned Cu electrode, and in this embodiment, the patterned Cu electrodes on the lower surfaces of the n core particles 102 to 10n to be bonded correspond to the patterned Cu electrodes on the upper surface of the semiconductor wafer 101 to be bonded in position. The dielectric layer is an insulating material comprising silicon dioxide, silicon nitride, aluminum oxide, and the like.
As shown in fig. 2, in the second step, the dielectric layer corresponding to the core grain bonding region on the upper surface of the wafer 101 to be bonded is subjected to photolithography etching to form a wafer groove 201, and the dielectric layers on the lower surfaces of n core grains to be bonded are subjected to photolithography etching to form a core grain groove 202; the core particle groove 202 has a width of 1-20 μm, a depth of 5-50 μm, and a distance of 5-1000 μm from the core particle boundary.
In this embodiment, the dielectric material is SiO2The core particle groove 202 is 5 μm wide and 20 μm deep, 20 μm from the core particle boundary, and partitions the Cu electrode of the core particle 102.
The wafer groove 201 and the core grain groove 202 completely correspond in shape, size and position to be bonded, referring to fig. 3 and 4, a schematic diagram and a three-dimensional schematic diagram of the bottom surface of the etched groove of the core grain 102 to be bonded are shown, and a schematic diagram of the top surface of the etched groove of the wafer 101 to be bonded is shown in fig. 5.
As shown in fig. 6, step three, depositing a TiN barrier layer in the wafer groove 201 and the core grain groove 202 by using a chemical vapor deposition method, forming a seed layer of copper by sputtering, filling the wafer groove 201 and the core grain groove 202 with electroplating-grown copper, and then processing the surfaces of the wafer to be bonded and the core grain to be bonded, which are electroplated with copper, by using chemical mechanical polishing CMP to form a core grain copper wall 302 and a wafer copper wall 301; fig. 7 and 8 show a schematic bottom view and a three-dimensional schematic view of the copper wall of the core grain 102 to be bonded, and fig. 9 shows a schematic top view of the etched groove of the wafer 101 to be bonded.
And step four, aligning and attaching the core particles to be bonded with the copper wall formed in the step three and the wafer to be bonded with the two-dimensional material layer, and applying certain pressure for mixed bonding to obtain a pre-bonded wafer group.
And step five, carrying out annealing heat treatment on the pre-bonded wafer group to realize stable bonding of the wafer and the core particles, as shown in fig. 10.
As shown in fig. 11, without high density integration using copper walls to separate the core grains, breakdown may occur between the core grains and the high and low voltage electrodes between the core grains; the high voltage and the suspended electrode can also form coupling, and the suspended electrode is also coupled with the high voltage, which can cause certain influence on the high-density integration reliability of the hybrid bonded wafer.
As shown in fig. 12, the bonding structure implemented by the bonding method of the present invention includes a semiconductor wafer 101 to be bonded and n core particles 102 to 10n to be bonded, where the semiconductor wafer 101 to be bonded and the n core particles 102 to 10n to be bonded are aligned and bonded, and then mixed and bonded, and then annealed to form a bonding structure; the upper surface of the semiconductor wafer 101 to be bonded and the lower surfaces of the n core particles 102-10 n to be bonded are provided with dielectric layers and patterned Cu electrodes; a wafer groove 201 is formed in the dielectric layer, corresponding to the core grain bonding area, of the upper surface of the semiconductor wafer 101 to be bonded through photoetching, and core grain grooves 202 are formed in the dielectric layers of the lower surfaces of the n core grains to be bonded through photoetching; the wafer groove 201 and the core grain groove 202 are respectively provided with a wafer copper wall 301 and a core grain copper wall 302. The core grain groove 202 is square and surrounds the inner Cu electrode of the bonding surface to divide the Cu electrode of the core grain 102.
The wafer copper wall 301 and the core grain copper wall 302 are formed by depositing TiN barrier layers in the wafer groove 201 and the core grain groove 202 through a chemical vapor deposition method, forming a seed crystal layer of copper through sputtering, filling the wafer groove 201 and the core grain groove 202 with electroplated copper through electroplating growth, and finally processing the surfaces of the wafer to be bonded and the core grain to be bonded, which are electroplated with copper, through Chemical Mechanical Polishing (CMP).
The core grain copper wall 302 is connected with a core grain grounding signal, and the wafer copper wall 301 is connected with a wafer grounding signal; the electric signal crosstalk between core particles and inside the core particles can be effectively avoided, the high pressure difference, the coupling and the like between the core particles and in the core particles are reduced, the extra copper wall greatly improves the heat dissipation of D2W integration, heat can be dispersed below a wafer through the copper wall, the local accumulation of heat during the operation of the core particles is avoided, and the bonding method can integrally improve the reliability of a bonding result.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the foregoing has described the practice of the present invention in detail, it will be apparent to those skilled in the art that modifications may be made to the practice of the invention as described in the foregoing examples, or that certain features may be substituted in the practice of the invention. All changes, equivalents and modifications which come within the spirit and scope of the invention are desired to be protected.
Claims (9)
1. A hybrid bonding structure for improving the integration reliability of a multi-core-grain wafer is characterized by comprising a semiconductor wafer (101) to be bonded and n core grains (102) to (10 n) to be bonded, wherein the semiconductor wafer (101) to be bonded and the n core grains (102) to (10 n) to be bonded are aligned and attached, then hybrid bonding is carried out, and annealing heat treatment is carried out to form the bonding structure; the upper surface of the semiconductor wafer (101) to be bonded and the lower surfaces of the n core particles (102) -10 n to be bonded are respectively provided with a dielectric layer and a graphical Cu electrode; a wafer groove (201) is formed in the dielectric layer, corresponding to the core grain bonding area, of the upper surface of the semiconductor wafer (101) to be bonded through photoetching, and core grain grooves (202) are formed in the dielectric layers, corresponding to the lower surfaces of the n core grains to be bonded, of the lower surfaces of the n core grains to be bonded through photoetching; and a wafer copper wall (301) and a core grain copper wall (302) are respectively arranged in the wafer groove (201) and the core grain groove (202).
2. The hybrid bonding structure for improving the integration reliability of a multi-die wafer as claimed in claim 1, wherein the patterned Cu electrodes of the lower surfaces of the n to-be-bonded core dies (102) -10 n correspond to the patterned Cu electrode positions of the upper surface of the to-be-bonded semiconductor wafer (101).
3. The hybrid bonding structure for improving the integration reliability of a multi-die wafer as claimed in claim 1, wherein the wafer copper wall (301) and the core copper wall (302) are formed by depositing TiN barrier layers in the wafer grooves (201) and the core grooves (202) by chemical vapor deposition, forming a seed layer of copper by sputtering, filling the wafer grooves (201) and the core grooves (202) with copper by electroplating growth, and finally processing the surfaces of the wafer to be bonded and the core to be bonded, which are plated with copper, by chemical mechanical polishing CMP.
4. The hybrid bonding structure for improving the integration reliability of a multi-die wafer as claimed in claim 1, wherein the die recess (202) is formed in a square shape around the Cu electrode inside the die to be bonded, so as to partition the Cu electrode of the die (102).
5. The hybrid bonding structure for improving the integration reliability of a multi-core-grain wafer as claimed in claim 1, wherein the core grain grooves (202) have a width of 1-20 μm, a depth of 5-50 μm, and a distance of 5-1000 μm from the boundary of the core grain.
6. The hybrid bonding structure for improving multi-die wafer integration reliability as claimed in claim 1, wherein the wafer recess (201) and the die recess (202) correspond in shape, size, and location to be bonded.
7. The hybrid bond structure for improving multi-die wafer integration reliability as recited in claim 1, wherein the core die copper wall (302) is connected to a core die ground signal and the wafer copper wall (301) is connected to a wafer ground signal.
8. The hybrid bonding structure for improving the integration reliability of a multi-die wafer as claimed in claim 1, wherein the dielectric layer of the upper surface of the semiconductor wafer (101) to be bonded and the lower surfaces of the n core dies (102) to be bonded to the core dies (10 n) is an insulating material comprising silicon dioxide, silicon nitride, aluminum oxide.
9. A hybrid bonding method for improving the integration reliability of a multi-core grain wafer is characterized by comprising the following steps:
providing a semiconductor wafer (101) to be bonded and n core particles (102) to be bonded to the core particles (10 n), wherein the upper surface of the semiconductor wafer (101) to be bonded and the lower surfaces of the n core particles (102) to be bonded to the core particles (10 n) are provided with dielectric layers and graphical Cu electrodes, and the graphical Cu electrodes on the lower surfaces of the core particles correspond to the graphical Cu electrodes on the upper surface of the wafer in position;
step two, photoetching and etching the dielectric layer corresponding to the core grain bonding area on the upper surface of the semiconductor wafer (101) to be bonded to form a wafer groove (201), photoetching and etching the dielectric layers on the lower surfaces of n core grains to be bonded to form a core grain groove (202);
depositing a TiN barrier layer in the wafer groove (201) and the core grain groove (202), sputtering to form a seed crystal layer of copper, electroplating to grow copper to fill the wafer groove (201) and the core grain groove (202), and then processing the surfaces of the wafer to be bonded and the core grain to be bonded which are electroplated with copper by utilizing Chemical Mechanical Polishing (CMP) to respectively form a wafer copper wall (301) and a core grain copper wall (302);
aligning and attaching the core particles to be bonded with the copper wall formed in the step three and the wafer to be bonded, and then carrying out mixed bonding to obtain a pre-bonded wafer group;
and step five, carrying out annealing heat treatment on the pre-bonded wafer group to realize stable bonding of the wafer and the core particles.
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| CN115172192A (en) * | 2022-09-09 | 2022-10-11 | 之江实验室 | Hybrid bonding method for multi-core-grain wafer level integration |
| CN115799184A (en) * | 2023-02-13 | 2023-03-14 | 江西萨瑞半导体技术有限公司 | Semiconductor packaging method |
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