TWI700752B - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TWI700752B
TWI700752B TW107123352A TW107123352A TWI700752B TW I700752 B TWI700752 B TW I700752B TW 107123352 A TW107123352 A TW 107123352A TW 107123352 A TW107123352 A TW 107123352A TW I700752 B TWI700752 B TW I700752B
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Taiwan
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encapsulating material
package
opening
sealing ring
device die
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TW107123352A
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TW201926487A (zh
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王博漢
余振華
郭宏瑞
胡毓祥
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台灣積體電路製造股份有限公司
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種半導體封裝形成方法，包含將封裝組件包封於包封 材料中，其中包封材料包含直接位於封裝組件上方之部分。包封材料之所述部分經圖案化以形成顯露封裝組件中之導電特徵的開口。重佈線延伸至開口中以接觸導電特徵。電連接件形成於導電特徵上方且電耦接至導電特徵。

Description

半導體封裝及其形成方法
本揭露的實施例是有關於一種半導體封裝及其形成方法。
隨著半導體技術之發展，半導體晶片/晶粒正變得愈來愈小。同時，更多功能需要整合至半導體晶粒中。因此，半導體晶粒需要具有愈來愈多I/O墊裝配於小區域中，且I/O墊之密度隨時間而快速增大。結果，半導體晶粒之封裝變得較困難，其不利地影響封裝的產率。
習知封裝技術可劃分為兩種類別。在第一類別中，在切割晶粒之前封裝晶圓上的晶粒。此封裝技術具有一些有利特徵，諸如較大產出率及較低成本。此外，需要較少底部填充料或模製化合物。然而，此封裝技術亦具有缺點。由於晶粒之大小變得愈來愈小，且各別封裝可僅為扇入型封裝，其中每一晶粒之I/O墊受限於直接位於各別晶粒之表面上之區域，所以在晶粒之有限區域的情況下，I/O墊之數目由於I/O墊的間距之限制而受限。若墊之間距減小，則可出現焊橋。另外，在固定球大小要求下，焊球 必須具有某一大小，所述大小則限制可封裝於晶粒之表面上之焊球的數目。
在封裝之另一類別中，在封裝晶粒之前自晶圓切割晶粒。此封裝技術的有利特徵為形成扇出型封裝的可能性，這意謂可將晶粒上的I/O墊重佈至比晶粒更大的區域，且因此可增加封裝於晶粒之表面上之I/O墊的數目。此封裝技術之另一有利特徵為只封裝「已知良好晶粒」且捨棄有缺陷之晶粒，且因此不在有缺陷之晶粒上浪費成本及精力。
在扇出型封裝中，裝置晶粒包封於模製化合物中，所述模製化合物隨後經平面化以暴露裝置晶粒。介電層形成於裝置晶粒上方。重佈線形成於介電層中以連接至裝置晶粒。當重佈線形成時，密封環可形成於介電層中。扇出型封裝亦可包含穿透模製化合物之穿孔。
本發明的一實施例提供一種形成半導體封裝的方法，包括：將封裝組件包封於包封材料中，其中所述包封材料包括位於所述封裝組件正上方之第一部分；圖案化所述包封材料之所述第一部分以在所述封裝組件中形成顯露導電特徵之開口；形成延伸至所述開口中以接觸所述導電特徵之重佈線；以及形成在所述導電特徵上且電耦接至所述導電特徵之電連接件。
本發明的一實施例提供一種形成半導體封裝的方法，包括：將裝置晶粒附接至基礎層；將所述裝置晶粒包封於包封材料中，其中所述包封材料包括位於所述裝置晶粒正上方之第一部 分，以及包圍所述第一部分之第二部分；圖案化所述包封材料之所述第一部分以形成在所述裝置晶粒中顯露導電特徵之第一開口；圖案化所述包封材料之所述第二部分以形成顯露所述基礎層之第二開口；形成延伸入所述第一開口之重佈線；以及形成延伸入所述第二開口之密封環。
本發明的一實施例提供一種半導體封裝，包括：裝置晶粒；包封材料，包封其中之所述裝置晶粒，其中所述包封材料包括：第一部分，直接位於所述裝置晶粒上方，其中所述第一部分具有第一頂部表面；以及第二部分，包圍所述裝置晶粒，其中所述第二部分具有低於所述第一頂部表面之第二頂部表面；密封環，位於所述包封材料中；以及第一重佈線及第二重佈線，包括位於所述包封材料上方之部分，其中所述第一重佈線及所述第二重佈線分別連接至所述裝置晶粒及所述密封環。
20:載體
22:釋放層
24:介電層
25:晶粒附接膜
26:晶粒附接膜
28:封裝組件
30:導電特徵/金屬柱
32:頂部介電層
36:包封材料
38A:開口/貫通開口
38B、38C:開口
39:金屬晶種層
40:密封環
40A:外底部拐角
40B:內底部拐角
41:經圖案化罩幕
42:重佈線
43:密封環延伸部分
44:介電層
46:開口
48:重佈線
50:介電層
52:重佈線
54:介電層
56:重佈線
58:電連接件/焊料區域
60:積體被動裝置
62:密封環
64:密封環
66:模板
68:穿孔
70:金屬接腳
70A:接腳頭
70B:接腳尾
71:部分
72:開口
100:封裝/複合晶圓
100':單個封裝
300:封裝
302:焊料區域
304:金屬墊
320:封裝組件
322:封裝
324:金屬墊
326:結構/封裝
500:處理流程
502、504、506、508、510、512、514、516、618、520、522:步驟
600:處理流程
602、604、606、608、610、612、614、616、618、620、622、624、626:步驟
D1:凹部深度
D2:深度/厚度
Dia1、Dia2、Dia3:直徑
H1:總高度
S1:間隔
T1、T2、T3、T4:厚度
△H1、△H2:高度差
當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露之態樣。應注意，根據業界中之標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵之尺寸。
圖1至圖9示出根據一些實施例之形成包含穿透模製材料之密封環的封裝之中間階段的橫截面視圖。
圖10至圖21示出根據一些實施例之形成包含穿透模製材料之金屬接腳的封裝之中間階段的透視圖及橫截面視圖。
圖22至圖24示出根據一些實施例之封裝之一些部分的放大 視圖。
圖25及圖26示出根據一些實施例之用於形成封裝的處理流程。
以下揭露內容提供用於實施本發明之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵形成於第二特徵上方或上可包含第一特徵與第二特徵直接接觸地形成之實施例，且亦可包含額外特徵可形成於第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸之實施例。另外，本揭露可在各種實例中重複圖示元件符號及/或字母。此重複是出於簡單性及清晰性之目的，且本身並不指示所論述之各種實施例及/或組態之間的關係。
此外，為便於描述，可在本文中使用諸如「下伏」、「在…之下」、「下部」、「上覆」、「上部」及類似者之空間相對術語以描述如圖式中所說明之一個元件或特徵與其他元件或特徵的關係。除了圖式中所描繪之定向以外，空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用之空間相對描述詞可同樣相應地進行解釋。
根據各種例示性實施例提供封裝及其形成方法。根據一些實施例說明形成封裝之中間階段。論述一些實施例之一些變化。在各種視圖及說明性實施例中，相同圖示元件符號用以指代 相同元件。
圖1至圖9示出根據一些實施例之封裝的形成中之中間階段的橫截面視圖。展示於圖1至圖9中之步驟亦示意性地說明於如圖25中所展示之處理流程500中。
圖1示出載體20及塗佈於載體20上之釋放層22。載體20可為玻璃載體、陶瓷載體或其類似者。載體20可具有圓形俯視形狀，且可具有矽晶圓之大小。舉例而言，載體20可具有8吋直徑、12吋直徑或其類似者。釋放層22可由光-熱轉換(Light-To-Heat-Conversion；LTHC)塗佈形成，其可連同載體20自將在後續步驟中形成的上覆結構中移除。根據本揭露之一些實施例，釋放層22由環氧樹脂類熱釋放材料形成。釋放層22可經由塗佈及固化安置於載體20上。
介電層24(有時稱為用於形成上覆結構之基礎層或緩衝層)形成於釋放層22上方。介電層24之底部表面可與釋放層22之頂部表面相接觸。根據本揭露之一些實施例，介電層24由聚合物形成，所述聚合物可為諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺(polyimide)或其類似者之感光性材料。根據替代實施例，介電層24由非感光性材料或無機介電材料形成，所述非感光性材料或無機介電材料可為諸如氮化矽之氮化物、諸如氧化矽之氧化物、磷矽玻璃(Phospho-Silicate glass；PSG)、硼矽玻璃(Boro-Silicate Glass；BSG)、硼摻雜磷矽玻璃(Boron-Doped Phospho-Silicate Glass；BPSG)或其類似者。
圖1亦說明封裝組件28之置放/附接。其步驟在圖25中所展示之處理流程中之步驟502中說明。封裝組件28經由晶粒附 接膜(Die-Attach Films；DAF)26附接至介電層24，所述晶粒附接膜為黏著膜。封裝組件28中之每一者可包含具有與各別下伏晶粒附接膜26實體接觸之背表面(面向下之表面)的半導體基底(未單獨展示)。封裝組件28可包含半導體基底之前表面(面向上之表面)處的積體電路裝置(諸如包含(例如)電晶體之主動裝置，未展示)。封裝組件28可包含邏輯晶粒，諸如中央處理單元(Central Processing Unit；CPU)晶粒、圖形處理單元(Graphic Processing Unit；GPU)晶粒、行動應用程式晶粒、微控制單元(Micro Control Unit；MCU)晶粒、輸入輸出(input-output；IO)晶粒、基頻(BaseBand；BB)晶粒、應用程式處理器(Application processor；AP)晶粒或其類似者。封裝組件28亦可包含記憶體晶粒，諸如動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)晶粒或靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒。封裝組件28亦可包含系統晶片(System on Chip；SoC)晶粒、記憶體堆疊(諸如高頻寬記憶體(High-Bandwidth Memory；HBM)方塊)、封裝或其類似者。封裝組件28可彼此相同或彼此不同。
儘管兩個封裝組件28說明為實例，但每封裝可存在一個封裝組件28或大於兩個封裝組件。應理解，封裝過程可在晶圓級或晶粒級上執行。當在晶圓級上執行時，存在封裝組件之多個相同群組，其中每一群組經示意性地說明，置放於載體20上，且封裝組件之多個群組經分配為陣列。
根據一些例示性實施例，導電特徵30預形成為封裝組件28之部分，其中導電特徵30電耦接至封裝組件28中之諸如電晶 體(未展示)的積體電路裝置。導電特徵30可為金屬柱(諸如銅柱)、金屬墊、微凸塊或其類似者。儘管為簡單起見而針對封裝組件28中之每一者說明一個導電特徵30，但每一封裝組件28可包含多個導電特徵30。在本說明書中，導電特徵30稱為金屬柱，但其可為其他類型之導電特徵。
根據本揭露之一些實施例，封裝組件28包含填充相鄰金屬柱30之間的間隙的頂部介電層32。頂部介電層32可包含覆蓋金屬柱30之頂部表面之至少一些部分的部分。根據本揭露之一些實施例，頂部介電層32由聚合物形成，所述聚合物可為聚苯并噁唑或聚醯亞胺。根據本揭露之一些實施例，介電層32經蝕刻以形成開口，金屬柱30經由所述開口暴露。根據本揭露之替代實施例，此時未形成用以暴露金屬柱30之開口。相反，在模製材料形成之後時，顯露金屬柱30。
接下來，封裝組件28藉由包封材料36包封，如圖2中所展示。其步驟在圖25中所展示之處理流程中之步驟504中說明。包封材料36填充相鄰封裝組件28之間的間隙。包封材料36可為環氧樹脂(或樹脂)類材料，且可為感光性的。包封材料36可由乾膜形成，所述乾膜預形成為膜且隨後層壓於圖1中所展示之結構上。層壓膜可在例如介於約25度與約150度之間的範圍內之高溫下按壓。乾膜可由環氧樹脂(或樹脂)或其類似者形成，所述環氧樹脂藉由聚乙烯(Polyethylene；PE)或聚對苯二甲酸乙二酯(Polyethylene Terephthalate；PET)保護膜覆蓋於兩側上。根據替代實施例，包封材料36經配製以呈可流動形式，且隨後經固化(例如經由熱固化或紫外(Ultra-Violet；UV)固化)。包封 材料36之頂部表面高於封裝組件28之頂部表面，其中封裝組件28由一薄層的包封材料36覆蓋。此外，諸如模製化合物及底填充料之典型模製材料可包含諸如SiO2、Al2O3或矽石粒子之填充劑粒子(filler particle)。根據本揭露之一些實施例，包封材料36不含填充劑粒子，且整個包封材料36可由均質材料形成。製造不含填充劑粒子之包封材料36允許包封材料36直接位於封裝組件28上方之部分極薄而不犧牲隔離能力。
圖23示意性地說明圖2中所展示之結構之一部分的放大視圖。歸因於封裝組件28之高度，包封材料36之頂部表面可包含位於封裝組件28正上方之第一部分，以及不位於封裝組件28正上方之第二部分。第二部分包圍第一部分。根據本揭露之一些實施例，包封材料36之形成不包含平坦化製程(諸如化學機械拋光(Chemical Mechanical Polish；CMP)製程或機械研磨製程(mechanical grinding process))。相應地，包封材料36之頂部表面的第一部分高於包封材料36之頂部表面的第二部分，其中自第一部分平滑轉變至第二部分。第一部分與第二部分之間的高度差△H1可大於約2微米，且可介於約4微米與約10微米之間的範圍內。根據本揭露之替代實施例，執行平坦化製程，且因此包封材料36之頂部表面為平坦的。包封材料36直接位於封裝組件28上之部分亦可具有介於約10微米與約30微米之間的範圍內之厚度T1。
參考圖3，開口38A及38B形成於包封材料36中。其步驟在圖25中所展示之處理流程中之步驟506中說明。根據本揭露之一些實施例，開口38A穿透包封材料36，以使得介電層24暴 露。開口38B亦穿透包封材料36，以使得金屬柱30暴露。若此時金屬柱30仍由頂部介電層32覆蓋，則頂部介電層32例如在蝕刻步驟(可將經圖案化包封材料36用作蝕刻罩幕來執行)中經圖案化，直至顯露金屬柱30。根據本揭露之一些實施例，包封材料36由感光性材料形成，且包封材料36之圖案化可經由使用包含不透明部分及透明部分之光微影罩幕(未展示)的曝光來達成，且隨後使包封材料36顯影以形成開口38A及38B。儘管在圖3中所展示之橫截面視圖中，開口38A示為為分離的開口，但在圖3中所展示之結構的俯視圖中，所說明之開口38A可為包圍封裝組件28之開口環的部分。另一方面，開口38B為分離的開口，其中每一開口暴露金屬柱30中之一者。
圖4及圖5說明密封環40及重佈線(Redistribution Lines；RDL)42之形成。其步驟在圖25中所展示之處理流程中之步驟512中說明。參考圖4，沈積金屬晶種層39。其步驟經在圖25中所展示之處理流程中之步驟508中說明。根據本揭露之一些實施例，金屬晶種層39包含鈦層及鈦層上方之銅層。根據本揭露之替代實施例，金屬晶種層39包含直接接觸包封材料36之銅層。金屬晶種層39為共形或實質上共形的膜(例如，具有小於約百分之15之厚度變化)。舉例而言，金屬晶種層39之形成可包含物理氣相沈積(Physical Vapor Deposition；PVD)。
經圖案化罩幕41形成於晶種層39上方。其步驟在圖25中所展示之處理流程中之步驟510中說明。根據本揭露之一些實施例，經圖案化罩幕41之形成包含配製及圖案化光阻劑。接下來，可執行電鍍製程，且電鍍諸如銅或銅合金之金屬材料。在電鍍製 程之後，移除經圖案化罩幕41，且執行快閃蝕刻(flash etch)以移除先前直接位於經圖案化罩幕41下之晶種層39部分。圖5中展示所得結構。
經電鍍金屬材料之剩餘部分及晶種層39之剩餘部分是稱為重佈線42與密封環40之組合。重佈線42在包封材料36上方。密封環40穿透包封材料36，且可自高於封裝組件28之頂部表面的第一層級延長至低於或齊平於封裝組件28之底部表面的第二層級。此外，密封環延伸部分43形成於包封材料36上方。
圖24說明圖5中所展示之結構之一部分的放大視圖。密封環40(處於如圖3中之開口38A中)包含開口38A之底部處之底部部分，且所述底部部分具有厚度T2。重佈線42包含位於包封材料36上方且具有厚度T3之水平部分。經沈積金屬材料為共形的，且因此厚度T2接近於厚度T3。舉例而言，厚度T2可在厚度T3的約百分之85與百分之95之間。此外，密封環40包含外底部拐角40A及內底部拐角40B。外底部拐角可為不具有顯著圓度之鋒利拐角，而內拐角40B可為圓形的，例如具有大於厚度T2之約百分之50的半徑R1，且比率R1/T2可介於約0.5與約1.5之間的範圍內。
返回參考圖5，重佈線42包含位於包封材料36上方且經由部分延長至開口38B中(圖3)之金屬軌跡(trace metal)部分，以使得重佈線42電連接至導電特徵30。儘管未說明，但歸因於重佈線42之共形特徵，重佈線42直接位於開口38B上方之部分可具有凹部。
參考圖6，形成介電層44。其步驟在圖25中所展示之處 理流程中之步驟514中說明。根據本揭露之一些實施例，介電層44由諸如聚苯并噁唑、聚醯亞胺或類似者之聚合物形成。根據替代實施例，介電層44由諸如氮化矽、氧化矽或其類似者之無機材料形成。開口46隨後例如經由光微影製程形成。密封環延伸部分43及重佈線42暴露於開口46。
圖24亦說明介電層44之一部分之放大視圖。歸因於如圖5中所展示之開口38A，介電層44(圖24)之頂部表面具有位於密封環40正上方之凹部。凹部位於在密封環40之相對側壁部分之間延伸的介電層44之一部分的正上方，所述側壁部分位於各別開口38A之相對側壁上。凹部深度D1可大於厚度T3之約百分之30，且可介於厚度T3之約百分之30與約百分之50之間的範圍內。
參考圖7，更多特徵形成於介電層44上方，所述特徵包含介電層50及介電層54以及重佈線48、重佈線52及重佈線56。其步驟在圖25中所展示之處理流程中之步驟516中說明。根據本揭露之一些實施例，重佈線48之形成包含沈積金屬晶種層(未展示)，在金屬晶種層上方形成且圖案化光阻劑(未展示)，以及在金屬晶種層上方電鍍諸如銅或鋁之金屬材料。金屬晶種層及經電鍍材料可由相同材料或不同材料形成。隨後移除經圖案化光阻劑，接著對晶種層先前由經圖案化光阻劑覆蓋之部分進行蝕刻。重佈線52及重佈線56之材料及形成過程可類似於重佈線48之材料及形成過程。介電層50及介電層54之材料及形成過程可類似於介電層44之材料及形成過程。因此，不在本文中重複細節。
積體被動裝置(Integrated Passive Device；IPD)60可黏合至重佈線56，且電連接件58根據一些例示性實施例來形成。其步驟在圖25中所展示之處理流程中之步驟518中說明。根據本揭露之一些實施例，未形成凸塊下金屬(Under-Bump Metallurgies；UBM)，且電連接件58直接形成於重佈線56上。此可在對應封裝為低成本封裝時達成，且因此省略一些特徵(諸如UBM及穿透包封材料36之通孔)以降低製造成本。根據本揭露之替代實施例，UBM(未展示)形成於重佈線56與電連接件58之間。
電連接件58之形成可包含將焊球置放於重佈線56之經暴露部分上，且隨後回焊所述焊球。根據本揭露之替代實施例，電連接件58之形成包含執行電鍍製程以在重佈線56上方形成焊料層，且隨後回焊所述焊料層。電連接件58亦可包含金屬柱，或金屬柱及金屬柱上之焊蓋，所述金屬柱亦可經由電鍍形成。在本說明書中，包含介電層24之結構以及上覆結構組合稱為封裝100，其可為包含多個封裝組件28之複合晶圓(且在下文中亦稱為複合晶圓100)。
接下來，自載體20去黏合封裝100，例如藉由將紫外光或雷射光束投射至釋放層22上，以使得釋放層22在紫外光或雷射光束之熱量下分解。其步驟在圖25中所展示之處理流程中之步驟520中說明。所得封裝100展示於圖8中。根據本揭露之一些實施例，在所得封裝100中，介電層24保持為封裝100之底部部分，且保護密封環40。接下來，單體化(晶粒鋸)製程經執行以將複合晶圓100分離為單個封裝100'(圖9)。其步驟亦在圖25 中所展示之處理流程中之步驟520中說明。
圖9亦示出封裝組件320與封裝100'之黏合，由此形成封裝322。其步驟在圖25中所展示之處理流程中之步驟522中說明。經由焊料區域58執行黏合，這使重佈線56與封裝組件320中之金屬墊324相接合。根據本揭露之一些實施例，封裝組件320包含封裝基底、內插件、印刷電路板或其類似者。
在封裝322中，重佈線48、重佈線52以及重佈線56之一些部分在介電層44、介電層50以及介電層54中形成密封環62，其中重佈線48、重佈線52以及重佈線56之對應部分中之每一者形成鄰近封裝100'之周邊的完整環。密封環62連接至密封環延伸部分43(其亦形成完整環)及密封環40以形成密封環64。因此，密封環64自作為封裝100'中之頂部介電層的介電層54之頂部表面一直延伸至包封材料36之底部表面。相應地，封裝組件28亦受保護以免被可穿透包封材料36從而劣化封裝組件28之有害物質(如水分及化學品)影響。
在封裝322中，包封材料36包含處於與封裝組件28相同層級之第一部分，以及高於封裝組件28之第二部分。第一部分及第二部分分別為連續性材料之部分，其之間不具有可辨別介面之積體材料。此外，因為第一部分及第二部分形成於相同製程中，且在第一部分與第二部分之形成之間未執行平坦化，所以包封材料36之頂部表面中不存在研磨標記。
圖10至圖21說明根據本揭露之一些實施例在封裝的形成中之中間階段的透視圖及橫截面視圖。除無密封環形成於包封材料中外，這些實施例類似於圖1至圖9中所展示之實施例。相 反，金屬接腳置放於包封材料中。除非另外規定，否則在這些實施例中之組件的材料及形成方法實質上與相同組件相同，所述組件由與圖1至圖9中所展示之實施例中之相同圖示元件符號表示。關於圖10至圖21中所展示之組件的形成過程及材料之細節可因此在對圖1至圖9中所展示之實施例的論述中發現。展示於圖10至圖21中之步驟亦示意性地說明於如圖26中所展示之處理流程600中。
參考圖10，提供模板66。模板66可由諸如金屬(不鏽鋼、銅、鋁或其類似者)之剛性材料形成。穿孔68形成於模板66中。模板66可附接至真空頭(未展示)，所述真空頭經組態以在由箭頭所展示之方向上排出空氣。金屬接腳70包含接腳頭70A及接腳尾70B。應理解，接腳頭70A、接腳尾70B以及穿孔68可具有圓形或包含(且不限於)方形、六邊形或其類似者之其他形狀。接腳頭70A具有大於穿孔68之直徑的直徑(或橫向尺寸)，且接腳尾70B具有小於穿孔68之直徑的直徑(或橫向尺寸)。相應地，當接腳尾70B插入至穿孔68中時，接腳頭70A被卡住。參考圖11B，根據本揭露之一些實施例，接腳頭70A之直徑Dia1介於約200微米與約250微米之間的範圍內，接腳尾70B之直徑Dia2介於約150微米與約200微米之間的範圍內，且穿孔68之直徑Dia3介於約180微米與約230微米之間的範圍內。金屬接腳70之總高度H1可介於約200微米與約250微米之間的範圍內。
參考圖11A，金屬接腳70插入至穿孔68中。其步驟在圖26中所展示之處理流程中之步驟602中說明。插入可例如經由挑選及置放來達成。根據替代實施例，金屬接腳70藉由將金屬接 腳70傾入模板66上方以及使模板66振動來插入，以使得尾70B落入穿孔68中。在接腳尾70B插入至穿孔68中之後，提供真空抽吸，從而使得金屬接腳70藉由真空固定於模板66上。圖11B說明圖11A中之部分71的橫截面視圖。
參考圖12，將模板66連同固定於其上之金屬接腳70一起翻轉倒置。金屬接腳70隨後移動至晶粒附接膜25。真空使得金屬接腳70保持於模板66上。根據本揭露之一些實施例，如圖12中所展示，晶粒附接膜25黏附至介電層24，所述介電層進一步形成於釋放層22上。將釋放層22塗佈於載體20上。載體20、釋放層22、介電層24以及晶粒附接膜25可具有圓形俯視圖形狀，多個相同封裝可形成於所述形狀上。
金屬接腳70壓靠於且黏附至晶粒附接膜25。其步驟在圖26中所展示之處理流程中之步驟604中說明。接下來，釋放真空，且移開模板66。在後續步驟中，封裝組件28黏附至晶粒附接膜25，如圖13A中所展示。其步驟在圖26中所展示之處理流程中之步驟606中說明。圖13A說明單個封裝組件28，儘管實際上，多個封裝組件28及多個金屬接腳70可置放於晶粒附接膜25上以形成多個相同群組，其中所述群組中之每一者包含一或多個封裝組件28及多個金屬接腳70。根據本揭露之一些實施例，金屬接腳70及封裝組件28具有相似高度，例如具有金屬接腳70之高度的約百分之20的高度差。圖13B說明圖13A中所展示之結構的橫截面視圖。
接下來，參考圖14A，包封材料36經配製以覆蓋封裝組件28及金屬接腳70。其步驟在圖26中所展示之處理流程中之步 驟608中說明。配製包封材料36之材料及方法可類似於參考圖2所論述的材料及方法，且因此並不在本文中重複。圖14B說明圖14A中所展示之結構的透視圖。
圖15A及圖15B分別說明在暴露導電特徵30及金屬接腳70之開口38B及開口38C的形成中之橫截面視圖及透視圖。其步驟在圖26中所展示之處理流程中之步驟610中說明。包封材料36可由感光性材料形成，且因此開口38B及開口38C可經由曝光(使用光微影罩幕)及顯影過程形成。
圖22說明圖15A及圖15B中所展示之結構之一部分的放大視圖。歸因於金屬接腳70之高度，包封材料36之頂部表面包含位於金屬接腳70正上方之第一部分，以及包圍金屬接腳70之第二部分。根據本揭露之一些實施例，包封材料36之形成不包含平坦化製程(諸如化學機械拋光製程或機械研磨製程)。相應地，包封材料36之第一部分的頂部表面高於包封材料36之第二部分的頂部表面，其中自第一部分之頂部表面平滑轉變至第二部分之頂部表面。第一部分與第二部分之頂部表面之間的高度差△H2大於約2微米，且可介於約4微米與約5微米之間的範圍內。根據本揭露之替代實施例，執行平坦化製程，且因此包封材料之頂部表面為平坦的。包封材料36位於金屬接腳70正上方之第一部分亦可具有介於約10微米與約30微米之間的範圍內之厚度T4。相鄰金屬接腳70之間的間隔S1可介於約100微米與約150微米之間的範圍內。根據一些例示性實施例，包封材料36之深度/厚度D2可介於約160微米與約250微米之間的範圍內。
圖16說明金屬晶種層39之形成，所述金屬晶種層可包 含銅層或鈦層及鈦層上方之銅層。其步驟在圖26中所展示之處理流程中之步驟612中說明。可由光阻劑形成之經圖案化罩幕41隨後形成於金屬晶種層39上方。其步驟在圖26中所展示之處理流程中之步驟614中說明。可參考圖4之論述得到用於形成經圖案化罩幕41之材料及形成過程。接下來，如圖17中所示，執行電鍍製程經以電鍍金屬材料，接著使用移除經圖案化罩幕41之移除製程，以及使用移除正下伏於經移除圖案化罩幕41之金屬晶種層39之部分的蝕刻工藝。因此，形成重佈線42及密封環延伸部分43。其步驟在圖26中所展示之處理流程中之步驟616中說明。重佈線42包含連接至一些金屬接腳70的第一部分以及連接至金屬柱30之第二部分。密封環部分43形成包圍位於封裝組件28正上方之區域的環。根據本揭露之一些實施例，出於電接地目的，金屬接腳70中之一或多者連接至密封環部分43。
圖18及圖19示出介電層44、介電層50及介電層54以及重佈線48、重佈線52及重佈線56之形成。其步驟在圖26中所展示之處理流程中之步驟618及步驟620中說明。參考圖6及圖7在實施例中論述形成過程及各別材料，且不在本文中重複細節。密封環62經形成以包圍重佈線48、重佈線52以及重佈線56，且密封環62包含延伸部分43，所述延伸部分電連接至金屬接腳70中之一者以用於在最終封裝中電接地。積體被動裝置60可黏合至重佈線56。相應步驟在圖26中所展示之處理流程中之步驟622中說明。電連接件58形成於重佈線56上。包含介電層24及上覆結構之複合晶圓100因此形成。
在後續步驟中，複合晶圓100例如藉由經由雷射光束或 紫外光分解釋放層22而自載體20去黏合。相應步驟在圖26中所展示之處理流程中之步驟624中說明。所得複合晶圓100隨後單體化為多個封裝100'，且圖20說明所得封裝100'中之一者。相應步驟亦在圖26中所展示之處理流程中之步驟624中說明。金屬接腳70隨後藉由移除介電層24及晶粒附接膜25之一些部分(例如經由鐳射鑽孔)而顯露，因此形成開口72。藉由使接腳頭70A大於接腳尾70B，鐳射鑽孔之製程裕量增大。
圖21說明封裝300與封裝100'之黏合。相應步驟在圖26中所展示之處理流程中之步驟626中說明。經由焊料區域302執行黏合，所述焊料區域使金屬接腳70與封裝300中之金屬墊304相接合。根據本揭露之一些實施例，封裝300包含封裝基底(未單獨展示)及裝置晶粒(未單獨展示)，所述裝置晶粒可為諸如SRAM晶粒、DRAM晶粒或其類似者之記憶體晶粒。
圖21亦說明封裝組件320與封裝100'之黏合，因此形成疊層封裝(Package-on-Package；PoP)結構/封裝326。經由焊料區域58執行黏合，這使重佈線56與封裝組件320中之金屬墊324相接合。根據揭露之一些實施例，封裝組件320包含封裝基底、內插件、印刷電路板或其類似者。
根據本揭露之一些實施例，如圖9中所展示之密封環64及如圖21中所展示之金屬接腳70整合於同一封裝100'中。各個封裝之相應形成過程類似於在圖10至圖21中所展示之過程(除在圖15A及圖15B中所展示之步驟中之外)，其中當圖15A及圖15B中之開口38B及開口38C形成時，用於形成密封環40之貫通開口38A(類似於圖3中所展示之開口)同時形成。
在上文所說明之例示性實施例中，根據本揭露之一些實施例論述一些例示性過程及特徵。亦可包含其他特徵及過程。舉例而言，可包含測試結構以幫助對3D封裝或3DIC裝置之驗證測試。測試結構可包含例如形成於重佈線層中或基底上之測試墊以允許測試3D封裝或3DIC、使用探針及/或探針卡及類似操作。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露之結構及方法可結合中間驗證已知良好晶粒的測試方法一起使用，以提高產率及降低成本。
本揭露之實施例具有一些有利特徵。藉由配製包封材料以覆蓋裝置晶粒及/或金屬接腳，包封材料充當包封材料及覆蓋裝置晶粒之介電層。由於另外兩個形成過程合併為一個過程，因此製造成本降低。此外，省略在其他製程上會在模製材料上執行之平坦化製程，從而使得製造成本進一步降低。密封環可經形成以延伸至包封材料中，從而使得對裝置晶粒與有害物質之隔離改進。金屬接腳可用於替換經由電鍍形成之通孔，此亦降低製造成本。
根據本揭露之一些實施例，形成半導體封裝的方法包含將封裝組件包封於包封材料中，其中包封材料包含位於封裝組件正上方之部分。包封材料之所述部分經圖案化以形成顯露封裝組件中之導電特徵的開口。重佈線延伸至開口中以接觸導電特徵。電連接件形成於導電特徵上方且電耦接至導電特徵。所述方法更包含：圖案化包封材料之第二部分以形成穿透包封材料之貫通開口，其中所述貫通開口延伸至至少與封裝組件之底部表面共面之層級；以及填充貫通開口以在包封材料中形成密封環。在一實施 例中，密封環包括包封材料之相對側壁上之相對部分，且方法更包括配製介電層，其中介電層之一部分在密封環之相對部分之間延伸。在一實施例中，密封環為包圍封裝組件之完整環。在一實施例中，方法進一步包含包封材料上方之額外密封環，其中密封環與額外密封環經互連以形成整合式密封環。在一實施例中，方法更包含將多個金屬接腳包封於包封材料中，其中包封材料包括位於金屬接腳正上方之第二部分，且其中當包封材料之第一部分經圖案化時，包封材料之第二部分同時經圖案化以形成顯露多個金屬接腳之凹部。在一實施例中，方法更包含：預形成多個金屬接腳；將已形成之多個金屬接腳附接至黏著膜上；以及將封裝組件附接至黏著膜。在一實施例中，不在包封材料上執行平坦化，且在重佈線形成時，包封材料之第一部分具有第一頂部表面，且包圍封裝組件之包封材料的第二部分具有低於第一頂部表面之第二頂部表面。在一實施例中，包封材料中不含填充劑粒子。
根據本揭露之一些實施例，形成半導體封裝的方法包含：將裝置晶粒附接至基礎層；將裝置晶粒包封於包封材料中，其中所述包封材料包括位於裝置晶粒正上方之第一部分以及包圍第一部分之第二部分；圖案化包封材料之第一部分以形成顯露裝置晶粒中之導電特徵的第一開口；圖案化包封材料之第二部分以形成顯露基礎層之第二開口；形成延伸入第一開口中之重佈線；以及形成延伸入第二開口中之密封環。在一實施例中，包封材料之第一部分及第二部分同時經圖案化。在一實施例中，包封材料由感光性材料形成，且圖案化包封材料之第一部分及圖案化包封材料之第二部分包括曝光及顯影。在一實施例中，密封環自高於 裝置晶粒之頂部表面的第一層級延伸至低於裝置晶粒之底部表面的第二層級。在一實施例中，密封環完全地包圍裝置晶粒。在一實施例中，在密封環之橫截面視圖中，密封環具有U形狀，且方法更包括在包封材料上方形成介電層，其中介電層延伸入U形狀。
根據本揭露之一些實施例，半導體封裝包含裝置晶粒；包封材料，將裝置晶粒包封於其中，其中所述包封材料包括：第一部分，直接位於裝置晶粒上方，其中第一部分具有第一頂部表面；以及第二部分，包圍裝置晶粒，其中第二部分具有低於第一頂部表面之第二頂部表面；密封環，位於包封材料中；以及第一重佈線及第二重佈線，包括位於包封材料上方之部分，其中所述第一重佈線及第二重佈線分別連接至裝置晶粒及密封環。在一實施例中，密封環穿透包封材料，且自高於裝置晶粒之頂部表面的第一層級延伸至低於裝置晶粒之底部表面的第二層級。在一實施例中，密封環包括接觸包封材料之相對部分，且封裝更包括在密封環之相對部分之間延伸的介電材料。在一實施例中，第一表面連續且平滑地連接至第二表面。在一實施例中，在封裝之俯視圖中，密封環為無斷裂之完整環。
前文概述若干實施例之特徵，以使得所屬領域中具通常知識者可較佳地理解本發明之態樣。所屬領域中具通常知識者應理解，所屬領域中具通常知識者可易於使用本發明作為設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優點之其他過程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本發明之精神及範疇，且所屬領域中具通常知識者可在不脫離本發明之精神及範疇的情況下在本文中 進行各種改變、替代以及更改。
24:介電層
25:晶粒附接膜
28:封裝組件
36:包封材料
42:重佈線
44:介電層
48:重佈線
50:介電層
52:重佈線
54:介電層
56:重佈線
58:電連接件/焊料區域
60:積體被動裝置
62:密封環
70:金屬接腳
70A:接腳頭
70B:接腳尾
72:開口
100':單個封裝

Claims (10)

  1. 一種形成半導體封裝的方法，包括：將封裝組件包封於包封材料中，其中所述包封材料的整體在相同製程中形成，且所述包封材料包括位於所述封裝組件正上方之第一部分，以及包圍所述第一部分之第二部分，其中所述第一部分的第一頂部表面高於所述第二部分的第二頂部表面；圖案化所述包封材料之所述第一部分以在所述封裝組件中形成顯露導電特徵之開口；形成延伸至所述開口中以接觸所述導電特徵之重佈線；以及形成在所述導電特徵上且電耦接至所述導電特徵之電連接件。
  2. 如申請專利範圍第1項所述之方法，更包括：圖案化所述包封材料之所述第二部分以形成穿透所述包封材料之貫通開口，其中所述貫通開口延伸至至少與所述封裝組件之底部表面共面之層級；以及填充所述貫通開口以於所述包封材料中形成密封環。
  3. 如申請專利範圍第1項所述之方法，更包括：將多個金屬接腳包封於所述包封材料中，其中所述包封材料包括位於所述金屬接腳正上方之第三部分，且其中當所述包封材料之所述第一部分經圖案化時，所述包封材料之所述第三部分同時經圖案化以形成顯露所述多個金屬接腳之凹部。
  4. 一種形成半導體封裝的方法，包括：將裝置晶粒附接至基礎層；將所述裝置晶粒包封於包封材料中，其中所述包封材料的整 體在相同製程中形成，且所述包封材料包括位於所述裝置晶粒正上方之第一部分，以及包圍所述第一部分之第二部分，其中所述第一部分的第一頂部表面高於所述第二部分的第二頂部表面；圖案化所述包封材料之所述第一部分以形成在所述裝置晶粒中顯露導電特徵之第一開口；圖案化所述包封材料之所述第二部分以形成顯露所述基礎層之第二開口；形成延伸入所述第一開口之重佈線；以及形成延伸入所述第二開口之密封環。
  5. 如申請專利範圍第4項所述之方法，其中所述包封材料之所述第一部分及所述第二部分同時經圖案化。
  6. 如申請專利範圍第4項所述之方法，其中所述包封材料由感光性材料形成，且圖案化所述包封材料之所述第一部分及圖案化所述包封材料之所述第二部分包括光暴露及顯影。
  7. 如申請專利範圍第4項所述之方法，其中所述密封環耦接至電接地。
  8. 一種半導體封裝，包括：裝置晶粒；包封材料，包封其中之所述裝置晶粒，其中所述包封材料包括：第一部分，直接位於所述裝置晶粒上方，其中所述第一部分具有第一頂部表面；以及第二部分，包圍所述裝置晶粒，其中所述第二部分具有低於所述第一頂部表面之第二頂部表面； 密封環，位於所述包封材料中；以及第一重佈線及第二重佈線，包括位於所述包封材料上方之部分，其中所述第一重佈線及所述第二重佈線分別連接至所述裝置晶粒及所述密封環。
  9. 如申請專利範圍第8項所述之封裝，其中所述密封環穿過所述包封材料，且自高於所述裝置晶粒之頂部表面的第一層級延伸至低於所述裝置晶粒之底部表面的第二層級。
  10. 如申請專利範圍第8項所述之封裝，其中在所述封裝之俯視圖中，所述密封環為無斷裂之完整環。
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