TWI696252B - 封裝體及其製造方法 - Google Patents
封裝體及其製造方法 Download PDFInfo
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- TWI696252B TWI696252B TW107115812A TW107115812A TWI696252B TW I696252 B TWI696252 B TW I696252B TW 107115812 A TW107115812 A TW 107115812A TW 107115812 A TW107115812 A TW 107115812A TW I696252 B TWI696252 B TW I696252B
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Abstract
一種方法包括:將犧牲區點膠到載體上,並在載體上形
成金屬柱。金屬柱與犧牲區的至少一部分重疊。所述方法更包括將金屬柱和犧牲區包封在包封材料中,從載體上卸下金屬柱、犧牲區以及包封材料,並移除犧牲區的至少一部分以形成凹陷,所述凹陷從包封材料的表面水平延伸至包封材料中。
Description
本發明實施例提供一種封裝體及其製造方法。
隨著半導體技術的發展,半導體晶片/晶粒的尺寸越來越小,同時,更多的功能需要整合到半導體晶粒中,因此,半導體晶粒需要越來越多的輸入/輸出(I/O)接墊被封裝到更小的區域中,且I/O接墊的密度與日俱增,因此,半導體晶粒的封裝體變得更加困難,這對封裝體的良率有不利影響。
傳統的封裝技術大致可以分為兩類。在第一類中,晶圓上的晶粒在被切割前進行封裝。這種封裝體技術具有產量大與成本低的優點。此外,需要較少的底部填充劑或模製化合物。然而,這種封裝體技術也存在缺點。由於晶粒的尺寸越來越小,各封裝體只能採用扇入式封裝體,其中每個晶粒的I/O接墊限定在相應晶粒表面的正上方區域。隨著晶粒的有限區域,I/O接墊的數量也受限於I/O接墊的間距的限制。如果要縮小接墊的間距,可能會出現銲料橋接(solder bridges)。另外,在固定銲球尺寸的要求下,
銲球必須具有一定的尺寸,這又限制了可以封裝在晶粒表面上的銲球的數量。
在另一類封裝中,晶粒在封裝之前從晶圓上切割下來。這種封裝技術的優點是可以形成扇出式封裝體,這意味著晶粒上的I/O接墊可以重新分佈到比所述晶粒更大的區域,因此可以增加封裝在晶粒表面上的I/O接墊的數量。該封裝技術的另一個優點是封裝「已知良好晶粒」,且丟棄有缺陷的晶粒,因此不會浪費成本和精力在有缺陷的晶粒上。
本發明實施例提供一種封裝體,包括:第一晶片、多個金屬柱、包封材料、重分佈結構、多個連接墊以及第二晶片。所述金屬柱環繞所述第一晶片,其中所述多個金屬柱包括第一下凹式金屬柱。所述包封材料環繞所述第一晶片與所述多個金屬柱,其中所述第一下凹式金屬柱的頂面包括第一部分,其低於所述包封材料的頂面水平。所述重分佈結構位於所述第一晶片與所述多個金屬柱的下方且電性連接至所述第一晶片與所述多個金屬柱。所述多個連接墊位於所述重分佈結構的下方且電性連接至所述重分佈結構。所述第二晶片電性連接至所述第一下凹式金屬柱。
本發明實施例提供一種封裝體的製造方法,其步驟如下所示。在載體上形成犧牲區;在所述載體上形成金屬柱,其中所述金屬柱與至少一部分的所述犧牲區重疊;將所述金屬柱與所述
犧牲區包封在包封材料中;從所述載體上卸下所述金屬柱、所述犧牲區以及所述包封材料;以及移除所述至少一部分的所述犧牲區以形成凹陷,所述凹陷自所述包封材料的表面水平延伸至所述包封材料中。
本發明實施例提供一種封裝體,包括:包封材料、金屬柱、銲料區以及元件晶粒。所述金屬柱位於所述包封材料中。所述銲料區包括第一部分,其從所述包封材料的頂面延伸至所述金屬柱中,其中所述金屬柱環繞所述銲料區的所述第一部分。所述元件晶粒位於所述包封材料中。
20:載體
22:離型膜
23:緩衝層
24:犧牲點
26:點膠機
28:固化單元
30:金屬晶種層
30A:鈦層
30B:銅層
32:圖案化的罩幕
34:開口
36:金屬柱
38:元件晶粒
39:晶粒貼附膜(DAF)
41:半導體基底
42:金屬柱
43:部分的頂介電層
44:頂介電層
48:包封材料
50:介電層
52:開口
54:重分佈線
54A:導通孔
54B:金屬跡線
58、62、66:介電層
60、64:重分佈線
68:凸塊下金屬(UBMs)
70:電連接件
74:膠帶
76:框架
78:頂面水平
79:凹陷
80:銲料區
81:鈦層
86:封裝構件
88:接合墊
100:複合晶圓
100’、200、300:封裝體
202:元件晶粒
204:封裝基底
206:金屬墊
208:底部填充劑
400:製造流程
402、404、406、408、410、412、414、416、418、420、422、424:步驟
D1:深度
H1、H2、H3:高度
W1、W2:寬度
結合附圖閱讀以下詳細說明,會最佳地理解本發明的各態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1、圖2A和圖3至圖18繪示出根據一些實施例形成封裝體的中間階段的剖面圖。
圖2B繪示出根據一些實施例點膠聚合物點的透視圖。
圖19繪示出根據一些實施例的穿孔中的凹陷的上視圖。
圖20至圖26繪示出根據一些實施例的封裝體中一些凹陷的橫剖面圖。
圖27A和圖27B分別繪示出根據一些實施例的封裝體中的細
長凹陷的上視圖和剖面圖。
圖28A和圖28B分別繪示出根據一些實施例的細長光阻的剖面圖和上視圖。
圖29和圖30分別繪示出根據一些實施例的穿孔中的聚合物點和凹陷的細節。
圖31繪示出根據一些實施例形成封裝體的製造流程圖。
以下揭露內容提供用於實施所提供的目標的不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然,這些僅僅為實例而非用以限制。舉例來說,在以下描述中,在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例,且也可包括第一特徵與第二特徵之間可形成有額外特徵,使得第一特徵與第二特徵可不直接接觸的實施例。此外,本揭露在各種實例中可重複使用元件符號及/或字母。元件符號的重複使用是為了簡單及清楚起見,且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
此外,為易於說明,本文中可能使用例如「在...下方(underlying)」、「在...下面(below)」、「下部的(lower)」、「在...上方(overlying)」、「上部的(upper)」等空間相對術語來闡述圖中所示的一個元件或特徵與另一(些)元件或特徵的關係。所述
空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向(旋轉90度或在其他定向),而本文所用的空間相對術語相應地作出解釋。
根據各種示例性實施例,提供了一種整合扇出型(Integrated Fan-Out,InFO)封裝體及其形成方法。根據一些實施例說明了形成InFO封裝體的中間階段。討論一些實施例中的一些變形。在各種視圖和說明實施例中,類似的元件符號用以表示類似的構件。
圖1、圖2A和圖3至圖18繪示出根據一些實施例形成封裝體的中間階段的剖面圖。圖1至圖18繪示出的製程也在圖31中的製造流程400中示意性地示出。
參照圖1,提供載體20,並將離型膜22塗佈在載體20上。相應的步驟如圖31中製造流程中的步驟402所示。載體20可以是玻璃載體、陶瓷載體、有機載體或其類似載體。離型膜22與載體20的頂面物理接觸。離型膜22可由光熱轉換(LTHC)塗佈材料來形成。離型膜22可藉由塗佈法被施加到載體上。根據本揭露的一些實施例,LTHC塗佈材料能夠在光/輻射(例如雷射)的熱下分解,因此可以將載體20自形成於其上的結構釋放。根據本揭露的一些實施例,LTHC塗佈材料22包括碳黑(碳顆粒)、溶劑、矽填充物以及/或環氧樹脂。環氧樹脂可以包括聚醯亞胺或其他聚合物,例如丙烯酸樹脂。LTHC塗佈材料22可以可流動形式來塗覆,接著,在例如紫外(UV)光下被固化。
根據一些實施例,如圖1所示,在LTHC塗佈材料22上形成聚合物緩衝層23。根據一些實施例,聚合物緩衝層23包括聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)或其他適用的聚合物。根據另一實施例,未形成聚合物緩衝層23。因此,使用虛線來繪示聚合物緩衝層23以表示聚合物緩衝層23可能會形成或可能不會形成。
圖2A至圖7繪示出金屬柱36的形成。在整篇說明書中,金屬柱36可替代地稱為穿孔(through-via)36,因為金屬柱36可貫穿後續經點膠所形成的包封材料。
參照圖2A,形成犧牲區/材料/點24。根據本揭露的一些實施例,犧牲點24包括聚合物,其可由丙烯酸、環氧樹脂、PBO、聚醯亞胺或其類似材料所形成。犧牲點24也可包括模製化合物、液體或凝膠類型的晶粒貼合膜、底部填充劑、模製底部填充劑或其類似材料。犧牲點24在下文中可替代地稱為聚合物點,但也可以使用除了聚合物以外的其他材料。相應的步驟如圖31的製造流程中的步驟404所示。
根據本揭露的一些實施例,聚合物點24是通過點膠、模板印刷或其類似方法來形成。當點膠或印刷時,聚合物點24可以稍微流動並具有高黏性。因此,在點膠或印刷之後,聚合物點的頂部和側壁形狀變得平滑和彎曲。圖29繪示出聚合物點24的放大視圖。根據本揭露的一些實施例,聚合物點24的寬度W1在約100μm與約170μm之間的範圍內,而聚合物點24的高度H1可
以在約5μm與約100μm之間的範圍內。
根據本揭露的一些實施例,聚合物點24由點膠機26(圖2A)來進行點膠,然後用固化單元28來進行固化。固化單元28通過紫外光(UV)固化、熱固化或類似方法來固化聚合物點24。通過持續地進行(on-going)固化聚合物點24,而不是在載體20上的所有聚合物點24已經被點膠之後才同時固化所有聚合物點,聚合物點24在點膠與固化之間存在均勻的時間間隔。所述均勻時間間隔使得聚合物點24具有實質上均勻的寬度和實質上均勻高度,因此聚合物點24的形狀是均勻的。否則,較長的間隔可能導致聚合物點24塌陷得更多,導致更大的寬度W1和更小的高度H1。
圖2B繪示出聚合物點24的點膠的透視圖。根據本揭露的一些實施例,點膠機26和固化單元28被控制為具有均勻的間距,且固化單元28跟隨點膠機26移動。因此,在點膠聚合物點24之後的固定時間間隔之後,固化單元28移動到經點膠的聚合物點24的頂部以固化之。聚合物點24被點膠到將要形成金屬柱的位置。
根據本揭露的另一實施例,聚合物點24包括光阻,其形成製程包括點膠光阻、使用微影罩幕對光阻進行曝光,並顯影光阻。光阻的所留下的部分為聚合物點24。所得到的聚合物點24可具有實質上筆直且垂直的邊緣,如圖28A所示。
犧牲點可以形成為條狀而不是分散的點狀。因此可形成聚合物條。圖28B繪示出示例性的聚合物條24的上視圖。根據一
些實施例,聚合物條24形成為細長條(strips)或細長塊(blocks)。如圖28B所示,聚合物條24亦可以是環形。可以理解,如圖28B所示的聚合物條24的圖案可以在載體20上重複(圖2A)以形成陣列,每個陣列用於形成如圖18所示的一個封裝體。
參照圖3,通過物理氣相沉積(PVD)或其類似方法形成金屬晶種層30。相應的步驟如圖31中的製造流程中的步驟406所示。根據本揭露的一些實施例,金屬晶種層30位於聚合物緩衝層23和聚合物點24上,並與聚合物緩衝層23和聚合物點24接觸。根據本揭露的另一實施例,聚合物緩衝層23未形成在LTHC塗佈材料22與金屬晶種層30之間,因此金屬晶種層30與LTHC塗佈材料22是物理接觸。根據本揭露的一些實施例,金屬晶種層30包括鈦層30A(如放大區域所示)和鈦層30A上的銅層30B。根據本揭露的另一實施例,金屬晶種層30包括銅層,其接觸LTHC塗佈22。金屬晶種層30實質上為共形膜,因此聚合物點24上的金屬晶種層30的部分的輪廓是順沿著聚合物點24的輪廓。
圖4、圖5、圖6A、圖6B以及圖6C繪示出金屬柱36的形成。相應的步驟如圖31中的製造流程中的步驟408所示。參照圖4,形成圖案化的罩幕32。圖案化的罩幕32可包括光阻,在下文中稱為光阻32。圖案化的光阻32的形成包括分配毯覆式的光阻,並使用微影罩幕(未示出)對光阻32進行曝光。在後續顯影後,開口34形成在光阻32中。金屬晶種層30的一些部分外露於開口34。根據本揭露的一些實施例,開口34寬於聚合物點24,
且開口34的寬度W2大於聚合物點24的寬度W1。根據本揭露的另一實施例,開口34窄於聚合物點24。
接著,如圖5A所示,藉由在開口34中鍍覆金屬材料來形成金屬柱36。因為金屬柱36將穿過最終封裝體中後續形成的封裝材料(其可以是模製化合物),所以金屬柱36可替代地稱為穿孔或貫穿模製穿孔(through-molding vias)。經鍍覆的金屬材料可以是銅或銅合金。金屬柱36的頂面低於光阻32的頂面,使得金屬柱36的形狀被開口34所限制。金屬柱36可具有實質上垂直的和筆直的邊緣。另外,金屬柱36在剖面視圖中可具有沙漏形狀(sand-timer shape),其中金屬柱36的中間部分窄於相應的頂部部分和底部部分。
在圖5A中,金屬柱36的寬度W2大於聚合物點24的寬度,因此金屬柱36延伸超過聚合物點24的邊緣。圖5B繪示出根據一些實施例的結構,其中聚合物點24的寬度W1大於金屬柱36的寬度W2,因此聚合物點24延伸超過相應的金屬柱36的邊緣。
在後續的步驟中,光阻32被移除,因此暴露出下方的金屬晶種層30的部分。然後在蝕刻步驟中(例如,在非等向性蝕刻或等向性蝕刻步驟中)移除金屬晶種層30的暴露部分。因此,剩餘的晶種層30的邊緣與金屬柱36的相應的上覆部分齊平。所得到的示例性金屬柱36示於圖6A。在全文中,金屬晶種層30的剩餘部分可被認為是金屬柱36的一部分或不屬於金屬柱36的一部分。金屬柱36的上視形狀包括但不限於圓形、橢圓形、矩形、六
邊形、八邊形和類似形狀。在形成金屬柱36之後,可暴露出LTHC塗佈材料22或緩衝層23。
圖6B和6C繪示出一些實施例,其中聚合物點24寬於相應的上覆的穿孔36。在圖6B中,當蝕刻金屬晶種層30時,延伸超出穿孔36邊緣的聚合物點24的部分不會被蝕刻,並且剩餘的聚合物點24仍然寬於相應的上覆的穿孔36。在圖6C中,當蝕刻金屬晶種層30時,延伸超出穿孔36的邊緣的聚合物點24的部分也被蝕刻,因此聚合物點24的邊緣與相應的上覆的穿孔36的邊緣齊平。
圖7繪示出封裝構件38的置放/貼合。相應的步驟如圖31中的製造流程中的步驟410所示。封裝構件38可以是元件晶粒,因此在下文中為了簡化而稱為元件晶粒38,而封裝構件38的另一種形式也可以是封裝體、記憶體堆疊或其類似結構。元件晶粒38藉由晶粒貼附膜(Die-Attach Film,DAF)39貼合至LTHC塗佈材料22或緩衝層23上。所述DAF 39是一種附著膜,其在元件晶粒38被置放在LTHC塗佈材料22之前預先貼合在元件晶粒38上。因此,在貼合至LTHC塗佈材料22之前,DAF 39和元件晶粒38組合為一個整合件。元件晶粒38可包括半導體基底41,其具有與DAF39物理接觸的背面(表面朝下)。元件晶粒38可在半導體基底41的正面(表面向上)處具有積體電路元件(例如主動元件,其例如包括電晶體,未示出)。根據本揭露的一些實施例,元件晶粒38是一種邏輯晶粒,它可以是中央處理器(CPU)晶粒、
圖形處理單元(GPU)晶粒,行動應用(mobile application)晶粒、微控制單元(Micro Control Unit,MCU)晶粒、輸入-輸出(input-output,IO)晶粒、基頻(BaseBand,BB)晶粒或應用處理器(Application processor,AP)晶粒。
根據一些示例性實施例,金屬柱42(例如銅柱)是預先形成為元件晶粒38的一部分,並且金屬柱42電性耦合至積體電路元件,例如是元件晶粒38上的電晶體(未示出)。根據本揭露的一些實施例,介電材料(如聚合物)填充鄰近的金屬柱42之間的間隙,以形成頂介電層44。頂介電層44還可以包括一部分(以虛線43表示),其覆蓋並保護金屬柱42。根據本揭露的一些實施例,聚合物層44可以由PBO或聚醯亞胺所形成。
接著,將元件晶粒38和金屬柱36包封在包封材料48中,如圖8所示。相應的步驟如圖31中的製造流程中的步驟412所示。包封材料48填充鄰近的穿孔36之間的間隙以及穿孔36與元件晶粒38之間的間隙。包封材料48可包括模製化合物、模製底部填充劑、環氧樹脂以及/或樹脂。包封材料48的頂面高於金屬柱42的頂端。當由模製化合物形成時,包封材料48可以包括基材,其可以是聚合物、樹脂、環氧樹脂或其類似材料以及在所述基材中的填充劑顆粒。填充劑顆粒可以是SiO2、Al2O3、二氧化矽(silica)或其類似材料的介電顆粒,且所述填充劑顆粒可以是球形。而且,球形填充劑顆粒可具有多個不同的直徑。
在後續的步驟中,如圖9所示,進行平坦化製程(例如
化學機械研磨(CMP)製程或機械研磨製程),以薄化包封材料48和介電層44,直到穿孔36和金屬柱42暴露出來。相應的步驟亦如圖31中的製造流程中的步驟412所示。由於所述平坦化製程,穿孔36的頂端與金屬柱42的頂面實質上齊平(共平面),且穿孔36的頂端與包封材料48的頂面實質上共平面。
圖10至圖14說明了重分佈線(RDLs)的形成,其亦可稱為重分佈結構。相應的步驟如圖31中的製造流程中的步驟414。圖10和圖11繪示出重分佈的第一層和相應的介電層的形成。參照圖10,形成介電層50。根據本揭露的一些實施例,介電層50由聚合物(例如PBO,聚醯亞胺或其類似材料)所形成。所述形成方法包括塗佈可流動形式的介電層50,然後固化介電層50。根據本揭露的另一實施例,介電層50由無機介電材料(例如氮化矽、氧化矽或其類似材料)所形成。所述形成方法可包括化學氣相沉積(CVD)、原子層沉積(ALD)、電漿增強化學氣相沉積(PECVD)或其他適用的沉積方法。然後,藉由例如微影製程來形成開口52。根據一些實施例,介電層50是由如PBO或聚醯亞胺之類的光敏材料所形成,開口52的形成是有關於使用微影罩幕(未示出)的曝光以及顯影步驟。穿孔36和金屬柱42外露於開口52。
接著,參照圖11,在介電層50上形成重分佈線54。重分佈線54包括導通孔54A與金屬跡線(金屬線)54B。導通孔54A形成在介電層50中,以連接到金屬柱42和穿孔36。金屬跡線(金
屬線)54B形成在介電層50上。根據本揭露的一些實施例,重分佈線54(包括54A和54B)在鍍覆製程中形成,其包括沉積金屬晶種層(未示出),形成圖案化的光阻(未示出)覆蓋在所述金屬晶種層上,並且在所述金屬晶種層上鍍覆諸如銅以及/或鋁的金屬材料。所述金屬晶種層和鍍覆金屬材料可以由相同的材料或不同的材料所形成。然後移除圖案化的光阻,接著蝕刻先前被所述圖案化的光阻所覆蓋的金屬晶種層的部分。雖然沒有示出,但從開口52生長的重分佈線54的部分的頂面可以是凹陷的,且低於直接覆蓋介電層50上的重分佈線54的部分。
參照圖12,根據本揭露的一些實施例,介電層58形成在圖11所示的結構之上,接著在介電層58中形成開口(由重分佈線60所填充)。因此重分佈線54的一些部分外露於所述開口。介電層58可使用選自形成介電層50的相同候選材料的材料來形成,其可包括PBO、聚醯亞胺、BCB或其他有機或無機材料。然後形成重分佈線60。重分佈線60還包括導通孔部分與金屬線部分。所述導通孔部分延伸到介電層58的開口中,以接觸重分佈線54。所述金屬線部分直接位於介電層58上方。重分佈線60的形成可與重分佈線54的形成相同,其包括形成晶種層,形成圖案化的罩幕,鍍覆重分佈線60,然後移除所述圖案化的罩幕與所述晶種層中不期望的部分。
圖13繪示出介電層58和重分佈線60上的介電層62和重分佈線64的形成。介電層62可以是選自形成介電層50、60的
同一組候選材料的材料來形成。重分佈線64也可以由金屬或金屬合金(包括鋁、銅、鎢或其合金)來形成。可以理解的是,雖然在所示的示例性實施例中,形成了三層重分佈線(54、60以及64),但所述封裝體可以具有任何數量的RDL層,例如一層、兩層或超過三層。
圖14繪示出根據一些示例性實施例的介電層66、凸塊下金屬(UBMs)68以及電連接件70的形成。介電層66可以是選自由形成介電層50、58以及62的同一組候選材料的材料來形成。舉例來說,介電層66可使用PBO、聚醯亞胺或BCB來形成。在說明性示例性實施例中,開口形成在介電層66中,以暴露下方的金屬墊(或稱為連接墊),所述金屬墊為重分佈線64的一部分。根據本揭露的一些實施例,UBMs 68形成並延伸到介電層66中的開口中,以接觸重分佈線64中的金屬墊。UBMs 68可以由鎳、銅、鈦或其多層所形成。根據一些示例性實施例,UBMs 68包括鈦層以及鈦層上的銅層。
然後,形成電連接件70。相應的步驟如圖31中的製造流程中的步驟416所示。電連接件70的形成可包括將銲球置放在UBMs 68的暴露部分上,接著回銲所述銲球,因此電連接件70便形成了銲料區。根據本揭露的另一實施例,電連接件70的形成包括進行鍍覆步驟,以在UBMS 68上形成銲料層,然後回銲所述銲料層。電連接件70還可以包括非銲料金屬柱,或者是金屬柱以及所述非銲料金屬柱上的銲料帽,其亦可藉由鍍覆來形成。在整個
說明書中,所述結構(包括聚合物緩衝層23與上覆結構的組合)被稱為封裝體100,其是包括多個元件晶粒38的複合晶圓(以下也稱為複合晶圓100)。
接著,參照圖15,將複合晶圓100置放在貼合至框架76的膠帶74上。根據本揭露的一些實施例,電連接件70與膠帶74接觸。舉例來說,藉由將輻射線(例如雷射光束)投射到LTHC塗佈材料22上且輻射線穿透過透明載體20的方式使得複合晶圓100與載體20分離(圖14)。相應的步驟如圖31中的製造流程中的步驟418所示。因此,LTHC塗佈材料22因由輻射線所導入的熱量而分解。因此載體20可以從經分解的LTHC塗佈材料22上剝離出來,且複合晶圓100因此從載體20分離(拆卸)出來。然後藉由電漿清洗步驟移除LTHC塗佈材料22的殘留物。所得到的複合晶圓100,如圖15所示。
根據本揭露的實施例,形成聚合物緩衝層23,如圖14所示,聚合物緩衝層23外露於複合晶圓100的頂部處。聚合物緩衝層23被蝕刻,以得到如圖15所示的結構。根據本揭露的另一實施例,未形成聚合物緩衝層23。如圖15所示,穿孔36、聚合物點24、包封材料48以及DAF 39被暴露出來。經暴露的聚合物點24從穿孔36的頂面向下延伸。
接著,移除聚合物點24,形成延伸到穿孔36中的凹陷79,所述穿孔36亦可稱為下凹式金屬柱。所得到的結構如圖16所示。相應的步驟如圖31中的製造流程中的步驟420所示。根據
本揭露的一些實施例,使用雷射鑽孔以及/或蝕刻來移除聚合物點24。舉例來說,可進行雷射鑽孔,以移除聚合物點24,後續進行電漿清潔或濕式清潔。所述雷射鑽孔可使用低能量來進行,以便移除聚合物點24,而穿孔36的金屬部分不被損壞。另外,移除聚合物點24和金屬晶種層30中鈦層的下方的部分,而穿孔36的銅部分不被損壞。電漿清潔用於清潔殘留物,並且可以使用由含有CF4、O2或CF4和O2混合物的製程氣體所產生的電漿來進行。濕式清潔可以使用異丙醇(IPA)、四甲基氫氧化銨(TMAH)、HF或其類似物來進行。
根據本揭露的一些實施例,藉由蝕刻(包括乾式蝕刻或濕式蝕刻)來移除聚合物點24。被移除的聚合物點24留下的空間形成了凹陷79。蝕刻化學品(蝕刻氣體或蝕刻溶液)取決於聚合物點24的材料。在蝕刻聚合物點24之後,蝕刻晶種層30中的鈦層30A(圖3)。由於鈦的電阻率高於銅的電阻率,所以藉由移除鈦層,以使穿孔36的銅部分(其電阻率低於鈦層)暴露出來。因此,接至穿孔36的連接可具有較低的電阻。根據本揭露的一些實施例,藉由使用氫氟酸(HF)溶液、磷酸或HF和磷酸的混合物的濕式蝕刻來進行鈦層30A的蝕刻。所述蝕刻也可以使用乾式蝕刻來進行。
凹陷79的深度D1可以實質上等於聚合物點24的高度H1(圖29),並且可在約5μm至約50μm之間的範圍內。D1/H2的比值可在約0.03以及0.3之間的範圍內,其中H2是穿孔36的
高度。凹陷79的寬度W1可在約120μm與約170μm之間的範圍內。
在聚合物點24的蝕刻或清潔過程中,包封材料48和DAF 39也可能被蝕刻和凹蝕。蝕刻速率取決於包封材料48和DAF 39的材料以及蝕刻化學品的類型。因此,DAF 39可能被部分蝕刻(並因此凹陷)或完全移除。包封材料48也可能被凹蝕,因此包封材料48的頂面可以是凹陷的並低於穿孔36的頂面。圖16示意性地繪示出虛線78,其代表了經凹陷的包封材料48的可能的頂面水平。包封材料48的經凹陷的頂面也可以是任何水平面,其高於所示虛線78。因此,在經凹陷的包封材料48的例子中,穿孔36的高度H2可能高於包封材料48的高度H3。
在圖16中,虛線81被繪示為鈦層與穿孔36的下方的含銅部分之間的界面。虛線81表示為鈦層可能存在,也可能不存在。
同樣如圖16所示,複合晶圓100包括多個彼此相同的封裝體100’,每個封裝體100’包括多個穿孔36和一個(或多個)元件晶體粒38。
圖17繪示出將多個封裝體200(圖示為單一個封裝體200)接合到封裝體100’上,進而形成了多個相同的堆疊式封裝(PoP)結構/封裝體300。相應的步驟如圖31中的製造流程中的步驟422所示。所述接合藉由銲料區80來進行,所述銲料區80將穿孔36連接到上覆的封裝體200中的金屬墊206。銲料區80延伸到凹陷79中,且可以(或可以不)接觸穿孔36的頂面,其
中所述頂面圍繞凹陷79(圖16)。根據本揭露的一些實施例,封裝體200包括封裝基底204和元件晶粒202,所述元件晶粒202可以是記憶體晶粒,如靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒或其類似晶粒。底部填充劑208也設置在封裝體200和下方的封裝體100’之間的間隙中,並加以固化。
接著,亦如圖17所示,進行單體化(晶粒切割)製程,以將複合晶圓100和上覆的封裝體200分離成彼此相同的個別的封裝體300。相應的步驟如圖31中的製造流程中的步驟424所示。所述單體化可在膠帶74上進行。所述單體化可使用刀具來進行,或是可以使用雷射來進行預切割,從而形成凹槽,然後使用刀具切穿相應的凹槽。
圖18繪示出藉由銲料區70將經單體化的封裝體300接合至封裝構件86。根據本揭露的一些實施例,封裝構件86是一個封裝基底,其可以無核心的基底或具有核心的基底。根據本揭露的其他實施例,封裝構件86是印刷電路板或封裝體。銲料區70可以接合至封裝構件86中的接合墊88。
圖19至圖26繪示出根據本揭露的一些實施例的穿孔36以及穿孔36中的相應的凹陷79或包封材料48。為了簡潔起見,填入凹陷79中的銲料區80(圖18)並未示出,而所述銲料區是存在的。圖19繪示出穿孔36和凹陷79的上視圖。穿孔36的一些頂部部分形成了環形凹陷79。凹陷79和穿孔36的俯視圖形狀
包括但不限於圓形、正方形、橢圓形、六邊形、八邊形或其類似形狀。圖19所示的上視圖可以從圖20至圖22所示的結構中獲得。凹陷79的寬度W1可以小於穿孔36的寬度W2。寬度W1和W2可以是直徑,其中凹陷79和穿孔36具有圓形上視形狀。
圖20繪示出根據本揭露的一些實施例的穿孔36。凹陷79延伸到穿孔36中,並具有圓形的底面和側壁,此為圓形的聚合物點24的結果(圖7和圖29)。鈦層30A位於穿孔36的頂部(亦稱為第一部分),且包圍凹陷79(亦稱為第二部分)。鈦層30A是原始的晶種層30的剩餘部分(圖3)。由於延伸到凹陷79中的鈦層30A的部分已在聚合物移除製程中被移除,並且可藉由雷射鑽孔移除,因此沒有鈦層延伸到凹陷79中。
圖21繪示出根據本揭露的一些實施例的穿孔36。凹陷79延伸到穿孔36中,並具有圓形的底面和側壁,此為圓形的聚合物點24的結果(圖7和圖29)。穿孔36的頂部沒有鈦層。舉例來說,在移除聚合物的過程中或之後,金屬晶種層中的鈦層(圖3)可藉由蝕刻移除。
圖22繪示出根據本揭露的一些實施例的穿孔36。凹陷79延伸到穿孔36中,並具有實質上筆直的與垂直的側壁。此外,凹陷79的底面可以是實質上平面。根據這些實施例,凹陷79可藉由使用圖案化的光阻所形成的聚合物點來形成。沒有鈦層留在穿孔36的頂部。舉例來說,在移除聚合物的過程中或之後,金屬晶種層中的鈦層可藉由蝕刻移除。
圖23至圖26繪示出根據本揭露的一些實施例的穿孔36和凹陷79,其中聚合物點寬於相應的穿孔36。舉例來說,形成製程可如圖5B所示。另外,根據本揭露的一些實施例,包封材料48的頂面高於穿孔36的頂面/表面,因此,凹陷79由包封材料48所定義並外露於包封材料48。
圖23繪示出根據本揭露的一些實施例的穿孔36和凹陷79。根據這些實施例,穿孔36的頂面不存在鈦層。穿孔36的頂面是圓形的,並且可以(或不可以)連續地連接到包封材料48的周圍部分的頂面。圖23所示的結構可由圖6B所示的製程來形成。
圖24繪示出根據本揭露的一些實施例的穿孔36和凹陷79。根據這些實施例,沒有鈦層位於穿孔36的頂面。穿孔36的頂面為實質上平面,可以(也可以不)連續連接到包封材料48的周圍部分的實質上平面的頂面。根據這些實施例,凹陷79也可以藉由使用圖案化的光阻作為犧牲點來形成。圖24所示的結構可使用如圖6B所示的製程來形成(除了聚合物點24將具有垂直的側壁和平面的頂面)。
圖25繪示出根據本揭露的一些實施例的穿孔36和凹陷79。根據這些實施例,聚合物點24具有剩餘部分殘留在最終結構中(如圖18所示)並延伸超過穿孔36的邊緣。剩餘的聚合物點24將與銲料區80(圖18)接觸。圖25中所示的結構可使用圖6B中所示的製程來形成。在圖25中,鈦層30A具有與聚合物點24重疊的部分,所述部分更進一步地與穿孔36重疊。鈦層30A的其
它部分已經在圖6B所示的製程或圖16所示的製程中被移除。
圖26繪示出根據本揭露的一些實施例的穿孔36和凹陷79。根據這些實施例,聚合物點24的剩餘部分殘留在最終結構中(如圖18所示),並且剩餘的聚合物點24的邊緣與穿孔36的邊緣齊平。剩餘的聚合物點24將與銲料區80(圖18)接觸。圖26中所示的結構可使用圖6C中所示的製程來形成。在圖26中,鈦層30A具有一些部分與聚合物點24重疊,所述部分更進一步地與穿孔36重疊。鈦層30A的其它部分已經在圖6C所示的製程或圖16所示的製程中被移除。
圖27A和圖27B繪示出根據一些實施例的封裝體的上視圖和剖面圖。參照圖27A,其顯示了封裝體100’的上視圖,包封材料48具有形成為細長條狀的凹陷79。穿孔36外露於細長的凹陷條79。根據一些實施例,細長的凹陷條79相互連接,以形成凹陷環,圖27A繪示了兩個凹陷環為例。
圖27B繪示出圖27A所示的結構的剖面圖,其中剖面圖是從圖27A中包括線27B-27B的平面所獲得。如圖27B所示,凹陷79在多個穿孔36上延伸。這可視為是為每個穿孔36所形成的凹陷79是相互連接的,沒有包封材料48將凹陷分開。還繪示出用於將穿孔36連接到封裝構件200的銲料區80。
圖27A和圖27B中用於形成凹陷條或凹陷環79的製程可包括形成光阻條或光阻環作為犧牲/聚合物點。舉例來說,用於形成包括凹陷環的封裝體的示例性製程基本上可與圖1至圖18中所
示和描述相同,除了圖2A和圖2B所示的聚合物點24被如圖28A和圖28B所示的光阻24所取代。圖28A繪示出的光阻24的截面圖具有實質上筆直的和垂直的邊緣,以及實質上平面的頂面。圖28B繪示出用以形成環的光阻24的上視圖。光阻24的材料不同於圖5A中的光阻32的材料,因此在蝕刻金屬晶種層(圖6B)的步驟中,光阻24未被蝕刻。如圖27A和圖27B所示,光阻24的環最終將產生凹陷79。
圖29詳細繪示出示例性聚合物點24的剖面圖。由於流動性和高黏性,聚合物點24的頂部部分是彎曲和圓形的。聚合物點的頂面具有圓形的部分24A。表面部分24B比頂部部分24A具有更大的斜率。部分24C的斜率降至低於部分24B的斜率。圖30繪示出由於具有如圖29所示的形狀的聚合物點24而形成的所得的凹陷79。因此,如圖29所示,凹陷79的底面具有聚合物24的頂面形狀的倒置形狀(inverted shape)。
在上述示例性實施例中,根據本揭露的一些實施例討論了一些示例性製程和特徵。其他特徵和製程也可包括在內。舉例來說,可以包括測試結構來輔助三維(3D)封裝體或三維積體電路(3DIC)元件的驗證測試。測試結構可包括例如形成於重佈線層中或基底上的測試墊,所述測試墊使得能夠測試3D封裝體或3DIC、使用探針(probe)及/或探針卡(probe card)等。可對中間結構及最終結構執行驗證測試。另外,本文中所公開的結構及方法可接合包括對已知良好晶粒(known good dies)的中間驗證
的測試方法一起使用,以提高良率(yield)及降低成本。
本揭露的實施例具有一些有利的特徵。在如晶片上系統(System-on-Chip,SOC)封裝的一些應用中,所述SOC(對應於圖18中的元件晶粒38)由於SOC晶粒中所產生的顯著熱量而具有散熱問題。為了良好的散熱,元件晶粒最好具有厚的矽基底,使得更多熱能從矽基底的側壁散發。但是,這意味著整個封裝體厚度增加了,有時高達40%。根據本揭露的一些實施例,在穿孔中形成凹陷,使得銲料區的一些部分位於凹陷中。如此一來,即使為了獲得更好的散熱特性而增加元件晶粒的厚度,也不會改變封裝體的總厚度。
根據本發明的一些實施例,一種封裝體包括第一晶片;多個金屬柱環繞所述第一晶片,其中所述多個金屬柱包括第一下凹式金屬柱;包封材料環繞所述第一晶片和所述多個金屬柱,其中所述第一下凹式金屬柱的頂面包括低於所述包封材料的頂面水平的第一部分;重分佈結構,位於所述第一晶片與所述多個金屬柱的下方且電性連接至所述第一晶片與所述多個金屬柱;多個連接墊,位於所述重分佈結構的下方且電性連接至所述重分佈結構;以及第二晶片電性連接至所述第一下凹式金屬柱。根據一些實施例,所述第一下凹式金屬柱的頂面更包括環繞所述第一部分的第二部分,且所述第二部分高於所述第一部分。根據一些實施例,所述第一下凹式金屬柱的所述頂面的所述第一部分在所述金屬柱的剖面圖中是彎曲的。根據一些實施例,所述第一下凹式金
屬柱包括含銅部分;以及所述含銅部分上的含鈦層,其中所述第一下凹式金屬柱的所述頂面的所述第一部分包括所述含銅部分的頂面,而所述第一下凹式金屬柱的所述頂面的所述第二部分包括所述含鈦層的頂面。根據一些實施例,所述封裝體更包括銲料區,其與所述第一下凹式金屬柱的所述第一部分接觸,其中所述銲料區將所述第二晶片接合至所述第一晶片。根據一些實施例,所述第一下凹式金屬柱的所述頂面更包括環繞所述第一部分的第二部分,且所述封裝體更包括聚合物,其位於所述第二部分上且與所述第二部分接觸。根據一些實施例,所述多個金屬柱更包括第二下凹式金屬柱,部分的所述包封材料的位於所述第一下凹式金屬柱與所述第二下凹式金屬柱之間,且所述部分的所述包封材料的頂面低於所述包封材料的所述頂面水平。
根據本發明的一些實施例,一種方法,包括:在載體上點膠犧牲區,且在所述載體上形成金屬柱。所述金屬柱與至少一部分的所述犧牲區重疊。所述方法更包括將所述金屬柱與所述犧牲區包封在包封材料中,從所述載體上卸下所述金屬柱、所述犧牲區以及所述包封材料,以及移除所述犧牲區的至少一部分以形成凹陷,所述凹陷自所述包封材料的表面水平延伸至所述包封材料中。在一實施例中,所述形成所述金屬柱包括:沉積毯覆式的金屬晶種層,其在所述犧牲區的側壁與頂面上延伸;在所述毯覆式的金屬晶種層上形成圖案化的光阻;以及在所述圖案化的光阻中的開口中鍍覆所述金屬柱。在一實施例中,所述毯覆式的金屬
晶種層包括鈦層與所述鈦層上的銅層,且在移除所述犧牲區以形成所述凹陷之後,所述凹陷中的部分的所述鈦層被移除。在一實施例中,所述金屬柱與整個所述犧牲區重疊,所述金屬柱延伸超出所述犧牲區的邊緣,且所述凹陷延伸進入部分的所述的金屬柱並被所述部分的所述金屬柱環繞。在一實施例中,所述金屬柱與所述犧牲區的第一部分重疊,且所述犧牲區更包括第二部分,所述第二部分延伸超出所述金屬柱的邊緣,而所述包封材料的側壁暴露出所述凹陷。在一實施例中,所述點膠所述犧牲區包括:點膠聚合物點;以及固化所述聚合物點。在一實施例中,整個所述犧牲區被移除。在一實施例中,所述犧牲區的第一部分被移除,而所述犧牲區的第二部分保持不被移除。
根據本發明的一些實施例,一種方法包括點膠聚合物點;在所述聚合物點上沉積金屬晶種層;在所述金屬晶種層上形成圖案化的罩幕,其中所述圖案化的罩幕中的開口與整個所述聚合物點重疊;在所述開口中形成金屬柱;移除所述圖案化的罩幕以及被所述圖案化的罩幕所覆蓋的部分所述金屬晶種層;將元件晶粒置放在與所述金屬柱相同的水平上;將元件晶粒和金屬柱包封在包封材料中;移除所述聚合物點的至少一部分以形成延伸到所述金屬柱中的凹陷,其中所述金屬柱包括環繞所述凹陷的環部;並形成延伸到凹陷中的焊料區。在一實施例中,所述移除聚合物點包括雷射鑽孔。在一實施例中,所述移除聚合物點包括蝕刻製程。在一實施例中,所述方法更包括移除所述金屬晶種層中
的第一鈦部分,其中所述第一鈦部分位於所述聚合物點的曲面上。在一實施例中,在所述第一鈦部分被移除之後,所述金屬晶種層中的第二鈦部分仍保留著,且所述第二鈦部分包括所述金屬柱的平面上的平坦部。在一實施例中,在形成所述凹陷之後,所述聚合物點包括一部分,其被所述金屬柱的一部分所環繞並在同一水平上。在一實施例中,所述凹陷具有圓形的底面。
根據本發明的一些實施例,一種封裝體,包括:包封材料;金屬柱位於所述包封材料中;銲料區包括第一部分,其從所述包封材料的頂面延伸至所述包封材料中,其中所述金屬柱環繞所述銲料區的所述第一部分;以及元件晶粒,位於所述包封材料中。在一實施例中,所述銲料區的所述第一部分的所有側壁均與所述金屬柱的側壁接觸。在一實施例中,所述封裝體更包括聚合物材料,其延伸至所述金屬柱中,且所述銲料區的所述第一部分的側壁與所述聚合物材料的側壁接觸。在一實施例中,所述封裝體更包括鈦層,其位於所述金屬柱與所述聚合物材料之間。在一實施例中,所述銲料區的所述第一部分與所述金屬柱形成界面,並且所述界面是圓形的。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知,其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識
到,這些等效構造並不悖離本發明的精神及範圍,而且其可在不悖離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
400:製造流程
402、404、406、408、410、412、414、416、418、420、422、424:步驟
Claims (9)
- 一種封裝體,包括:第一晶片;多個金屬柱,環繞所述第一晶片,其中所述多個金屬柱包括第一下凹式金屬柱;聚合物,位於所述第一下凹式金屬柱中;包封材料,環繞所述第一晶片與所述多個金屬柱,其中所述第一下凹式金屬柱包括含銅部分,所述含銅部分包括具有相同材料的第一部分與第二部分,所述第一部分的頂面低於所述第二部分的頂面;重分佈結構,位於所述第一晶片與所述多個金屬柱的下方且電性連接至所述第一晶片與所述多個金屬柱;多個連接墊,位於所述重分佈結構的下方且電性連接至所述重分佈結構;以及第二晶片,電性連接至所述第一下凹式金屬柱。
- 如申請專利範圍第1項所述的封裝體,其中所述第二部分環繞所述第一部分。
- 如申請專利範圍第2項所述的封裝體,其中所述第一下凹式金屬柱包括:含鈦層,位於所述聚合物與所述第二部分之間。
- 如申請專利範圍第1項所述的封裝體,更包括銲料區,其中所述銲料區與所述第一下凹式金屬柱的所述第一部分接觸,且所述銲料區將所述第二晶片接合至所述第一晶片。
- 一種封裝體的製造方法,包括:在載體上形成犧牲區,其中所述犧牲區的材料包括聚合物;在所述載體上形成金屬柱,其中所述金屬柱與至少一部分的所述犧牲區重疊;將所述金屬柱與所述犧牲區包封在包封材料中;從所述載體上卸下所述金屬柱、所述犧牲區以及所述包封材料;以及移除所述至少一部分的所述犧牲區以形成凹陷,所述凹陷自所述包封材料的表面水平延伸至所述包封材料中。
- 如申請專利範圍第5項所述的封裝體的製造方法,其中所述金屬柱與整個所述犧牲區重疊,所述金屬柱延伸超出所述犧牲區的邊緣,且所述凹陷延伸進入部分的所述金屬柱,並被所述部分的所述金屬柱環繞。
- 如申請專利範圍第5項所述的封裝體的製造方法,其中所述金屬柱與所述犧牲區的第一部分重疊,且所述犧牲區更包括第二部分,所述第二部分延伸超出所述金屬柱的邊緣,且所述包封材料的側壁暴露出所述凹陷。
- 一種封裝體,包括: 包封材料;金屬柱,位於所述包封材料中;銲料區,包括第一部分,所述第一部分從所述包封材料的頂面延伸至所述金屬柱中,其中所述金屬柱環繞所述銲料區的所述第一部分;元件晶粒,位於所述包封材料中;以及聚合物材料,延伸至所述金屬柱中,且所述銲料區的所述第一部分的側壁與所述聚合物材料的側壁接觸。
- 如申請專利範圍第8項所述的封裝體,更包括鈦層,其位於所述金屬柱與所述聚合物材料之間。
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US20170032977A1 (en) * | 2015-07-31 | 2017-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution lines having stacking vias |
Also Published As
Publication number | Publication date |
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US10515901B2 (en) | 2019-12-24 |
US11075168B2 (en) | 2021-07-27 |
US20190103362A1 (en) | 2019-04-04 |
CN109585388A (zh) | 2019-04-05 |
US20200035608A1 (en) | 2020-01-30 |
US20210327816A1 (en) | 2021-10-21 |
TW201916300A (zh) | 2019-04-16 |
US11901302B2 (en) | 2024-02-13 |
KR20190038253A (ko) | 2019-04-08 |
CN109585388B (zh) | 2020-09-25 |
KR102051056B1 (ko) | 2019-12-02 |
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